PHILIPS SAA8113HL

INTEGRATED CIRCUITS
DATA SHEET
SAA8113HL
Digital PC-camera signal processor
Preliminary specification
File under Integrated Circuits, IC22
1999 Sep 27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
QUICK REFERENCE DATA
6
BLOCK DIAGRAM
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
Black offset preprocessing
Y, CR and CB separation
RGB processing
Y processing
RGB to UV conversion
UV processing
Display function
Analog output processing
Measurement engine
VH reference and window timing and control
Pulse pattern generator
Miscellaneous functions
Mode control
Microcontroller
Audio amplifier
I2C-bus interface
9
LIMITING VALUES
10
THERMAL CHARACTERISTICS
11
OPERATING CHARACTERISTICS
12
ELECTRICAL CHARACTERISTICS
13
APPLICATION INFORMATION
14
PACKAGE OUTLINE
15
SOLDERING
15.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
15.2
15.3
15.4
15.5
16
DEFINITIONS
17
LIFE SUPPORT APPLICATIONS
18
PURCHASE OF PHILIPS I2C COMPONENTS
1999 Sep 27
2
SAA8113HL
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
1
SAA8113HL
FEATURES
• High precision digital processing with 10-bit input
• Medium resolution complementary mosaic CCD
sensors PAL or NTSC (interlaced mode only)
• Internal PPG, dedicated to SHARP, TOSHIBA and
PANASONIC sensors
• Integrated microcontroller (80C51) for control loops
Auto Optical Black (AOB), Auto White Balance (AWB)
and Auto Exposure (AE)
3
The SAA8113HL is a 2nd generation camera Digital
Signal Processor (DSP) designed for low-cost DTV
applications. It integrates the DSP core, the Pulse Pattern
Generator (PPG), the 80C51 microcontroller and the
VDAC in one IC. It is the successor of the SAA8110G,
dedicated to analog output cameras.
• Black offset preprocessing
• RGB separation
• RGB processing (colour correction matrix,
programmable knee and gamma)
• Separate Y-processing (saturation concealment,
programmable knee and gamma)
The SAA8113HL must be applied together with an analog
front-end that includes a Correlated Double Sampling
(CDS), an Automatic Gain Control (AGC) and an
Analog-to-Digital Converter (ADC). This may be the
TDA8786 or the TDA8784.
• RGB to UV conversion (including down-sampling filters)
• Noise reduction in Y and UV
• Display function for system evaluation
The PPG generates the timing pulses to drive medium
resolution PAL/NTSC complementary mosaic CCD
sensors (512 × 492 NTSC and 512 × 582 PAL).
• Analog output processing, including PAL/NTSC encoder
and 9-bit Video Digital-to-Analog Converter (VDAC)
• Measurement engine (prepared for AE and AWB
features)
The input of the DSP is 10 bits with a maximum pixel
frequency equal to 9.66 MHz. The DSP core processes
this sensor signal to a standard video output signal. The
SAA8113HL output is an analog CVBS video signal.
• Miscellaneous functions, e.g. power management, 7-bit
Control DAC (CDAC) serial interface with preprocessing
• VH reference and window timing for internal use
The microcontroller provides the settings for the IC
registers from EEPROM at power-up or reset and controls
the AWB, AE and AOB loops. It also provides a hardware
I2C-bus interface, so the microcontroller can be used as an
I2C-bus slave. The software code is embedded in an
internal ROM but it is also possible to use a combined data
and address bus, connected to an external program
EPROM.
• Master I2C-bus interface for communication with an
external EEPROM (containing the default settings)
• Slave I2C-bus interface for communication with an
external microcontroller
• Parallel interface for communication with an external
EPROM (for ROM code debugging)
• Integrated audio amplifier.
2
GENERAL DESCRIPTION
A built-in power management function allows the power
dissipation to be optimized.
APPLICATIONS
• Low-cost desktop video applications
• Videophone systems.
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
SAA8113HL
LQFP100
1999 Sep 27
DESCRIPTION
plastic low profile quad flat package; 100 leads;
body 14 × 14 × 1.4 mm
3
VERSION
SOT407-1
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
5 QUICK REFERENCE DATA
Measured over full voltage and temperature range.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3.0
3.3
3.6
V
VDDA
analog supply voltage
3.0
3.3
3.6
V
IDD(tot)
total supply current
VDDD = 3.3 V
−
60
−
mA
VI
input voltage
3.0 V < VDDD < 3.6 V
low-voltage TTL compatible
V
note 1
5 V tolerant, TTL compatible
V
3.0 V < VDDD < 3.6 V
low-voltage TTL compatible
V
note 1
VO
output voltage
5 V tolerant, TTL compatible
V
fclk
clock frequency input
−
38
−
MHz
δ
duty factor of fclk
−
50
−
%
Ptot
total power dissipation
−
200
250
mW
Tstg
storage temperature
Tamb = 25 °C
−55
−
+150
°C
Tamb
ambient temperature
0
25
70
°C
Tj
junction temperature
−40
−
+125
°C
Tamb = 70 °C
Note
1. This concerns pins SCL and SDA.
1999 Sep 27
4
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8
13, 17, 23,
40, 57, 64, 71, 83
54, 56, 95
3
9
12, 19, 20, 21,
41, 60, 61, 72, 82
2
24, 25
29
2
26, 28
27
AUDIO BUFFER
Y
PROCESSING
CCD9
to
CCD0
85 to 94
10
Y
AND
CR, CB
OFFSET
PREPROCESSING
DISPLAY
RGB
TO
UV
RGB
PROCESSING
SEPARATION
ANALOG
OUTPUT
(PREPROCESSING) VDAC
UV
PROCESSING
18
22
OUTAB
VDOBCVBS
DECREF
PAL/NTSC
ENCODER
49 to 42
M2 to M0
1 to 3
8 50
MODE
CONTROL
AND
CLOCK
GENERATOR
XOSC
3
XIN
5
XOUT
CDACOUT
RBIASCDAC
62
63
MEASUREMENT ENGINE
VH
REFERENCE
TIMING
32
P0
INTERNAL
MICROCONTROLLER
INTERFACE
58
PSEN
39 to 33
P3
P2
PPG
SENSOR/PREPROCESSOR TIMING AND CONTROL
11
80C51
P4
AD14 to AD8
7
10
MICROCONTROLLER
59
CDAC MISCELLANEOUS
FUNCTIONS
P0.7 to P0.0
ALE
Philips Semiconductors
55, 96
AGND5,
AGND6
VDDA4
Digital PC-camera signal processor
2
MICIAB,
VCOMAB
AGND1 to AGND4,
AGND7 to AGND11
DGND1 to DGND3
BLOCK DIAGRAM
VDDA5 to VDDA9
6
VDDA1 to VDDA3,
VDDD2
book, full pagewidth
1999 Sep 27
VDDD1,
P1
14
15
SCLE
SDAE
SCL
SDA
5, 6, 7, 8
8
4
100, 99,
98, 97,
84, 51, 6
30, 31
65, 66,
67, 68, 3
69, 70
75,
74, 76
4
73
79, 80,
77, 78
SAA8113HL
81
4
2
16, 53
9
KNOB3
to
KNOB0
52
FCE312
KNOB4
FH1,
FH2,
FR
OFDX
BCP,
DCP,
FS,
FCDS
CLK1
Fig.1 Block diagram.
T1,
INT1
RESET
EA
Preliminary specification
V1X,
VH1X,
V2X,
V3X,
VH3X,
V4X
SAA8113HL
SDATA,
SCLK,
STROBE,
STDBY,
SMP,
LED,
OUTBVEN,
OUTGAIN
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
7
SAA8113HL
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
M2
1
I
test mode control signal bit 2
M1
2
I
test mode control signal bit 1
M0
3
I
test mode control signal bit 0
KNOB4
4
I
input connected to DSP core
KNOB3
5
I/O
I/O connected to internal 80C51
KNOB2
6
I/O
I/O connected to internal 80C51
KNOB1
7
I/O
I/O connected to internal 80C51
KNOB0
8
I/O
I/O connected to internal 80C51
RESET
9
I
Power-on reset
SCLE
10
O
master I2C-bus clock output to control EEPROM
SDAE
11
I/O
master I2C-bus data I/O to control EEPROM
AGND1
12
I
analog ground 1 for output buffers
VDDA1
13
I
analog supply voltage 1 for output buffers
SCL
14
I
slave I2C-bus clock input
SDA
15
I/O
T1
16
I
Timer 1 for internal 80C51
slave I2C-bus data I/O
VDDA2
17
I
analog supply voltage 2 for DAC output buffer
VDOBCVBS
18
O
VDAC output buffer for CVBS signal
AGND2
19
I
analog ground 2 for DAC output buffer
AGND3
20
I
analog ground 3 for analog DAC core and band gap (connected to substrate)
AGND4
21
I
analog ground 4 for analog DAC core and band gap (not connected to substrate)
DECREF
22
O
decoupled pin for reference voltage HIGH
VDDA3
23
I
analog supply voltage 3 for analog DAC core and band gap
MICIAB
24
I
microphone input audio buffer
VCOMAB
25
I
common voltage for audio buffer
AGND5
26
I
analog ground 5 for audio buffer (not connected to substrate)
OUTAB
27
O
output audio buffer
AGND6
28
I
analog ground 6 for audio buffer (connected to substrate)
VDDA4
29
I
analog supply voltage 4 for audio buffer
OUTBVEN
30
O
output to enable the bias voltage of the microphone for the audio buffer
OUTGAIN
31
O
output to control the gain factor of an external audio buffer
PSEN
32
O
program store enable; read strobe for external program memory (active LOW)
AD8
33
O
address bit 8 for external program memory (PROM)
AD9
34
O
address bit 9 for external program memory (PROM)
AD10
35
O
address bit 10 for external program memory (PROM)
AD11
36
O
address bit 11 for external program memory (PROM)
AD12
37
O
address bit 12 for external program memory (PROM)
AD13
38
O
address bit 13 for external program memory (PROM)
AD14
39
O
address bit 14 for external program memory (PROM)
VDDA5
40
I
analog supply voltage 5 for output buffers
1999 Sep 27
6
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SYMBOL
SAA8113HL
PIN
I/O
DESCRIPTION
AGND7
41
I
P0.0
42
I/O
port 0 bidirectional bit 0 for external program memory data I/O (PROM)
P0.1
43
I/O
port 0 bidirectional bit 1 for external program memory data I/O (PROM)
P0.2
44
I/O
port 0 bidirectional bit 2 for external program memory data I/O (PROM)
P0.3
45
I/O
port 0 bidirectional bit 3 for external program memory data I/O (PROM)
P0.4
46
I/O
port 0 bidirectional bit 4 for external program memory data I/O (PROM)
P0.5
47
I/O
port 0 bidirectional bit 5 for external program memory data I/O (PROM)
P0.6
48
I/O
port 0 bidirectional bit 6 for external program memory data I/O (PROM)
P0.7
49
I/O
port 0 bidirectional bit 7 for external program memory data I/O (PROM)
ALE
50
O
address latch enable pulse for external latch
LED
51
O
output to drive LED
analog ground 7 for output buffers
EA
52
I
external access select bit for internal 80C51 (active LOW)
INT1
53
I
interrupt 1 for internal 80C51
DGND1
54
I
digital ground 1 for input buffers, predrivers and the digital core
VDDD1
55
I
digital supply voltage 1 for input buffers, predrivers and the digital core
DGND2
56
I
digital ground 2 for input buffers, predrivers and the digital core
VDDA6
57
I
analog supply voltage 6 for CDAC
RBIASCDAC
58
O
bias resistor for CDAC
CDACOUT
59
O
output CDAC
AGND8
60
I
analog ground 8 for CDAC
AGND9
61
I
analog ground 9 for 38 MHz (fundamental) crystal oscillator
XIN
62
I
oscillator input
XOUT
63
O
oscillator output
VDDA7
64
I
analog supply voltage 7 for 38 MHz (fundamental) crystal oscillator
V1X
65
O
vertical CCD transfer pulse 1X
VH1X
66
O
vertical CCD load pulse H1X
V2X
67
O
vertical CCD transfer pulse 2X
V3X
68
O
vertical CCD transfer pulse 3X
VH3X
69
O
vertical CCD load pulse H3X
V4X
70
O
vertical CCD transfer pulse 4X
VDDA8
71
I
analog supply voltage 8 for output buffers
AGND10
72
I
analog ground 10 for output buffers
OFDX
73
O
overflow drain pulse for shutter control
FH2
74
O
horizontal CCD transfer pulse F2
FH1
75
O
horizontal CCD transfer pulse F1
FR
76
O
CCD output amplifier reset pulse (TDA8786 or TDA8784)
FS
77
O
CCD output level sample and hold pulse (TDA8786 or TDA8784)
FCDS
78
O
reference level sample and hold pulse (TDA8786 or TDA8784)
BCP
79
O
black pixel clamp pulse (TDA8786 or TDA8784)
DCP
80
O
dummy pixel clamp pulse (TDA8786 or TDA8784)
CLK1
81
O
pixel clock to preprocessor (TDA8786 or TDA8784)
1999 Sep 27
7
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SYMBOL
SAA8113HL
PIN
I/O
DESCRIPTION
AGND11
82
I
analog ground 11 for output buffers
VDDA9
83
I
analog supply voltage 9 for output buffers
SMP
84
O
switch mode pulse for DC-to-DC power supply
CCD9
85
I
(preprocessed) AD-converted CCD signal bit 9
CCD8
86
I
(preprocessed) AD-converted CCD signal bit 8
CCD7
87
I
(preprocessed) AD-converted CCD signal bit 7
CCD6
88
I
(preprocessed) AD-converted CCD signal bit 6
CCD5
89
I
(preprocessed) AD-converted CCD signal bit 5
CCD4
90
I
(preprocessed) AD-converted CCD signal bit 4
CCD3
91
I
(preprocessed) AD-converted CCD signal bit 3
CCD2
92
I
(preprocessed) AD-converted CCD signal bit 2
CCD1
93
I
(preprocessed) AD-converted CCD signal bit 1
CCD0
94
I
(preprocessed) AD-converted CCD signal bit 0
DGND3
95
I
digital ground 3 for input buffers, predrivers and the digital core
VDDD2
96
I
digital supply voltage 2 for input buffers, predrivers and the digital core
STDBY
97
O
standby control output to TDA8786 or TDA8784
STROBE
98
O
strobe to TDA8786 or TDA8784
SCLK
99
O
serial clock to TDA8786 or TDA8784
SDATA
100
O
serial data to TDA8786 or TDA8784
1999 Sep 27
8
Philips Semiconductors
Preliminary specification
76 FR
77 FS
78 FCDS
79 BCP
81 CLK1
80 DCP
82 AGND11
83 VDDA9
84 SMP
85 CCD9
86 CCD8
87 CCD7
88 CCD6
SAA8113HL
89 CCD5
90 CCD4
91 CCD3
92 CCD2
93 CCD1
94 CCD0
95 DGND3
96 VDDD2
97 STDBY
98 STROBE
100 SDATA
handbook, full pagewidth
99 SCLK
Digital PC-camera signal processor
M2
1
75 FH1
M1
2
74 FH2
M0
3
73 OFDX
KNOB4
4
72 AGND10
KNOB3
5
71 VDDA8
KNOB2
6
70 V4X
KNOB1
7
69 VH3X
KNOB0
8
68 V3X
RESET
9
67 V2X
SCLE 10
66 VH1X
SDAE 11
65 V1X
64 VDDA7
AGND1 12
SAA8113HL
VDDA1 13
63 XOUT
SCL 14
62 XIN
SDA 15
61 AGND9
T1 16
60 AGND8
VDDA2 17
59 CDACOUT
58 RBIASCDAC
VDOBCVBS 18
AGND2 19
57 VDDA6
AGND3 20
56 DGND2
AGND4 21
55 VDDD1
DECREF 22
54 DGND1
VDDA3 23
53 INT1
MICIAB 24
52 EA
VCOMAB 25
Fig.2 Pin configuration.
1999 Sep 27
9
ALE 50
P0.7 49
P0.6 48
P0.5 47
P0.4 46
P0.3 45
P0.2 44
P0.1 43
P0.0 42
AGND7 41
VDDA5 40
AD14 39
AD13 38
AD12 37
AD11 36
AD10 35
AD9 34
AD8 33
PSEN 32
OUTGAIN 31
OUTBVEN 30
VDDA4 29
AGND6 28
OUTAB 27
AGND5 26
51 LED
FCE313
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8
8.1
SAA8113HL
FUNCTIONAL DESCRIPTION
advantage of the full code range. Otherwise, the black
level is fixed by settings that are downloaded through the
serial interface.
Black offset preprocessing
The CCD signal contains additional pixels outside the
active window, which are used to measure the reference
black level. These pixels are located in the optical black
window, whose position can be set through the serial
interface. The optical black level can be adjusted by the
microcontroller in order to proceed rapidly. In this case, the
microcontroller directly adjusts the analog preprocessing
clamp included in the TDA8786 or TDA8784 and takes
handbook, full pagewidth
8.2
Y, CR and CB separation
For each pixel value, this block (see Fig.3) generates the
three components: the luminance signal Y and the two
colour signals CR (2R − G) and CB (2B − G). Two line
memories are required for this function. This block also
provides vertical contour and white clip information.
LINE
MEMORY
Y
CR
LINE
MEMORY
RGB
COLOUR
SEPARATION
CB
white clip
Yvertical contour
CCD inputs
10
FCE314
Fig.3 Y, CR and CB separation diagram.
1999 Sep 27
10
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.3
SAA8113HL
• Separate gain controls for R and B signals dedicated to
white balance control. The colour temperature can be
adjusted independently of the colour matrix.
RGB processing
The RGB processing (see Fig.4) includes several features:
• Colour space matrix to handle different types of colour
sensors. The result is an optimum colour reproduction
through the minimization of colour errors. The default
matrix coefficients (positive or negative) can be adjusted
through an external interface.
• Knee function (compression factor and knee point are
adjustable).
• Adjustable gamma function to compensate for the
non-linearity of display devices.
• Separate and adjustable black offsets for
R, G and B signals.
handbook, full pagewidth
The RGB path has a reduced bandwidth (less than
1 MHz), which is required for CVBS output.
LPF
Y
COLOUR
MATRIX
LPF
CB
Rgain
+
×
Gblack
LPF
CR
Rblack
KNEE
R
KNEE
+
GAMMA
GAMMA
G
Bblack
Bgain
+
×
KNEE
GAMMA
B
FCE315
Fig.4 RGB processing diagram.
1999 Sep 27
11
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.4
SAA8113HL
• Black offset
Y processing
The separate Y processing (see Fig.5) includes the
following features:
• Pre-gain control to adjust the Y signal with respect to the
gamma range
• Saturation concealment to reduce the typical saturation
distortion
• Knee function (compression factor and knee point are
adjustable)
• Contour processing to improve picture sharpness
• Adjustable gamma function
• Noise reduction
• Gain control.
handbook, full pagewidth
CONTOUR PROCESSING
AND
NOISE REDUCTION
Yvertical contour
Y
SATURATION
CONCEALMENT
Yblack
Ypre-gain
+
×
+
KNEE
GAMMA
Ygain
×
Y
FCE316
Fig.5 Y processing diagram.
8.5
RGB to UV conversion
8.7
After R, G and B processing, the data path is converted to
U and V signals (see Fig.1). As a result of the reduced
bandwidth, the Y signal is only used as an input for control
loop purposes (measurement engine).
8.6
As an optional feature and for software debugging, it is
possible to visualize:
• Eight display bars (assigned via the microcontroller)
• Several measurement engine inputs.
UV processing
The chrominance processing consists of a noise reduction
by coring and the UV gain control.
1999 Sep 27
Display function
12
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.8
SAA8113HL
Analog output processing
twice the pixel clock and digitally prefiltered to keep the
external analog filter simple. The block also contains an
adjustable luminance clipper.
The analog output processing (see Fig.6) contains a
PAL/NTSC encoder to transform the YUV data path to the
CVBS output. The YUV input signals are up-sampled to
handbook, full pagewidth
Y
Y
U
PAL/NTSC
ENCODER
C
VDAC
MIX
VDOBCVBS
V
sync, blank, scaling, levels
FCE317
Fig.6 Analog output processing.
8.9
Measurement engine
8.10
The measurement engine performs data measurements
on a field basis to get inputs for the AE and AWB control
loops of the microcontroller. Up to 16 programmable
windows can be used for the measurement. There are two
down-samplers to prepare the data for two separate
accumulators. It is possible to proceed with eight different
measurements per field (odd and even fields separately).
An internal RAM workspace is used for data handling
operation.
VH reference and window timing and control
This block generates internal control signals for different
purposes:
• Vertical, horizontal and field references (VD, HD and FI)
for PAL or NTSC sensors
• Specification of the active window and the optical black
window
• Specification of the measurement window grid with
respect to the active window
• Specification of the vertical position of the display bars,
see Section 8.7.
All these specifications can be controlled through the serial
interface.
1999 Sep 27
13
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.11
SAA8113HL
Pulse pattern generator
The PPG is dedicated to the medium resolution sensors
with complementary mosaic colour filters (512 × 492
NTSC and 512 × 582 PAL) described in Table 1.
Figs. 11 and 12 show the PPG outputs.
The PPG generates timing pulses (Figs. 7 to 10) for
driving the CCD sensor (including the vertical driver) and
pulses for the preprocessor TDA8786 or TDA8784
(correlated double sampling and black clamping).
Table 1
Medium resolution CCD sensors driven by the internal PPG; note 1
BRAND
SHARP
TOSHIBA
SHARP low voltage
PANASONIC
FORMAT
TYPE
PAL 1/4”
LZ2423A
NTSC 1/4”
LZ2413A
PAL 1/5”
LZ2523
NTSC 1/5”
LZ2513
PAL 1/4”
TCD5391AP
NTSC 1/4”
TCD5381AP
PAL 1/4”
LZ2425
NTSC 1/4”
LZ2415
PAL 1/4”
MN37210FP
PAL 1/4”
MN37201FP
NTSC 1/4”
MN37110FP
NTSC 1/4”
MN37101FP
Note
1. All sensors are used with the vertical driver: NEC µPD16510.
The PPG includes special features:
• A charge reset is possible in every active line during the horizontal line blanking and multiple times during the vertical
blanking
• A fast shutter interface is available.
1999 Sep 27
14
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
4 × f pixel
handbook, full pagewidth
XIN
FH1
FH2
FCDS
FS_narrow
FS_wide
FR_wide
FR_narrow
delay (typ. 7 ns)
FR_narrow_delayed
delay (typ. 7 ns)
FR_wide_delayed
FCE318
Fig.7 High speed pulse timing (CCD sensor and preprocessor).
1999 Sep 27
15
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
NTSC line 17
PAL line 19
NTSC line 18
PAL line 20
NTSC line 279
PAL line 331
NTSC line 280
PAL line 332
HD
V1X
V2X
V3X
V4X
VH1X
VH3X
HD
V1X
V2X
V3X
V4X
VH1X
VH3X
FCE319
Fig.8 SHARP and TOSHIBA CCD sensors/vertical drivers.
1999 Sep 27
16
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
NTSC line 17
PAL line 19
NTSC line 18
PAL line 20
NTSC line 279
PAL line 331
NTSC line 280
PAL line 332
HD
V1X
V2X
V3X
V4X
VH3X
HD
V1X
V2X
V3X
V4X
VH3X
FCE320
Fig.9 SHARP low-voltage CCD sensors/vertical drivers.
1999 Sep 27
17
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
NTSC line 17
PAL line 19
NTSC line 18
PAL line 20
NTSC line 279
PAL line 331
NTSC line 280
PAL line 332
HD
V1X
V2X
V3X
V4X
VH1X
VH3X
OFDX
HD
V1X
V2X
V3X
V4X
VH1X
VH3X
OFDX
FCE321
Fig.10 PANASONIC CCD sensors/vertical drivers.
1999 Sep 27
18
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full HD
pagewidth
V1X
V2X
V3X
V4X
OFDX
BCP
DCP
FCE322
Fig.11 SHARP, all types, PPG output.
handbook, full pagewidth
HD
V1X
V2X
V3X
V4X
OFDX
BCP
DCP
FCE323
Fig.12 PANASONIC PPG output.
1999 Sep 27
19
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.12
SAA8113HL
• A 3-wire serial bus transfers the settings from the
microcontroller to the preprocessor (TDA8786 or
TDA8784).
Miscellaneous functions
• Power consumption: it is possible to switch the DSP off
without switching off the microcontroller.
• Oscillator frequency: a 7-bit CDAC tunes the oscillator
frequency according to the external quartz frequency to
guarantee the typical value of 38 MHz.
8.13
This block controls the operational modes of the
SAA8113HL: application or test modes, see Table 2. For a
smooth adaptability, it is possible to bypass the main
modules.
The control digital value is downloaded through the
serial interface.
Table 2
Mode control
Mode control
M2
M1
M0
EA
MODE
0
0
0
EA; note 1
0
0
1
−
0
1
0
−
application mode with bypassed microcontroller
0
1
1
0
application mode with bypassed PPG and microcontroller
application mode
application mode with bypassed PPG
Note
1. EA can be high or low, according to the application (high is for internal ROM access, low for external access).
8.14
Microcontroller
The microcontroller includes the following features:
• 16 kbyte internal ROM
The embedded microcontroller is basically an 80C654
core (80C51 family) with four ports. Its functionality is
standard, except that the core has no clock divided by 2
and the ports are dedicated input, output or I/O ports.
Ports P0 and P2 are available for connection to a
debugger or to an external program EPROM. The
microcontroller controls the AOB, the AE and the AWB
loops and downloads the settings for the DSP registers
from EEPROM at power-up or reset. Table 3 lists the
80C51 Standard Function Registers.
1999 Sep 27
• 256 byte RAM
• Hardware I2C-bus interface for communication with
external microcontroller: SDA and SCL
• Software I2C-bus interface for communication with
external EEPROM containing DSP settings: SDAE and
SCLE
• Four I/O pins which can be used as human interface
(knobs): P1.0, P1.1, P1.2 and P1.3.
20
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 3
SAA8113HL
80C51 Standard Function Registers
SFR
NAME
DESCRIPTION
SFR
ADDRESS
DATA
BIT 7
DATA
BIT 6
DATA
BIT 5
DATA
BIT 4
DATA
BIT 3
DATA
BIT 2
DATA
BIT 1
DATA
BIT 0
B
B register
F0H
B7
B6
B5
B4
B3
B2
B1
B0
ACC
accumulator
E0H
ACC7
ACC6
ACC5
ACC4
ACC3
ACC2
ACC1
ACC0
SIADR
serial interface address
DBH
SA6
SA5
SA4
SA3
SA2
SA1
SA0
GC
SIDAT
serial interface data
DAH
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
SISTA
serial interface status
D9H
ST7
ST6
ST5
ST4
ST3
0
0
0
SICON
serial interface control
D8H
CR2
ENS1
STA
STO
SI
AA
CR1
CR0
PSW
program status word
D0H
CY
AC
F0
RS1
RS0
OV
−
P
P4
port 4
C7H
−
−
−
−
−
−
−
STBY
IP
interrupt priority
B8H
−
IP6
IP5
IP4
PT1
PX1
PT0
PX0
P3
port 3
B0H
RDN
WRN
T1
T0
INT1
INT0
FI
CRST
IE
interrupt enable
A8H
EA
IE6
IE5
IE4
ET1
EX1
ET0
EX0
P2
port 2
A0H
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
P1
port 1
90H
SDA
SCL
SDAE
SCLE
P1.3
P1.2
P1.1
P1.0
TH1
timer HIGH 1
8DH
−
−
−
−
−
−
−
−
TH0
timer HIGH 0
8CH
−
−
−
−
−
−
−
−
TL1
timer LOW 1
8BH
−
−
−
−
−
−
−
−
TL0
timer LOW 0
8AH
−
−
−
−
−
−
−
−
TMOD
timer mode
89H
GATE
C/T
M1
M0
Gate
C/T
M1
M0
TCON
timer control
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
PCON
power control
87H
−
−
−
−
−
−
PD
IDL
DPH
data pointer HIGH
83H
−
−
−
−
−
−
−
−
DPL
data pointer LOW
82H
−
−
−
−
−
−
−
−
SP
stack pointer
81H
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
P0
port 0
80H
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
8.15
Audio amplifier
8.16
An analog audio amplifier is integrated in the SAA8113HL.
Its gain can be adjusted between a high (45 dB typical)
and a low (13 dB typical) value through the serial interface.
1999 Sep 27
I2C-bus interface
Table 4 gives the command list of the I2C-bus interface.
21
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 4
SAA8113HL
Command list
ADD
NAME
FUNCTION
FORMAT
RANGE
0
CONTROL0
see Table 5 for explanation
byte
n.a.
1
CONTROL1
see Table 7 for explanation
byte
n.a.
2
CONTROL2
see Table 8 for explanation
byte
n.a.
3
OB_STARTL_F0
first line optical black window in field 0
byte
[0 to 255]
4
OB_STARTL_F1
first line optical black window in field 1
byte
256 + [0 to 255]
5
OB_STARTP
first pixel optical black window
byte
[0 to 255]
6
OB_PE_F0
fixed optical black level for even pixel in field 0
byte
[0 to 127]
7
OB_PO_F0
fixed optical black level for odd pixel in field 0
byte
[0 to 127]
8
OB_PE_F1
fixed optical black level for even pixel in field 1
byte
[0 to 127]
9
OB_PO_F1
fixed optical black level for odd pixel in field 1
byte
[0 to 127]
10
COL_MAT_P11
colour matrix coefficient p11
byte
[−128 to 127]/16
11
COL_MAT_P12
colour matrix coefficient p12
byte
[−128 to 127]/16
12
COL_MAT_P13
colour matrix coefficient p13
byte
[−128 to 127]/16
13
COL_MAT_P21
colour matrix coefficient p21
byte
[−128 to 127]/16
14
COL_MAT_P22
colour matrix coefficient p22
byte
[−128 to 127]/16
15
COL_MAT_P23
colour matrix coefficient p23
byte
[−128 to 127]/16
16
COL_MAT_P31
colour matrix coefficient p31
byte
[−128 to 127]/16
17
COL_MAT_P32
colour matrix coefficient p32
byte
[−128 to 127]/16
18
COL_MAT_P33
colour matrix coefficient p33
byte
[−128 to 127]/16
19
R_BLACK
fixed R-black level offset
byte
[−128 to 127]
20
G_BLACK
fixed G-black level offset
byte
[−128 to 127]
21
B_BLACK
fixed B-black level offset
byte
[−128 to 127]
22
COL_MAT_RGAIN
colour matrix R-gain factor
byte
[0 to 255]/128
23
COL_MAT_BGAIN
colour matrix B-gain factor
byte
[0 to 255]/64
24
THR_LUM
threshold luminance for fader
byte
[0 to 255]
25
THR_COLOR
threshold colour for fader
byte
[0 to 255]
26
Y_BLACK
fixed Y-black level offset
byte
[−128 to 127]
27
K1
gain correction for Y path
byte
[0 to 255]/128
28
RGB_KNEE_OFFSET
offset for RGB knee
byte
[0 to 255]
29
Y_KNEE_OFFSET
offset for Y knee
byte
[0 to 255]
30
RGB_GAMMA_BALANCE
gamma multiplication factor (for RGB data path)
6 bits
[0 to 63]/64
31
Y_GAMMA_BALANCE
gamma multiplication factor (for Y data path)
6 bits
[0 to 63]/64
32
KCOMB
vertical contour comb filter coefficient (MS)
4 bits
[0 to 7]/8
VCGAIN
vertical contour gain (LS)
4 bits
[0 to 15]/16
33
CLDLEV
contour level dependency level
byte
[0 to 255]/2
34
HCLGAIN
horizontal contour BPF low gain (LS)
4 bits
[0 to 15]/16
HCHGAIN
horizontal contour BPF high gain (MS)
4 bits
[0 to 15]/16
35
CNCLEV
contour noise coring level
6 bits
[0 to 63]
36
CONGAIN
contour gain factor; see Table 9
2 bits
[0 to 63]/16
37
VU_VALUE 1
length of VU_Bar 1
byte
2 × [0 to 255]
1999 Sep 27
22
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
ADD
NAME
SAA8113HL
FUNCTION
FORMAT
RANGE
38
VU_VALUE 2
length of VU_Bar 2
byte
2 × [0 to 255]
39
VU_VALUE 3
length of VU_Bar 3
byte
2 × [0 to 255]
40
VU_VALUE 4
length of VU_Bar 4
byte
2 × [0 to 255]
41
VU_VALUE 5
length of VU_Bar 5
byte
2 × [0 to 255]
42
VU_VALUE 6
length of VU_Bar 6
byte
2 × [0 to 255]
43
VU_VALUE 7
length of VU_Bar 7
byte
2 × [0 to 255]
44
VU_VALUE 8
length of VU_Bar 8
byte
2 × [0 to 255]
45
Y_DISPLAY_OFFSET
display offset (to be used with D_Contour)
byte
4 × [0 to 255]
46
UNCLEV
U (chrominance) noise coring level
byte
[0 to 255]/4
47
VNCLEV
V (chrominance) noise coring level
byte
[0 to 255]/4
48
YGAIN
Y (luminance) gain factor
byte
[0 to 255]/128
49
UGAIN
U (B-Y) gain factor
byte
[0 to 255]/128
50
VGAIN
V (R-Y) gain factor
byte
[0 to 255]/128
51
CTR_UPD_LINE
number of line for DB-update control registers
byte
[0 to 255]
52
BURST_LEVEL
burst level colour burst
byte
[0 to 255]
53
A
AWB_A (Measurement Engine)
byte
[−128 to 127]/128
54
B
AWB_B (Measurement Engine)
byte
[−128 to 127]/128
55
C
AWB_C (Measurement Engine)
byte
[−128 to 127]/128
56
D
AWB_D (Measurement Engine)
byte
[−128 to 127]/128
57
E
AWB_E (Measurement Engine)
6 bits
[0 to 63]
58
F
AWB_F (Measurement Engine)
6 bits
[0 to 63]
59
HIGHLIGHTTHR
highlight threshold (Measurement Engine)
byte
[0 to 255]
60
ME_RESSCALE
ME sync + ME result scale (ME); see Table 10
4 bits
n.a.
61
DISP_CNTRL
control bits for display function; see Table 11
byte
n.a.
62
YDISPLEV
luminance display level in display function
byte
[0 to 255]
63
DMWSEL
display measurement window select;
see Table 13
byte
n.a.
64
ANA_WHITECLIP
white clip limiter level for analog outputs
byte
256 + [0 to 255]
65
PRE_SI_LSB
control data for analog processing
byte
[0 to 255]
66
PRE_SI_MSB
control data and address for analog processing;
see Table 14
5 bits
[0 to 63]
67
SMP_CNTRL
control for switch mode power supply
byte
[0 to 255]
68
CDAC_DATA
CDAC data (7-bit); see Table 15
7 bits
[0 to 127]
69
BLANKLEV
blanking level in analog output
byte
[0 to 255]
70
BL-SETUP
setup level in analog output
byte
[0 to 255]
71
PRE_PROC_DEL
control compensation delay w.r.t. preprocessing
4 bits
[0 to 15]
72
BCP_START
B clamp pulse start
byte
[0 to 255]
73
BCP_STOP
B clamp pulse stop
byte
[0 to 255]
74
DCP_START
D clamp pulse start
byte
[0 to 255]
75
DCP_STOP
D clamp pulse stop
byte
[0 to 255]
76
EE_CONTROL_LSB
E Exposure LSB
byte
[0 to 255]
1999 Sep 27
23
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
ADD
NAME
SAA8113HL
FUNCTION
FORMAT
RANGE
[0 to 255]
77
EE_CONTROL_MSB
E Exposure MSB
byte
78
MISC_CONTROL
miscellaneous control bits; see Table 16
5 bits
[0 to 31]
79
FPIX_ACT
number of first active pixel on a line
byte
[0 to 255]
80
LPIX_ACT_LSB
number of last active pixel on a line
byte
[0 to 255]
81
FLINE_ACT_F0
number of first active line in field 0
byte
[0 to 255]
82
LLINE_ACT_F0
number of last active line in field 0
byte
[0 to 255]
83
FLINE_ACT_F1
number of first active line in field 1
byte
[0 to 255]
84
LLINE_ACT_F1
number of last active line in field 1
byte
[0 to 255]
85
ACT_LINES_MSB
MSBs of active line numbers; see Table 17
byte
[0 to 255]
86
PPG_POL_SEL
select polarity of the PPG output signals;
see Table 18
5 bits
n.a.
128
ME_DPCC_A0_H_F1
ME data path control code A 0_H field 1
byte
[0 to 255]
129
ME_DPCC_A0_L_F1
ME data path control code A 0_L field 1
byte
[0 to 255]
130
ME_DPCC_B0_H_F1
ME data path control code B 0_H field 1
byte
[0 to 255]
131
ME_DPCC_B0_L_F1
ME data path control code B 0_L field 1
byte
[0 to 255]
132
ME_DPCC_A1_H_F1
ME data path control code A 1_H field 1
byte
[0 to 255]
133
ME_DPCC_A1_L_F1
ME data path control code A 1_L field 1
byte
[0 to 255]
134
ME_DPCC_B1_H_F1
ME data path control code B 1_H field 1
byte
[0 to 255]
135
ME_DPCC_B1_L_F1
ME data path control code B 1_L field 1
byte
[0 to 255]
136
ME_DPCC_A2_H_F1
ME data path control code A 2_H field 1
byte
[0 to 255]
137
ME_DPCC_A2_L_F1
ME data path control code A 2_L field 1
byte
[0 to 255]
138
ME_DPCC_B2_H_F1
ME data path control code B 2_H field 1
byte
[0 to 255]
139
ME_DPCC_B2_L_F1
ME data path control code B 2_L field 1
byte
[0 to 255]
140
ME_DPCC_A3_H_F1
ME data path control code A 3_H field 1
byte
[0 to 255]
141
ME_DPCC_A3_L_F1
ME data path control code A 3_L field 1
byte
[0 to 255]
142
ME_DPCC_B3_H_F1
ME data path control code B 3_H field 1
byte
[0 to 255]
143
ME_DPCC_B3_L_F1
ME data path control code B 3_L field 1
byte
[0 to 255]
144
ME_DPCC_A0_H_F2
ME data path control code A 0_H field 2
byte
[0 to 255]
145
ME_DPCC_A0_L_F2
ME data path control code A 0_L field 2
byte
[0 to 255]
146
ME_DPCC_B0_H_F2
ME data path control code B 0_H field 2
byte
[0 to 255]
147
ME_DPCC_B0_L_F2
ME data path control code B 0_L field 2
byte
[0 to 255]
148
ME_DPCC_A1_H_F2
ME data path control code A 1_H field 2
byte
[0 to 255]
149
ME_DPCC_A1_L_F2
ME data path control code A 1_L field 2
byte
[0 to 255]
150
ME_DPCC_B1_H_F2
ME data path control code B 1_H field 2
byte
[0 to 255]
151
ME_DPCC_B1_L_F2
ME data path control code B 1_L field 2
byte
[0 to 255]
152
ME_DPCC_A2_H_F2
ME data path control code A 2_H field 2
byte
[0 to 255]
153
ME_DPCC_A2_L_F2
ME data path control code A 2_L field 2
byte
[0 to 255]
154
ME_DPCC_B2_H_F2
ME data path control code B 2_H field 2
byte
[0 to 255]
155
ME_DPCC_B2_L_F2
ME data path control code B 2_L field 2
byte
[0 to 255]
156
ME_DPCC_A3_H_F2
ME data path control code A 3_H field 2
byte
[0 to 255]
157
ME_DPCC_A3_L_F2
ME data path control code A 3_L field 2
byte
[0 to 255]
1999 Sep 27
24
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
ADD
NAME
SAA8113HL
FUNCTION
FORMAT
RANGE
byte
[0 to 255]
158
ME_DPCC_B3_H_F2
ME data path control code B 3_H field 2
159
ME_DPCC_B3_L_F2
ME data path control code B 3_L field 2
byte
[0 to 255]
160
ME_RES_A0_H
ME data path result accuA 0_H
byte
[0 to 255]
161
ME_RES_A0_L
ME data path result accuA 0_L
byte
[0 to 255]
162
ME_RES_B0_H
ME data path result accuB 0_H
byte
[0 to 255]
163
ME_RES_B0_L
ME data path result accuB 0_L
byte
[0 to 255]
164
ME_RES_A1_H
ME data path result accuA 1_H
byte
[0 to 255]
165
ME_RES_A1_L
ME data path result accuA 1_L
byte
[0 to 255]
166
ME_RES_B1_H
ME data path result accuB 1_H
byte
[0 to 255]
167
ME_RES_B1_L
ME data path result accuB 1_L
byte
[0 to 255]
168
ME_RES_A2_H
ME data path result accuA 2_H
byte
[0 to 255]
169
ME_RES_A2_L
ME data path result accuA 2_L
byte
[0 to 255]
170
ME_RES_B2_H
ME data path result accuB 2_H
byte
[0 to 255]
171
ME_RES_B2_L
ME data path result accuB 2_L
byte
[0 to 255]
172
ME_RES_A3_H
ME data path result accuA 3_H
byte
[0 to 255]
173
ME_RES_A3_L
ME data path result accuA 3_L
byte
[0 to 255]
174
ME_RES_B3_H
ME data path result accuB 3_H
byte
[0 to 255]
175
ME_RES_B3_L
ME data path result accuB 3_L
byte
[0 to 255]
176
ME_SUBRES_A0_H
ME data path sub-result accuA 0_H
byte
[0 to 255]
177
ME_SUBRES_A0_L
ME data path sub-result accuA 0_L
byte
[0 to 255]
178
ME_SUBRES_B0_H
ME data path sub-result accuB 0_H
byte
[0 to 255]
179
ME_SUBRES_B0_L
ME data path sub-result accuB 0_L
byte
[0 to 255]
180
ME_SUBRES_A1_H
ME data path sub-result accuA 1_H
byte
[0 to 255]
181
ME_SUBRES_A1_L
ME data path sub-result accuA 1_L
byte
[0 to 255]
182
ME_SUBRES_B1_H
ME data path sub-result accuB 1_H
byte
[0 to 255]
183
ME_SUBRES_B1_L
ME data path sub-result accuB 1_L
byte
[0 to 255]
184
ME_SUBRES_A2_H
ME data path sub-result accuA 2_H
byte
[0 to 255]
185
ME_SUBRES_A2_L
ME data path sub-result accuA 2_L
byte
[0 to 255]
186
ME_SUBRES_B2_H
ME data path sub-result accuB 2_H
byte
[0 to 255]
187
ME_SUBRES_B2_L
ME data path sub-result accuB 2_L
byte
[0 to 255]
188
ME_SUBRES_A3_H
ME data path sub-result accuA 3_H
byte
[0 to 255]
189
ME_SUBRES_A3_L
ME data path sub-result accuA 3_L
byte
[0 to 255]
190
ME_SUBRES_B3_H
ME data path sub-result accuB 3_H
byte
[0 to 255]
191
ME_SUBRES_B3_L
ME data path sub-result accuB 3_L
byte
[0 to 255]
192
ME_WIN_START_0
simple window 0 (Vstart, Hstart)
4 bits
[0 to 15]
193
ME_WIN_STOP_0
simple window 0 (Vstop, Hstop)
4 bits
[0 to 15]
194
ME_WIN_START_1
simple window 1 (Vstart, Hstart)
4 bits
[0 to 15]
195
ME_WIN_STOP_1
simple window 1 (Vstop, Hstop)
4 bits
[0 to 15]
196
ME_WIN_START_2
simple window 2 (Vstart, Hstart)
4 bits
[0 to 15]
197
ME_WIN_STOP_2
simple window 2 (Vstop, Hstop)
4 bits
[0 to 15]
198
ME_WIN_START_3
simple window 3 (Vstart, Hstart)
4 bits
[0 to 15]
1999 Sep 27
25
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
ADD
NAME
SAA8113HL
FUNCTION
FORMAT
RANGE
4 bits
[0 to 15]
199
ME_WIN_STOP_3
simple window 3 (Vstop, Hstop)
200
ME_WIN_START_4
simple window 4 (Vstart, Hstart)
4 bits
[0 to 15]
201
ME_WIN_STOP_4
simple window 4 (Vstop, Hstop)
4 bits
[0 to 15]
202
ME_WIN_START_5
simple window 5 (Vstart, Hstart)
4 bits
[0 to 15]
203
ME_WIN_STOP_5
simple window 5 (Vstop, Hstop)
4 bits
[0 to 15]
204
ME_WIN_START_6
simple window 6 (Vstart, Hstart)
4 bits
[0 to 15]
205
ME_WIN_STOP_6
simple window 6 (Vstop, Hstop)
4 bits
[0 to 15]
206
ME_WIN_START_7
simple window 7 (Vstart, Hstart)
4 bits
[0 to 15]
207
ME_WIN_STOP_7
simple window 7 (Vstop, Hstop)
4 bits
[0 to 15]
208
ME_WIN_START_8
simple window 8 (Vstart, Hstart)
4 bits
[0 to 15]
209
ME_WIN_STOP_8
simple window 8 (Vstop, Hstop)
4 bits
[0 to 15]
210
ME_WIN_START_9
simple window 9 (Vstart, Hstart)
4 bits
[0 to 15]
211
ME_WIN_STOP_9
simple window 9 (Vstop, Hstop)
4 bits
[0 to 15]
212
ME_WIN_START_10
simple window 10 (Vstart, Hstart)
4 bits
[0 to 15]
213
ME_WIN_STOP_10
simple window 10 (Vstop, Hstop)
4 bits
[0 to 15]
214
ME_WIN_START_11
simple window 11 (Vstart, Hstart)
4 bits
[0 to 15]
215
ME_WIN_STOP_11
simple window 11 (Vstop, Hstop)
4 bits
[0 to 15]
216
ME_WIN_START_12
simple window 12 (Vstart, Hstart)
4 bits
[0 to 15]
218
ME_WIN_STOP_12
simple window 12 (Vstop, Hstop)
4 bits
[0 to 15]
219
ME_WIN_START_13
simple window 13 (Vstart, Hstart)
4 bits
[0 to 15]
220
ME_WIN_STOP_13
simple window 13 (Vstop, Hstop)
4 bits
[0 to 15]
221
ME_WIN_START_14
simple window 14 (Vstart, Hstart)
4 bits
[0 to 15]
222
ME_WIN_STOP_14
simple window 14 (Vstop, Hstop)
4 bits
[0 to 15]
223
ME_RAM_DUMMY_H
dummy read/write (additional RAM storage for
80C51)
byte
n.a.
224
ME_RAM_DUMMY_L
dummy read/write (additional RAM storage for
80C51)
byte
n.a.
225
HIGHLIGHTCOUNT_H
highlight counter H
byte
[0 to 255]
226
HIGHLIGHTCOUNT_L
highlight counter L
byte
[0 to 255]
227
AWBCOUNT_H
AWB counter H
byte
[0 to 255]
228
AWBCOUNT_L
AWB counter L
byte
[0 to 255]
229
ME_OB_PO_F0
measured optical black pixel odd field 0;
see Table 19
byte
[0 to 127]
230
ME_OB_PE_F0
measured optical black pixel even field 0;
see Table 20
byte
[0 to 127]
231
ME_OB_PO_F1
measured optical black pixel odd field 1;
see Table 21
byte
[0 to 127]
232
ME_OB_PE_F1
measured optical black pixel even field 1;
see Table 22
byte
[0 to 127]
254
DUMMY_READ
dummy read
byte
[0 to 255]
255
DUMMY_WRITE
dummy write
byte
[0 to 255]
1999 Sep 27
26
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 5
SAA8113HL
Register details: address 0 CONTROL0
BIT
NAME
CONTROL0.0
FUNCTION
not used
CONTROL0.1
RGB_KNEE_K
compression factor for RGB_KNEE; see Table 6
CONTROL0.2
RGB_KNEE_K
compression factor for RGB_KNEE; see Table 6
CONTROL0.3
PIX_PHASE
toggle phase for pixel in colour separation
CONTROL0.4
LINE_PHASE
toggle phase for line in colour separation
CONTROL0.5
INTERLINE_PHASE
toggle colour filter structure (interline)
CONTROL0.6
not used
CONTROL0.7
not used
Table 6
Truth table for bits CONTROL0.1 and CONTROL0.2
BIT NUMBER
COMPRESSION FACTOR
2
1
0
0
1/8
0
1
1/4
1
0
3/8
1
1
1/2
Table 7
Register details: address 1 CONTROL1
BIT
NAME
FUNCTION
CONTROL1.0
FR_WIDE
FR wide/narrow
CONTROL1.1
FR_SHIFT
FR shifted/unshifted
CONTROL1.2
FS_WIDE
FS wide/narrow
CONTROL1.3
DUALPOWER
SHARP dual power/other sensor select
CONTROL1.4
SHARP
SHARP/PANASONIC sensor select
CONTROL1.5
PAL_NTSC
choose between PAL/NTSC
CONTROL1.6
BCP_MODE
select BCP mode 1/0
CONTROL1.7
CP_TOGGLE
carrier phase toggle/not toggle
Table 8
Register details: address 2 CONTROL2
BIT
NAME
FUNCTION
CONTROL2.0
CATCH_CCD
catch CCD data/normal operation
CONTROL2.1
HFE_BYPASS
high frequency enhancer bypass/active
CONTROL2.2
Y_TEST
select y_test from RGB2(Y)UV instead of Y on/off
CONTROL2.3
MOD_BYPASS
chrominance modulator bypass/active
CONTROL2.4
DOUBLE_C
scale chrominance with factor 2 on/off
CONTROL2.5
Y_SEL
select as luminance input (F0) Yae/yn
CONTROL2.6
VCONTOUR_LPF
switch vertical contour LPF on/off
CONTROL2.7
FADER IMPL
select fader implementation n1/n2
1999 Sep 27
27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 9
SAA8113HL
Register details: address 36 CONGAIN
NAME
FUNCTION
CONGAIN.0 to CONGAIN.5
contour gain factor (0 to 63/16)
CONGAIN.6
contour gain fading off/on
Table 10 Register details: address 60 ME_RESSCALE
NAME
FUNCTION
ME_RESSCALE.0 to ME_RESSCALE.2 ME result scaler selection (0, 2, 4, 8 and 16)
MECNTRL.3
ME synchronization (synchronize field/frame toggle of Measurement
Engine)
Table 11 Register details: address 61 DISP_CNTRL
NAME
FUNCTION
DISP_CNTRL.0 and DISP_CNTRL.1
V display level
DISP_CNTRL.2 and DISP_CNTRL.3
U display level
DISP_CNTRL.4
contrast reduction/level insertion
DISP_CNTRL.5 to DISP_CNTRL.7
display signal selection code; see Table 12
Table 12 Truth table for bits DISP_CNTRL5 to DISP_CNTRL7]
BIT NUMBER
SELECT CODE
7
6
5
0
0
0
no display
0
0
1
D_VU
0
1
0
D_WC
0
1
1
D_AWBVAL
1
0
0
D_HIGHLIGHT
1
0
1
D_MWG
1
1
X
D_CONTOUR
Table 13 Register details: address 63 DMWSEL
NAME
FUNCTION
DMWSEL.0
display measurement window A for line 0
DMWSEL.1
display measurement window B for line 0
DMWSEL.2
display measurement window A for line 1
DMWSEL.3
display measurement window B for line 1
DMWSEL.4
display measurement window A for line 2
DMWSEL.5
display measurement window B for line 2
DMWSEL.6
display measurement window A for line 3
DMWSEL.7
display measurement window B for line 3
1999 Sep 27
28
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
Table 14 Register details: address 66 PRE_SI_MSB
NAME
FUNCTION
PRE_SI_MSB.0 and PRE_SI_MSB.1
control data bits d8 and d9
PRE_SI_MSB.2 to PRE_SI_MSB.4
control address bits a0 to a2
Table 15 Register details: address 68 CDAC_DATA
NAME
CDAC_DATA.0 to CDAC_DATA.6
FUNCTION
CDAC data bits 0 to 6
Table 16 Register details: address 78 MISC_CONTROL
NAME
FUNCTION
MISC_CONTROL.0
LED off/on
MISC_CONTROL.1
audio on/off
MISC_CONTROL.2
audio gain low (13 dB), high (45 dB)
MISC_CONTROL.3
select 1 kΩ mode (output impedance)
MISC_CONTROL.4
standby on/off
MISC_CONTROL.5 to MISC_CONTROL.7
reserved for miscellaneous additional functions
Table 17 Register details: address 85 ACT_LINES_MSB
NAME
FUNCTION
ACT_LINES_MSB.0 and ACT_LINES_MSB.1 bits 8 and 9 for last active pixel number on a line
ACT_LINES_MSB.2 and ACT_LINES_MSB.3 bits 8 and 9 for last active line number in field 0
ACT_LINES_MSB.4 and ACT_LINES_MSB.5 bits 8 and 9 for first active line number in field 1/frame
ACT_LINES_MSB.6 and ACT_LINES_MSB.7 bits 8 and 9 for last active line number in field 1/frame
Table 18 Register details: address 86 PPG_POL_SEL
Name
FUNCTION
PPG_POL_SEL.0
select polarity of PPG output FR as inverted/non-inverted
PPG_POL_SEL.1
select polarity of PPG output FS as inverted/non-inverted
PPG_POL_SEL.2
select polarity of PPG output FCDS as inverted/non-inverted
PPG_POL_SEL.3
select polarity of PPG output FH1 as inverted/non-inverted
PPG_POL_SEL.4
select polarity of PPG output FH2 as inverted/non-inverted
Table 19 Register details: address 229 ME_OB_PO_F0
FUNCTION
NAME BIT NO
ME_OB_PO_F0.0 to ME_OB_PO_F0.6
CCD_CATCH = 0
CCD_CATCH = 1
ME_OB_PO_F00 to ME_OB_PO_F06
CCD2 to CCD8
0
CCD9
ME_OB_PO_F0.7
1999 Sep 27
29
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
Table 20 Register details: address 230 ME_OB_PE_F0
FUNCTION
NAME BIT NO
ME_OB_PE_F0.0 and ME_OB_PE_F0.1
ME_OB_PE_F0.2 to ME_OB_PE_F0.6
CCD_CATCH = 0
CCD_CATCH = 1
ME_OB_PE_F00 and ME_OB_PE_F01
CCD0 and CCD1
ME_OB_PE_F02 to ME_OB_PE_F06
0
ME_OB_PE_F0.7
KNOB4
Table 21 Register details: address 231 ME_OB_PO_F1
FUNCTION
NAME BIT NO
ME_OB_PO_F1.0 to ME_OB_PO_F1.6
CCD_CATCH = 0
CCD_CATCH = 1
ME_OB_PO_F16 to ME_OB_PO_F10
‘undefined’
ME_OB_PO_F1.7
0
Table 22 Register details: address 232 ME_OB_PE_F1
FUNCTION
NAME BIT NO
ME_OB_PE_F1.0 to ME_OB_PE_F1.6
CCD_CATCH = 01
CCD_CATCH = 1
ME_OB_PE_F16 to ME_OB_PE_F10
‘undefined’
ME_OB_PE_F1.7
0
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); note 1 unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDDn
digital supply voltages 1 and 2 for input buffer and
pre-drivers
−0.5
+4.0
V
VDDAn
analog supply voltages 1, 5, 8 and 9 for output buffers
−0.5
+4.0
V
VDDA2
analog supply voltage 2 for DAC output buffer
−0.5
+4.0
V
VDDA3
analog supply voltage 3 for analog DAC core and band gap
−0.5
+4.0
V
VDDA4
analog supply voltage 4 for audio buffer
−0.5
+4.0
V
VDDA6
analog supply voltage 6 for CDAC
−0.5
+4.0
V
VDDA7
analog supply voltage 7 for 38 MHz crystal oscillator
−0.5
+4.0
V
DGNDn
digital grounds 1, 2, and 3 for input buffer and predrivers
−0.5
+4.0
V
AGNDn
analog grounds 1, 7, 10 and 11 for output buffers
−0.5
+4.0
V
AGND2
analog ground 2 for DAC output buffer
−0.5
+4.0
V
AGND3
analog ground 3 for analog DAC core and band gap,
connected to substrate
−0.5
+4.0
V
AGND4
analog ground 4 for analog DAC core and band gap, not
connected to substrate
−0.5
+4.0
V
AGND6
analog ground 6 for audio buffer connected to substrate
−0.5
+4.0
V
AGND5
analog ground 5 for audio buffer not connected to substrate
−0.5
+4.0
V
AGND8
analog ground 8 for CDAC
−0.5
+4.0
V
AGND9
analog ground 9 for 38 MHz crystal oscillator
−0.5
+4.0
V
1999 Sep 27
30
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SYMBOL
SAA8113HL
PARAMETER
CONDITIONS
MIN.
−0.5
MAX.
UNIT
VI, VO
input or output voltage
−0.5
+5.5
V
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
0
70
°C
Tj
junction temperature
−40
+125
°C
note 2
VDD + 0.5 V
Notes
1. Stress beyond these levels may cause permanent damage to the device.
2. For 5 V-tolerant buffers.
10 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
56
K/W
in free air
11 OPERATING CHARACTERISTICS
VDDD = VDDA = 3.3 V ±10%; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
General supplies
VDDD
digital supply voltage
3.0
3.3
3.6
V
VDDA
analog supply voltage
3.0
3.3
3.6
V
DGND
digital ground
−0.3
0.0
+0.3
V
AGND
analog ground
−0.3
0.0
+0.3
V
IDDD
digital supply current
Tamb = 25 °C
−
45
−
mA
IDDA
analog supply current
Tamb = 25 °C
−
15
−
mA
Tamb
ambient temperature
0
25
70
°C
Data and control inputs or I/Os (CCD9 to CCD0, M2 to M0, KNOB4 to KNOB0, RESET, EA, T1, INT1 and
P0.7 to P0.0)
VIL
LOW-level input voltage
−
−
0.2VDDD V
VIH
HIGH-level input voltage
0.8VDDD
−
−
V
Data and control outputs or I/Os (SMP, LED, OUTBVEN, OUTGAIN, SDATA, SCLK, SDAE, SCLE, STROBE,
STNDBY, FR, OFDX, AD14 to AD8 and P0.7 to P0.0)
VOL
LOW-level output voltage
0
−
0.4
V
VOH
HIGH-level output voltage
0.85VDDD
−
VDDD
V
Control outputs (FH1, FH2, FS, FCDS and CLK1)
VOL
LOW-level output voltage
note 1
−
−
0.8
V
VOH
HIGH-level output voltage
note1
2.2
−
−
V
Control outputs (V1X, V2X, V3X, V4X, VH1X and VH3X)
VOL
LOW-level output voltage
notes 2 and 3
−
−
0.8
V
VOH
HIGH-level output voltage
notes 2 and 3
2.6
−
−
V
1999 Sep 27
31
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SYMBOL
SAA8113HL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Control outputs (BCP and DCP)
VOL
LOW-level output voltage
−
−
0.6
V
VOH
HIGH-level output voltage
2.2
−
−
V
3
−
−
mA
5
−
−
mA
Switch Mode Pulse for DC-to-DC power supply (SMP)
IO
output current
Output to drive the LED (LED)
IO
output current
Notes
1. Connected to HCT (lab resources) with VIH(min) = 2.0 V and VIL(max) = 0.8 V.
2. Connected to NEC µPD16510 with VIH(min) = 0.8VDD and VIL(max) = 0.3VDD.
3. Connected to ACT/HCT (lab resources) with VIH(min) = 2.0 V and VIL(max) = 0.8 V.
12 ELECTRICAL CHARACTERISTICS
VDDD = VDDA = 3.3 V ±10%; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNIT
CDAC specifications
LOAD
RL
load resistance
10
−
−
kΩ
CL
load capacitance
−
−
100
pF
0.00
TRANSFER FUNCTION
VO
DC output voltage
at code ‘0’
−
0.05
V
DC output voltage
at code ‘127’
VDDD − 0.2 VDDD − 0.12
VDDD
V
RES
resolution
−
7
−
bit
DNL
differential non-linearity
−
−
1/2
LSB
INL
integral non-linearity
−
−
1
LSB
CR
conversion rate
−
−
60
Hz
BA
analog bandwidth
−
−
60
Hz
Ro
output resistance
−
13
−
Ω
SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP
tPD
propagation delay time
to 50% value
−
−
75
ns
tst1
settling time
10% to 90%
full-scale
−
−
120
ns
tst2
settling time
to ±1 LSB
−
−
156
ns
1999 Sep 27
32
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SYMBOL
SAA8113HL
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNIT
VDAC specifications
LOAD
RL
load resistance
with high
impedance
(1 kΩ mode)
0.8
1
−
kΩ
CL
load capacitance
with high
impedance
(1 kΩ mode)
−
−
5
pF
TRANSFER FUNCTION
Vo(0)
DC output voltage at code ‘0’
0.15
0.212
0.30
V
Vo(436)
DC output voltage at code ‘436’
1.45
1.55
1.75
V
VRL(p-p)
output voltage (436 to 0)
(peak-to-peak value)
1.15
1.288
1.6
V
RES
resolution
−
9
−
bit
DNL
differential non-linearity
−
−
1⁄
2
LSB
INL
integral non-linearity
−
−
1
LSB
CR
conversion rate
−
19
−
MHz
fCLK
clock frequency
−
19
−
MHz
BA
analog bandwidth
−
6.5
−
MHz
S/N
signal-to-noise ratio
43
46
−
dB
note 1
dynamic
THD
total harmonic distortion
−
−50
−42
dB
Ro
output resistance
−
2
3
Ω
SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP
tPD
propagation delay time
to 50% value
−
−
13
ns
tst1
settling time
10% to 90%
full-scale
−
−
15
ns
tst2
settling time
to ±1 LSB
−
−
50
ns
Audio amplifier specifications
LOAD
RL
load resistance
5
−
−
kΩ
CL
load capacitance
−
5
−
pF
TRANSFER FUNCTION
Vi(p-p)
nominal input level (peak-to-peak value)
−
5.6
−
mV
A1
amplification at high level
43
44.8
47
dB
141.2
173.7
223.8
A2
amplification at low level
11
12.5
14
3.5
4.2
5.0
−
0.97
−
VOH(p-p)
1999 Sep 27
nominal output level at high level
(peak-to-peak value)
33
dB
V
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SYMBOL
SAA8113HL
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNIT
VOL(rms)
nominal output level at high level
(RMS value)
−
0.34
−
V
Vo2(p-p)
nominal output level at low level
(peak-to-peak value)
−
23.5
−
mV
Vo2(rms)
nominal output level at low level
(RMS value)
−
8.3
−
mV
Vo(max)(p-p)
maximum output level (peak-to-peak value)
2
−
−
V
S/N
signal-to-noise ratio
40
−
−
dB
THD
total harmonic distortion at high level
−
−60
−50
dB
Zi
input impedance
5
−
−
kΩ
Zo
output impedance
−
−
100
Ω
B-3 dB
frequency range (−3 dB)
0.1
−
20
kHz
reference current
−
25
−
µA
BIASSING
Iref
Data input/output timing; (see Fig.13)
DATA INPUTS RELATED TO XIN (CCD9 TO CCD0 AND KNOB4)
tsu(i)(D)
data input setup time
note 2
9.5
−
−
ns
th(i)(D)
data input hold time
note 2
10.5
−
−
ns
DATA OUTPUTS RELATED TO XIN (OUTBVEN, OUTGAIN, SMP, LED, SDATA, SCLK, STROBE AND STNDBY)
th(o)(D)
data output delay time
note 2
−
5
7
ns
td(o)(D)
data output hold time
note 2
−
3
5.5
ns
PPG high speed pulse timing; CL = 10 pF (see Fig.14)
td1
FH2 fall time delay w.r.t. the rising edge of
FH1
−3
0
+3
ns
td2
FH2 rise time delay w.r.t. the falling edge of
FH1
−3
0
+3
ns
td3
FR fall time delay w.r.t. the rising edge of
FH1
0
1
2
ns
td3_delayed
FR_delayed fall time delay w.r.t. the rising
edge of FH1
7
8
10
ns
td4_wide
FCDS fall time delay w.r.t. the rising edge of
FR_wide
1
2
3
ns
td4_narrow
FCDS fall time delay w.r.t. the rising edge of
FR_narrow
14
15
16
ns
td5
FH1 fall time delay w.r.t. the rising edge of
FCDS
0
1
2
ns
td6_wide
FH1 rise time delay w.r.t. the rising edge of
FS_wide
0
1
2
ns
td6_narrow
FH1 rise time delay w.r.t. the rising edge of
FS_narrow
14
15
16
ns
td7
CLK1 fall time delay w.r.t. the rising edge of
FH1
0
1
2
ns
1999 Sep 27
34
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SYMBOL
SAA8113HL
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNIT
td8
CLK1 rise time delay w.r.t. the falling edge of
FH1
0
1
2
ns
twFH1
FH1 pulse width
−
53
−
ns
trFH1
FH1 rise time
−
4
−
ns
tfFH1
FH1 fall time
−
4
−
ns
twFH2
FH2 pulse width
−
53
−
ns
trFH2
FH2 rise time
−
4
−
ns
tfFH2
FH2 fall time
−
4
−
ns
twFR_wide
FR_wide pulse width
−
26
−
ns
twFR_narrow
FR_narrow pulse width
−
13
−
ns
trFR
FR rise time
−
4
−
ns
tfFR
FR fall time
−
4
−
ns
twFCDS
FCDS pulse width
−
26
−
ns
trFCDS
FCDS rise time
−
4
−
ns
tfFCDS
FCDS fall time
−
4
−
ns
twFS_wide
FS_wide pulse width
−
40
−
ns
twFS_narrow
FS_narrow pulse width
−
26
−
ns
trFS
FS rise time
−
4
−
ns
tfFS
FS fall time
−
4
−
ns
twCLK1
CLK1 pulse width
−
53
−
ns
Notes
1. Full code swing of colour bar with maximum headroom of 16.4%. Above code ‘436’, the DAC works but the settling
time will decrease gradually.
2. The internal clock signal used in the DSP core is derived from XIN: XIN divided by 4.
1999 Sep 27
35
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
tf
handbook, full pagewidth
tr
90%
XIN
90%
50%
10%
10%
t h(i)(D)
t su(i)(D)
data input
t h(o)(D)
t d(o)(D)
90%
90%
10%
10%
data output
FCE324
Fig.13 Data input/output timing.
1999 Sep 27
36
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
t wFH1
handbook, full pagewidth
50%
FH1
50%
50%
t d1
t d2
50%
FH2
50%
t wFH2
50%
FCDS
t wFCDS
t d5
t wFS
t d6_wide
FS_wide
t d6_narrow
FS_narrow
t d3
t wFR
t d4_wide
50%
FR_wide
t d4_narrow
50%
FR_narrow
t d3_delayed
50%
FR_wide_delayed
50%
FR_narrow_delayed
t d7
CLK1
t d8
50%
50%
t wCLK1
FCE325
Fig.14 PPG high speed pulse timing diagram.
1999 Sep 27
37
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
13 APPLICATION INFORMATION
handbook, full pagewidth
SAA8113HL
analog
preprocessing
optics
CCD sensor
PAL/NTSC
(medium
resolution)
DRIVERS
CDS,
AGC
AND
ADC
DIGITAL
SIGNAL
PROCESSING
LPF
VDAC
PREPROCESSING,
TIMING AND
CONTROL
parallel
interface
SENSOR,
TIMING AND
CONTROL
serial
interface
MODE CONTROL
AND
CLOCK GENERATOR
program
PROM
settings
EEPROM
MICROCONTROLLER
I2C-bus
interface
80C51
CDAC
HUMAN INTERFACE
AUDIO AMPLIFIER
FCE326
Fig.15 Application block diagram.
1999 Sep 27
38
analog
(CVBS)
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
14 PACKAGE OUTLINE
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SOT407-1
c
y
X
A
51
75
50
76
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
Lp
L
pin 1 index
100
detail X
26
1
25
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.5
1.3
0.25
0.28
0.16
0.18
0.12
14.1
13.9
14.1
13.9
0.5
HD
HE
16.25 16.25
15.75 15.75
L
Lp
v
w
y
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
1.15
0.85
7
0o
1.15
0.85
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-12-19
97-08-04
SOT407-1
1999 Sep 27
EUROPEAN
PROJECTION
39
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
If wave soldering is used the following conditions must be
observed for optimal results:
15 SOLDERING
15.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
15.2
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.3
15.4
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
1999 Sep 27
Manual soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
40
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
15.5
SAA8113HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable(2)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Sep 27
41
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
16 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
17 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Sep 27
42
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
NOTES
1999 Sep 27
43
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For all other countries apply to: Philips Semiconductors,
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 68
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545006/25/01/pp44
Date of release: 1999
Sep 27
Document order number:
9397 750 04816