INTEGRATED CIRCUITS DATA SHEET SAA4700 VPS dataline processor Preliminary specification File under Integrated Circuits, IC02 March 1991 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 FEATURES • Adaptive sync slicer with buffered composite sync output VCS • Adaptive data slicer • Data rate clock regenerator • Field selection and line 16 decoding QUICK REFERENCE DATA • Startcode and biphase check SYMBOL • Data valid output VP supply voltage (pins 15 and 16) 4.5 5 5.5 V IP total supply current − 18 23 mA Vi CVBS CVBS input signal sync-to-white (peak-to-peak value) 0.5 1 1.4 V 0 − +70 °C • Storage of data line information in a 40 bit register bank • I2C-bus transmission GENERAL DESCRIPTION The SAA4700 is a bipolar integrated circuit designed for use in dataline receivers and incorporates a dataline slicer and decoder. The slicer extracts the dataline signal from the video signal and regenerates the data clock. It also provides signals for the decoder in order to decode the binary data that is transmitted in line 16 of every first field of the composite video signal (video programming signal and video recording programming by Teletext, VPS and VPT systems). The decoded information out of words 5 and 11 to 14 is accessed via the built-in I2C-bus interface. This information then can be used for programming a video cassette recorder in order to start and stop a recording of a television program at the correct aligned time, regardless of a delay or extension in the transmission time of the required program. March 1991 Tamb PARAMETER MIN. operating ambient temperature TYP. MAX. UNIT ORDERING AND PACKAGE INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE SAA4700 18 DIL plastic SOT102 (1) Note 1. SOT102-1; 1996 December 4. 2 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 CSO handbook, full pagewidth DAV 0.1 µF (test line 16) 5 4.7 nF CVBS SYNC SEPARATOR SAA4700 12 1 FIELD SELECTOR LINE 16 DECODER DATA SLICER 9 SCL SDA 8 data 40-BIT DATA REGISTER CLOCK REGENERATOR 4.7 nF I2C-BUS CONTROL OUTPUT CONTROLLER 5 INPUT CONTROLLER to VP 7 line 16 4.7 kΩ 75 kΩ (2%) AD = LOW 11 8 2 470 pF 1 nF 6 data 40-BIT DATA LATCH 4 MULTIPLEXER 6 VCS 13 17 18 PLL WITH 5 MHz VCO AND PHASE DETECTOR 22 nF 8.2 kΩ TIME BASE 14 REFERENCE VOLTAGES POWER-ON RESET 3 clock pulse 4 15 0.1 µF 16 n.c. external reset 10 +5 V VP MEH095 Fig.1 Block diagram and test circuit. FUNCTIONAL DESCRIPTION Dataline 16 The information in dataline 16 consists of fifteen 8-bit words; the total information content is shown in Table 1; and the organization of transmitted bytes is shown in Table 2. Out of the fifteen possible 8-bit words the SAA4700 extracts words 5 and 11 to 14. The contents of these words can be read via the built-in I2C-bus interface. The circuit is fully transparent, thus each bit is transferred without modification with only the sequence of words being changed. Words 11 to 14 March 1991 are transmitted first followed by word 5. By evaluating the sliced sync signal the circuit can identify the beginning of dataline 16 in the first field. The dataline decoder stage releases the start code detector. When a correct start code is detected (for timing of start code detection see Fig.3) words 5 and 11 to 14 are decoded, checked for biphase errors and stored in a register bank. If no biphase error has occurred, the contents of the register bank are transferred to a second register bank by the data valid control signal. If the system has been addressed, this transfer will be 3 delayed until the next start or stop condition of the I2C-bus has been received. The last bit of correct information on the dataline remains available until it is read via the I2C-bus. Once the stored information has been read it is considered to be no longer valid and the internal new data flag is reset. Subsequently, if the circuit is addressed, the only VPS data that will be sent back is ”FFF to F”. The same conditions apply after power-up when no data can be read out. New data is available after reception of another error-free dataline 16. Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 PINNING PIN CONFIGURATION SYMBOL PIN DESCRIPTION CVBS 1 video signal input (CVBS from TV) SYNC 2 sync amplitude input (CVBS from TV) GND1 3 analog ground (0 V) GND2 4 digital ground (0 V) Cblack 5 capacitor for black level CSO 6 composite sync output AD 7 address set input SCL 8 SDA RS handbook, halfpage CVBS 1 18 n.c. SYNC 2 17 Cph GND1 3 16 VP2 I2C-bus clock line GND2 4 15 VP1 9 I2C-bus data line Cblack 5 10 reset input active LOW CSO 6 13 Rosc TP 11 test point for line 16 decoder AD 7 12 DAV DAV 12 data available output active LOW SCL 8 11 TP Rosc 13 oscillator resistor for frequency adjustment SDA 9 10 RS CP 14 test point clock pulse VP1 15 +5 V supply voltage (digital part) VP2 16 +5 V supply voltage (analog part) Cph 17 capacitor of phase detector n.c. 18 not connected External reset The circuit provides an internal power-on reset. When using this facility pin 10 should be connected to VP or, if external reset (RESET = LOW) is to be used pin 10 should be prepared by connecting pin 10 via a 10 kΩ pull-up resistor to VP. Reset forces the following: Fig.2 Pin configuration To enable proper storage of the sync value in the decoupling capacitor, the sync generator output resistance should not exceed 1 kΩ. Black level The capacitor connected to pin 5 stores the black level value for the adaptive sync slicer. Composite sync output (CSO) - DAV output to go HIGH (pin 12) A composite sync output signal for customer application is provided (pin 6). - transfer register to “FFF” CVBS input The CVBS signal is applied to the sync separator (pin 2) via a decoupling capacitor and to the data slicer (pin 1) via an RC high-pass filter. March 1991 14 CP MBH796 - I2C-bus not to acknowledge I2C-bus SAA4700 DAV output no valid data is available DAV remains HIGH. A short duration pulse of 1 µs (Fig.5) is inserted at the beginning of dataline 16; it will ensure that a HIGH-to-LOW transmission occurs which can then be used for triggering. 5 MHz VCO and phase detector The resistor connected between pin 13 and VP2 determines the current into the voltage controlled oscillator. The RC network connected to pin 17 acts as a low-pass filter for the phase detector. Power supply The data available output pin 12 is set LOW after an error free dataline 16 is received. DAV returnes to HIGH after the beginning of the next first field. If 4 To prevent crosscoupling the circuit is provided with separate ground and supply pins for analog and digital parts (pins 3, 4, 15 and 16). Philips Semiconductors Preliminary specification VPS dataline processor Table 1 SAA4700 Information per word in dataline 16 word number content 1 run in 2 start code 3 program source identification (binary coded) 4 program source identification (ASCII sequential) 5 sound and VTR control information 6 program/test picture identification 7 internal information exchange 8 address assignment of signal distribution 9 address assignment of signal distribution 10 messages/commands 11 12 VTR control / information 13 14 15 Table 2 reserve VTR control information of dataline 16 VTR CONTROL INFORMATION Word number 5 1 Bit number Label binary 11 8 XXXXXXXX 12 0 7 8 13 15 16 14 23 XXXXXXXX XXXXXXXX XXXXXXXX Word 5: AD Day Month Hour Minute System status code Interrupt code 0 2-channel 0 1 Mono 1 0 Stereo 1 1 2-channel Bit4 Status 1 0 free 0 1 free Special system code 1X00000111111111111111 NC.. .NC PC...PC 1X00000111111110111111 NC.. .NC PC...PC 1X00000111111101111111 Note 1. address range; NC = nation code; PC = program source code; X = 0 or 1 (bit) March 1991 Progr. source Bit2 Status 0 Bit3 Pause code 31 XXXXXXXX Nation (1) Bit1 24 5 NC.. .NC PC...PC Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 0.2 µs handbook, full pagewidth clock signal to time base data to controller run in (word 1) start code (word 2) 1 0 0 0 1 1 0 1 1 0 1 1 word 3 0 0 1 1 1 0 1 0 0 1 0 error start code pulse biphase error pulse (ignored in word 2) MEH097 Fig.3 Timing diagram of start code detection. handbook, full pagewidth white level 0.7 V 0.5 V ±5% 1V sync level 12.5 ±1.5 µs 48 µs Fig.4 Timing diagram of dataline 16; modulation depth 71.4%. March 1991 6 MEH098 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 word 15 word 14 word 13 word 12 word 11 word 10 word 9 word 8 word 6 word 5 word 4 word 3 word 2 CVBS input word 1 12.5 µs word 7 64 µs handbook, full pagewidth 48 µs DAV output 1 µs line 16 start code pulse word 5 latch pulse word 11 latch pulse word 14 latch pulse MEH096 Fig.5 Timing diagram of the data available output and word latch pulses. March 1991 7 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). Ground pins 3 and 4 as well as supply pins 15 and 16 tied together. SYMBOL PARAMETER MIN. MAX. UNIT VP1 supply voltage (pin 15) −0.5 6.0 V VP2 supply voltage (pin 16) −0.5 6.0 V Tstg storage temperature range −20 125 °C Tamb operating ambient temperature range 0 +70 °C THERMAL RESISTANCE SYMBOL PARAMETER Rth j-a MIN. MAX. − from junction to ambient in free air 78 UNIT K/W CHARACTERISTICS VP1 = VP2 = 5 V; Tamb = 25 °C; CVBS signal according to VPS and VPT standard and measurements taken in Fig.1, unless otherwise specified. SYMBOL PARAMETER VP1, VP2 supply voltages (pins 15 and 16) IP total supply current CONDITIONS MIN. TYP. MAX. UNIT 4.5 5 5.5 V I15 + I16 − 18 23 mA CVBS input signal (peak-to-peak value) sync-to-white note 1; Fig.4 0.5 1 1.4 V data input signal (peak-to-peak value, pin 1) line 16; Fig.4 250 500 700 mV CVBS and sync inputs (pins 1 and 2) Vi CVBS Vi data Vi sync sync input signal (peak-to-peak value, pin 2) 100 − 600 mV RS source resistance − − 1 kΩ Composite sync output (pin 6) VOL output voltage LOW − − 0.4 V VOH output voltage HIGH 2.4 − − V IOL output current LOW − − 200 µA IOH output current HIGH − − −500 µA td sync separator delay time − 0.3 − µs − − 0.4 V DAV output (pin 12) note 2 VOL output voltage LOW VOH output voltage HIGH 2.4 − − V IOL output current LOW − − 500 µA IOH output current HIGH − 0.01 1 µA March 1991 8 Philips Semiconductors Preliminary specification VPS dataline processor SYMBOL PARAMETER SAA4700 CONDITIONS MIN. TYP. MAX. UNIT SCL and SDA (pins 8 and 9) VIL input voltage LOW − − 1.5 V VIH input voltage HIGH 3 − − V II input current − − ±10 µA CI input capacitance − − 10 pF VO ACK output voltage during acknowledge on pin 9 − − 0.4 V 0.9VP IOL = 3 mA tr rise time − − 1 µs tf fall time − − 0.3 µs tp L pulse duration LOW 4.7 − − µs tp H pulse duration HIGH 4.0 − − µs SCL clock frequency − − 100 kHz AD set input (pin 7) note 2 VIL input voltage LOW address 23H 0 − 0.4 V VIH input voltage HIGH address 21H 2.4 − VP V RESET input (pin 10) note 2 VIL input voltage LOW reset active − − 0.4 V VIH input voltage HIGH reset non-active 2.4 − − V IIL input current LOW − − −10 µA IIH input current HIGH − 0.01 1 µA Notes to the characteristics 1. With standard sync and data amplitude of 68% to 75% black-white. 2. If the open collector output DAV is used, a pull-up resistor to VP1 is necessary. March 1991 9 Philips Semiconductors Preliminary specification VPS dataline processor handbook, full pagewidth SAA4700 +5 V VP 22 nF 4.7 nF 8.2 kΩ 75 kΩ (2%) 0.1 µF DAV n.c. 18 17 16 15 14 13 12 11 10 6 7 8 9 SCL SDA SAA4700 1 2 4 5 0.1 µF 4.7 nF 1 nF 4.7 kΩ 3 470 pF CSO CVBS MEH135 Fig.6 Application circuit. I2C-BUS FORMAT S SLAVE ADDRESS A DATA A DATA A DATA A DATA A DATA S = start condition SLAVE ADDRESS = 0010 0001 or 0010 0011 for set input AD = HIGH respectively LOW on pin 7 (the circuit is only a slave transmitter) A = acknowledge, generated by the slave or the master DATA = five data bytes, see words in Table 1 P = stop condition respectively non-acknowledge by the microcontroller P Remarks to I2C-bus transmission • the MSB of each word is transmitted first • there is no restriction on the number of words to be transmitted, but if more than five words are requested, the following content will be “FF” continuously. • Normally every dataline transmission has to be ended with STOP condition by non-acknowledge of the controller. March 1991 10 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 PACKAGE OUTLINE DIP18: plastic dual in-line package; 18 leads (300 mil) SOT102-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 10 18 pin 1 index E 1 9 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 1.40 1.14 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 0.85 inches 0.19 0.020 0.15 0.055 0.044 0.021 0.015 0.055 0.044 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.033 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 93-10-14 95-01-23 SOT102-1 March 1991 EUROPEAN PROJECTION 11 Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. March 1991 12