PHILIPS TDA8416

INTEGRATED CIRCUITS
DATA SHEET
TDA8416
TV and VTR stereo/dual sound
processor with integrated filters and
I2C-bus control
Preliminary specification
File under Integrated Circuits, IC02
November 1989
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor with
integrated filters and I2C-bus control
TDA8416
GENERAL DESCRIPTION
The TDA8416 is a processor of stereo/dual language
signals (B/G-standard) for stereo sound television
receivers and VTRs, using the switched-capacitor
technique. The AF signals at the TDA8416 inputs must be
“(L+R)/2” or “language A” on one channel and “R” or
“language B” on the second channel (where L = left and
R = right). The carrier frequency of the second channel is
also modulated by an identification signal (stereo or dual
sound). The device is controlled by a microcomputer via
the two-line, bidirectional I2C-bus.
Features
• Use of the switched-capacitor technique for signal
processing
• Small amount of peripheral components
• Integrated anti-aliasing filters
• Low distortion AF signal handling
• Integrated de-emphasis with a time constant of 50 µs
• Two general purpose output ports
• Full ESD protection
QUICK REFERENCE DATA
PARAMETER
CONDITION
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage (pin 15)
VP
−
12
−
V
Supply current (pin 15)
IP
−
10
−
mA
Vo
−
2
−
V
(S+W)/W
70
−
−
dB
dB
AF output signal (RMS value)
(pins 11 to 14)
Weighted signal-to-noise
ratio of the AF output
signals (CCIR 468/3)
Crosstalk attenuation
stereo mode at
f = 1 kHz
αS
40
−
−
dual sound mode at
f = 40 Hz to 12.5 kHz
αDS
70
−
−
dB
Pilot signal input sensitivity
Vi
−
2.5
−
mV
Total harmonic distortion
THD
−
0.1
−
%
PACKAGE OUTLINE
20-lead DIL; plastic (SOT146); SOT146-1; 1996 November 18.
November 1989
2
Philips Semiconductors
Preliminary specification
TDA8416
Fig.1 Block diagram.
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
November 1989
3
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
Fig.2 Input and output loading diagram.
November 1989
4
TDA8416
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
PINNING
1 Control port C1
2 SDA, serial data line (I2 C-bus)
3 SCL, serial clock line (I2 C-bus)
4 Oscillator input (or quartz)
5 Digital ground (0 V)
6 External AF input (E5)
7 Sound channel input AF2 (E2)
8 Sound channel input AF1 (E1)
9 External AF input (E4)
10 External AF input (E3)
11 Output A4 AF 2 output
12 Output A3 AF 2 output
13 Output A2 AF 1 output
14 Output A1 AF 1 output
15 Supply voltage VP
16 Analogue ground (0 V)
17 Ripple rejection improvement
18 Mute input
19 Control port C2
20 Module address (MAD)
FUNCTIONAL DESCRIPTION
Anti-aliasing filters
Frequency band limitation is performed by a second order Sallen and Key low-pass filter inserted in the AF signal path
and the identification circuit. This limitation is necessary because of the time-discrete signal processing needed to meet
the Nyquist criterium.
Identification
To enable the identification of the transmitted AF signal (mono, stereo or dual sound), the carrier frequency of the second
channel (E2) is also modulated by an identification signal. The identification signal is a 54.6875 kHz pilot carrier signal
which is 50% amplitude modulated by either a 117.4 Hz signal for stereo transmission or by a 274.1 Hz signal for dual
sound transmission.
The identification section of the circuit consists of a 54 kHz high-pass filter followed by a gain controlled amplifier with an
AM demodulator. The total gain of the high-pass filter and the amplifier is approximately 56 dB. The demodulated
identification signal is filtered by the identification band-pass filters, (117.4 Hz for stereo transmission, 274.1 Hz for dual
sound transmission). The output from either filter is converted to a DC signal by a peak detector and the necessary
hysteresis is performed by a Schmitt-trigger. The resultant DC output signals indicate the status of the transmitter (mono,
stereo or dual sound).
November 1989
5
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
De-matrix and de-emphasis
Depending on the results of the identification circuit (mono, stereo or dual sound) the AF signals at the inputs E1 and E2
are converted to the signals at E1* and E2* as listed in Table 1.
Table 1
Transmitter status (1)
TRANSMITTER STATUS
E1
E2
E1*
E2*
mono
0.7(L+R)
−
2(L+R)
−
stereo
0.7(L+R)
2R
4L
4R
dual sound
0.7A
B
2A
2B
Note
1. L = left channel signal;
R = right channel signal;
A = first sound channel signal;
B = second sound channel signal
This section of the circuit also performs the de-emphasis (50 µs time constant) with a high degree of accuracy.
AF switch
The AF switch is used to switch to either the internal sound sources (E1* or E1* and E2*) or, to the external sound source
(E3 and E4) and is controlled via the I2 C-bus.
Source selector
The source selector is used to connect the outputs from the AF switch to the outputs A1 to A4 as illustrated by Table 5.
The selector is controlled via the I2 C-bus.
Muting
In this mode the AF outputs A1 to A4 are muted, and the identification circuit is deactivated (mono). The muting is active
after power-on reset or as a result of user control (via the mute input and bit CR3 of the control byte of the mute and port
control register; see Table 4).
Sound mute
If the switch register is set to (00) hex, (sound mute) only the AF outputs are muted, the identification circuit is still active
and can be read (status register) via the I2 C-bus.
Power-on reset
The following actions are carried out by the internal power-on reset when it is active:
• The AF outputs are muted
• The identification circuit is deactivated (mono)
• The control ports (C1 and C2) are set LOW
• The I2 C-bus transceiver is initialized
November 1989
6
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
When the power-on reset becomes passive the following occurs:
• The AF outputs are kept in the mute state until the contents of the switch register are changed from (00) hex via the
I2 C-bus
• The identification circuit is activated
• The control ports are LOW until the mute and control port register is changed (CR bits 10, 11, 20 and 21)
• The I2 C-bus transceiver is activated
Fig.3 Mute modes.
November 1989
7
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
Control ports
The general purpose control ports C1 and C2 can be set to LOW, HIGH or high impedance via the I2C-bus.
I2 C-bus receiver and data handling
Bus specification
The TDA8416 is controlled, via the bidirectional 2-line I2 C-bus, by a microcomputer. The two lines are a serial data line
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer
may be initiated only when the bus is not busy.
When the bus is free both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock.
The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The set up and
hold times are specified in the CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as the start condition (S). A LOW-to-HIGH
transition of the SDA line while SCL is HIGH is defined as the stop condition (P). The bus receiver will be reset on the
reception of a start condition. The bus is considered to be busy after the start condition. The bus is considered to be free
again after a stop condition.
The I2 C-BUS PROTOCOL OF THE TDA8416
The TDA8416 is controlled by a microcomputer and can be written to or read from via the I2 C-bus.
The first byte is the address and determines whether the TDA8416 is to be read from (status register) or written to (switch
register or mute and port control register).
Read from (TDA8416 is a slave transmitter)
Write to (TDA8416 is a slave receiver)
Where:
S
= start bit
A
= acknowledge bit
MAD = module address bit
The MAD input (pin 20) allows the TDA8416 to operate from two different addresses:
MAD = LOW = > A3 = A4 = 0 − > slave address = 1000 010
MAD = HIGH = > A3 = A4 = 1 − > slave address = 1011 010
Fig.4 Address byte.
November 1989
8
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
Reading the TDA8416
Reading the TDA8416 means reading the status register and the data stream will have the format as illustrated in Fig.5.
Where:
S
= start bit
A
= acknowledge bit
P
= stop bit
MAD = module address
Fig.5 Read format.
The second byte, the contents of the status register, is defined by Table 2.
Table 2
Status register (see note 1)
D7
D6
D5
D4
D3
D2
D1
D0
PONRES
ST
DS
0
0
0
0
0
Note
1. PONRES = power on reset;
1 = power on reset active after switching on or power breakdown;
0 = after reading the status register;
ST = stereo transmission;
DS = dual sound transmission
The truth table for the ST and DS bits is provided by Table 3.
Table 3
Truth table for the ST and DS bits
ST
DS
0
0
mono transmission
0
1
dual sound transmission
1
0
stereo transmission
November 1989
DEFINITION
9
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
Writing to the TDA8416
Writing to the TDA8416 means, writing to either the switch register or the mute and port control register. Which one is to
be addressed is defined by the subaddress (the second byte) as illustrated by Fig.6. The third byte contains the
information to be stored in the specified register.
Where
S
= start bit
A
= acknowledge
P
= stop bit
MAD = module
bit
address
Fig.6 Write format.
Table 4 defines the contents of the mute and port control register.
Table 4
Mute and port control register (1)
D7
D6
D5
D4
CR3
D3
CR21
D2
CR20
D1
CR11
D0
CR10
DEFINITION
X
X
X
0
0
control port C1 = LOW
X
X
X
0
1
control port C1 = HIGH
X
X
X
1
X
control port C1 = high impedance
X
X
X
0
0
control port C2 = LOW
X
X
X
0
1
control port C2 = HIGH
X
X
X
1
X
control port C2 = high impedance
X
X
X
0
mute is active when pin 18 is LOW (default)
X
X
X
1
mute is active when pin 18 is HIGH
Note
1. X = don’t care
November 1989
10
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
Table 5 defines the contents of the switch register.
Table 5
Switch register (1)
SWITCH
INPUT
REGISTER
E1
E2
OUTPUT
E3
E4
D7 D6 D5 D4 D3 D2 D1 D0
(HEX)
E5 A1 A2 A3 A4
sound mute
−
−
−
−
−
−
no signal
0
0
0
0
0
0
0
0
(00)
mono
M
M
M
−
−
−
M
M
M
M
0
0
0
1
0
0
0
0
(10)
St
L*
R
−
−
−
L*
L*
L*
L*
0
0
0
1
0
0
0
0
(10)
stereo
St
L*
R
−
−
−
L
R
L
R
0
0
1
0
1
0
1
0
(2A)
sound A
DS
A
B
−
−
−
A
A
A
A
0
0
0
1
0
0
0
0
(10)
sound B
DS
A
B
−
−
−
B
B
B
B
0
0
0
1
1
1
1
1
(1F)
dual sound
DS
A
B
−
−
−
A
A
B
B
0
0
0
1
1
1
0
0
(1C)
DS
A
B
−
−
−
B
B
A
A
0
0
0
1
0
0
1
1
(13)
DS
A
B
−
−
−
A
B
A
A
0
0
0
1
0
0
1
0
(12)
dual sound
mix
external
DS
A
B
−
−
−
A
A
A
B
0
0
0
1
1
0
0
0
(18)
DS
A
B
−
−
−
A
B
A
B
0
0
0
1
1
0
1
0
(1A)
DS
A
B
−
−
−
B
B
A
B
0
0
0
1
1
0
1
1
(1B)
DS
A
B
−
−
−
A
B
B
B
0
0
0
1
1
1
1
0
(1E)
−
−
−
E3
E4
−
E3
E3
E3
E3
0
1
1
1
0
0
0
0
(70)
−
−
−
E3
E4
−
E4
E4
E4
E4
0
1
1
1
1
1
1
1
(7F)
−
−
−
E3
E4
−
E3
E4
E3
E4
0
1
1
1
1
0
1
0
(7A)
−
−
−
E3
E4
−
E4
E4
E3
E3
0
1
1
1
0
0
1
1
(73)
−
−
−
E3
E4
−
E3
E3
E4
E4
0
1
1
1
1
1
0
0
(7C)
−
−
−
E3
E4
−
E3
E4
E3
E3
0
1
1
1
0
0
1
0
(72)
−
−
−
E3
E4
−
E3
E3
E3
E4
0
1
1
1
1
0
0
0
(78)
−
−
−
E3
E4
−
E4
E4
E3
E4
0
1
1
1
1
0
1
1
(7B)
−
−
−
E3
E4
−
E3
E4
E4
E4
0
1
1
1
1
1
1
0
(7E)
−
−
−
−
−
E5
E5
E5
E5
E5
1
0
0
0
0
0
0
0
(80)
Note
1. M = mono;
St = stereo;
DS = dual sound;
R = right;
L = left;
L* = (L + R)/2;
A = sound A;
B = sound B
November 1989
11
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
RATINGS
Limiting values in accordance with Absolute Maximum System (IEC 134)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
VP = V15-16
−
−
13.2
V
IO
−
−
10
mA
(sink)
IO
−
−
7
mA
(source)
−IO
−
−
3
mA
Input voltage (not pin 18)
VI
0
−
VP
V
Input voltage pin 18
VI = V18-16
−
−
7
V
Output voltage
VO
0
−
VP
V
Total power dissipation
Ptot
−
−
1
W
ESD protection (each pin) (0 Ω/200 pF)
Ves
500
−
−
V
Operating ambient temperature range
Tamb
0
−
+ 70
°C
Storage temperature range
Tstg
−40
−
+ 150
°C
Supply
voltage(1)
Output current
pins 11, 12, 13, 14
pins 1 and 19
Note
1. Supply voltage may be applied only when both pins 5 and 15 are connected to ground.
November 1989
12
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
CHARACTERISTICS
VP = 12 V; Tamb = 25 °C. Measurement conditions (see Fig.7): reference level is 1 V (RMS); test
frequency = 3.183 kHz; noise measurement in accordance with DIN 45405, CCIR 468-3; oscillator
frequency = 10 MHz; pre-emphasis time constant = 50 µs.
PARAMETER
CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supplies
Supply voltage
VP = V15-16
10.8
12
13.2
V
Supply current
IP = I15
−
10
−
mA
pins 6 - 14 and 17
Vn-16
−
3.25
−
V
pin 4
V4-5
−
2
−
V
fCLK
0.7
−
100
kHz
Input voltage LOW
VIL
−0.3
−
1.5
V
Input voltage HIGH
VIH
3
−
5
V
Timing LOW period
tLOW
4.7
−
−
µs
Timing HIGH period
tHIGH
4
−
−
µs
Rise time
tr
−
−
1
µs
Fall time
tf
−
−
0.3
µs
Input current LOW
−IIL
−
−
10
µA
Input current HIGH
IIH
−
−
10
µA
Input voltage LOW
VIL
−0.3
−
1.5
V
Input voltage HIGH
VIH
3
−
5
V
Rise time
tr
−
−
1
µs
Fall time
tf
−
−
0.3
µs
DC levels
Bus transceiver
Clock frequency
(I2 C-bus)
note 1
Clock SCL (pin 3)
Data SDA (pin 2)
Data set-up time
tSU; DAT
0.25
−
−
µs
Input current LOW
−IIL
−
−
10
µA
Input current HIGH
IIH
−
−
10
µA
Output current LOW
IOL
3
−
−
mA
Input voltage LOW
V20-5
−
−
2.0
V
Input voltage HIGH
V20-5
3.0
−
−
V
MAD (pin 20)
November 1989
13
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
PARAMETER
CONDITIONS
TDA8416
SYMBOL
MIN.
TYP.
MAX.
UNIT
Mute port (pin 18)
Input voltage LOW
note 2
VIL
−0.3
−
1.5
V
Input voltage HIGH
note 2
VIH
3
−
5
V
Output voltage LOW
note 3
VOL
−
−
0.5
V
Output voltage HIGH
note 3
VOH
4.5
−
5
V
Output impedance
3-state
Control ports
(pins 1 and 19)
ZO
1
−
−
MΩ
Output current LOW
IOL
1
−
−
mA
Output current HIGH
−IOH
1
−
−
mA
Zi
150
200
−
kΩ
Input voltage E1
VI
−
−
0.7
V
Input voltage E2
VI
−
−
1
V
AF stages and identification
(pins 7 to 14)
Input impedance
(pins 7 to 10)
Input voltage E2 for
identification
active (RMS value)
note 4
Vi
2.5
−
−
mV
Voltage gain 7-15/output
note 5
Gv
5.9
6
6.1
dB
Voltage gain 8-15/output
note 5
Gv
8.9
9
9.1
dB
Gv
−0.1
0
0.1
dB
dual mode
αds
70
75
−
dB
stereo mode
αs
30
50
−
dB
ZO
400
500
600
Ω
49.5
50
50.5
µs
Voltage gain
6, 9, 10-15/output
Crosstalk attenuation
notes 6 to 8
Output impedance
(pins 11 to 14)
De-emphasis time
constant
Frequency response
note 9
note 6
∆f
−1
−
1
dB
note 10
THD
−
−
0.2
%
CL
−
−
1.5
nF
VO
−
−
2
V
Total harmonic
distortion
Capacitive load
(pins 11 to 14)
Output signal
(RMS value)
(pins 11 to 14)
November 1989
THD ≤ 0.2%
14
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
PARAMETER
Ripple rejection
Noise from
CONDITIONS
note 11
I2 C-bus
Signal-to-noise ratio
TDA8416
SYMBOL
MIN.
TYP.
MAX.
UNIT
50
66
−
NR
−
−
−80
dB
(S+W)/W
70
−
−
dBV
CCIR
SS
70
75
−
dB
−
−
30
mV
−
10
−
MHz
RR
dB
Signal suppression
during mute
note 6
Change of output
DC voltage level
between any two
modes
Oscillator
Oscillator frequency
fOSC
External oscillator
V4-5
1.7
−
−
V
Quartz series resistor
R1
−
−
100
Ω
Impedance
Zi
−
−1.2 + j9.3
−
kΩ
Capacitance
COSC
−
1.7
−
pF
signal (RMS value)
Notes to the characteristics
1. Full specification of I2 C-bus will be supplied on request.
2. Programmable mute state. If the CR3 bit of the mute and port control register is LOW, the mute is active LOW; if it
is HIGH, the mute input is active HIGH.
3. Output current IO ≈ 1 mA.
4. Unmodulated.
5. f = 400 Hz; RL = 1 MΩ.
6. 40 Hz ≤ f ≤ 15 kHz.
7. In dual mode: A(B)-signal into B(A)-channel.
In stereo mode: R-signal into left, L-signal = 0, reference is 1 V RMS.
8. Source impedance ZS < 1 kΩ.
9. Equivalent to an output level of −3 dB at f = 3.183 kHz.
10. VO = 1 V RMS; f = 1 kHz.
11. Test circuit see Fig.7.
November 1989
15
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
(1) This potentiometer has to be adjusted to achieve the best stereo separation.
(2) Direct connection between pins 5 and 16 is achieved.
Fig.7 Application and test circuit.
November 1989
16
TDA8416
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
Voltage input = supply voltage + pulse voltage at 70 Hz = 12 V ± 50 mV (p-p).
Fig.8 Ripple rejection test circuit.
Fig.9 Total harmonic distortion diagram (stereo mode).
November 1989
17
TDA8416
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
PACKAGE OUTLINE
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
b1
w M
(e 1)
b
MH
11
20
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.2
0.51
3.2
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
inches
0.17
0.020
0.13
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
D
e
e1
L
ME
MH
w
Z (1)
max.
6.40
6.22
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.0
0.25
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.078
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT146-1
November 1989
REFERENCES
IEC
JEDEC
EIAJ
SC603
18
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-05-24
Philips Semiconductors
Preliminary specification
TV and VTR stereo/dual sound processor
with integrated filters and I2C-bus control
TDA8416
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
November 1989
19