PHILIPS PCF8578H

INTEGRATED CIRCUITS
DATA SHEET
PCF8578
LCD row/column driver for
dot matrix graphic displays
Product specification
Supersedes data of 1998 Sep 08
2003 Apr 14
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
CONTENTS
18
SOLDERING
18.1
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
19
DATA SHEET STATUS
7
FUNCTIONAL DESCRIPTION
20
DEFINITIONS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
Mixed mode
Row mode
Multiplexed LCD bias generation
Power-on reset
Internal clock
External clock
Timing generator
Row/column drivers
Display mode controller
Display RAM
Data pointer
Subaddress counter
I2C-bus controller
Input filters
RAM access
Display control
TEST pin
21
DISCLAIMERS
22
PURCHASE OF PHILIPS I2C COMPONENTS
8
I2C-BUS PROTOCOL
8.1
Command decoder
9
CHARACTERISTICS OF THE I2C-BUS
9.1
9.2
9.3
9.4
Bit transfer
Start and stop conditions
System configuration
Acknowledge
10
LIMITING VALUES
11
HANDLING
12
DC CHARACTERISTICS
13
AC CHARACTERISTICS
14
APPLICATION INFORMATION
15
CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
16
CHIP-ON-GLASS INFORMATION
17
PACKAGE OUTLINES
2003 Apr 14
18.2
18.3
18.4
18.5
2
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
1
PCF8578
FEATURES
• Single chip LCD controller/driver
• Stand-alone or may be used with up to 32 PCF8579s
(40960 dots possible)
• 40 driver outputs, configurable as 32⁄8, 24⁄16, 16⁄24 or
8⁄ rows/columns
32
2
• Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
APPLICATIONS
• Automotive information systems
• Externally selectable bias configuration, 5 or 6 levels
• Telecommunication systems
• 1280-bit RAM for display data storage and scratch pad
• Point-of-sale terminals
• Display memory bank switching
• Computer terminals
• Auto-incremented data loading across hardware
subaddress boundaries (with PCF8579)
• Instrumentation.
• Provides display synchronization for PCF8579
• On-chip oscillator, requires only 1 external resistor
3
• Power-on reset blanks display
The PCF8578 is a low power CMOS LCD row/column
driver, designed to drive dot matrix graphic displays at
multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device
has 40 outputs, of which 24 are programmable,
configurable as 32⁄8, 24⁄16, 16⁄24 or 8⁄32 rows/columns.
The PCF8578 can function as a stand-alone LCD
controller/driver for use in small systems, or for larger
systems can be used in conjunction with up to
32 PCF8579s for which it has been optimized. Together
these two devices form a general purpose LCD dot matrix
driver chip set, capable of driving displays of up to
40960 dots. The PCF8578 is compatible with most
microcontrollers and communicates via a two-line
bidirectional bus (I2C-bus). Communication overheads are
minimized by a display RAM with auto-incremented
addressing and display bank switching.
• Logic voltage supply range 2.5 to 6 V
• Maximum LCD supply voltage 9 V
• Low power consumption
• I2C-bus interface
• TTL/CMOS compatible
• Compatible with most microcontrollers
• Optimized pinning for single plane wiring in multiple
device applications (with PCF8579)
• Space saving 56-lead plastic mini-pack and 64 pin quad
flat pack
• Compatible with chip-on-glass technology.
4
GENERAL DESCRIPTION
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8578T
PCF8578U/2
PCF8578H
2003 Apr 14
VSO56
−
LQFP64
DESCRIPTION
VERSION
plastic very small outline package; 56 leads
SOT190-1
−
chip with bumps in tray
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
3
SOT314-2
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
5
PCF8578
BLOCK DIAGRAM
C39 - C32
R31/C31 - R8/C8
R7 - R0
VDD
V2
V3
V4
V5
VLCD
TEST
17 - 56
(29 to 35, 37, 38 to 46
48 to 62, 63, 64, 1 to 6)
9 (20)
10 (21)
11 (22)
ROW/COLUMN
DRIVERS
12 (23)
(1)
PCF8578
13 (24)
14 (25)
6 (12)
DISPLAY
MODE
CONTROLLER
OUTPUT
CONTROLLER
Y DECODER
AND SENSING
AMPLIFIERS
32 x 40-BIT
DISPLAY RAM
DISPLAY
DECODER
X DECODER
(9) 3
SUBADDRESS
COUNTER
POWER-ON
RESET
SCL
SDA
RAM DATA POINTER
Y
TIMING
GENERATOR
SYNC
(10) 4
CLK
X
(16) 8
2 (8)
I 2 C-BUS
CONTROLLER
INPUT
FILTERS
1 (7)
15, 16
(14, 15, 17 to 19
26 to 28 36, 47)
n.c.
n.c.
COMMAND
DECODER
R OSC
(11) 5
7 (13)
MSA842
SA0
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
The pin numbers given in parenthesis refer to the LQFP64 package.
Fig.1 Block diagram.
2003 Apr 14
4
OSC
OSCILLATOR
VSS
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
6
PCF8578
PINNING
PIN
SYMBOL
DESCRIPTION
VSO56
LQFP64
SDA
1
7
I2C-bus serial data input/output
SCL
2
8
I2C-bus serial clock input
SYNC
3
9
cascade synchronization output
CLK
4
10
external clock input/output
VSS
5
11
ground (logic)
TEST
6
12
test pin (connect to VSS)
SA0
7
13
I2C-bus slave address input (bit 0)
OSC
8
16
oscillator input
VDD
9
20
positive supply voltage
10 to 13
21 to 24
LCD bias voltage inputs
VLCD
14
25
n.c.
15, 16
14, 15, 17 to 19,
26 to 28, 36, 47
C39 to C32
17 to 24
29 to 35, 37
R31/C31 to R8/C8
25 to 48
R7 to R0
49 to 56
V2 to V5
2003 Apr 14
LCD supply voltage
not connected
LCD column driver outputs
38 to 46, 48 to 62 LCD row/column driver outputs
63, 64, 1 to 6
LCD row driver outputs
5
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
SDA
1
56
SCL
2
55 R1
SYNC
3
54
R2
CLK
4
53
R3
VSS
5
52
R4
TEST
6
51
R5
SA0
7
50
R6
OSC
8
49
R7
VDD
9
48
R8/C8
V2 10
47
R9/C9
V3 11
46
R10/C10
V4 12
45 R11/C11
V5 13
44 R12/C12
VLCD
14
R0
43 R13/C13
PCF8578T
n.c. 15
42 R14/C14
n.c. 16
41 R15/C15
C39 17
40 R16/C16
C38 18
39 R17/C17
C37
19
38 R18/C18
C36
20
37 R19/C19
C35
21
36 R20/C20
C34
22
35 R21/C21
C33
23
34 R22/C22
C32
24
33 R23/C23
R31/C31
25
32 R24/C24
R30/C30
26
31 R25/C25
R29/C29
27
30 R26/C26
R28/C28
28
29 R27/C27
MSA839
Fig.2 Pin configuration (VSO56).
2003 Apr 14
6
Philips Semiconductors
Product specification
49 R21/C21
50 R20/C20
51 R19/C19
52 R18/C18
53 R17/C17
54 R16/C16
55 R15/C15
56 R14/C14
57 R13/C13
58 R12/C12
59 R11/C11
PCF8578
60 R10/C10
61 R9/C9
63 R7
64 R6
handbook, full pagewidth
62 R8/C8
LCD row/column driver for
dot matrix graphic displays
R5
1
48 R22/C22
R4
2
47 n.c.
R3
3
46 R23/C23
R2
4
45 R24/C24
R1
5
44 R25/C25
R0
6
43 R26/C26
SDA
7
42 R27/C27
SCL
8
41 R28/C28
PCF8578H
9
40 R29/C29
CLK 10
39 R30/C30
VSS 11
38 R31/C31
SYNC
Fig.3 Pin configuration (LQFP64).
2003 Apr 14
7
C36 32
C37 31
C38 30
C39 29
n.c. 28
n.c. 27
n.c. 26
33 C35
V5 24
OSC 16
VLCD 25
34 C34
V4 23
n.c. 15
V3 22
35 C33
V2 21
n.c. 14
VDD 20
36 n.c.
n.c. 19
SA0 13
n.c. 18
37 C32
n.c. 17
TEST 12
MBH588
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
7
PCF8578
FUNCTIONAL DESCRIPTION
Timing signals are derived from the on-chip oscillator,
whose frequency is determined by the value of the resistor
connected between OSC and VSS.
The PCF8578 row/column driver is designed for use in one
of three ways:
Commands sent on the I2C-bus from the host
microcontroller set the mode (row or mixed), configuration
(multiplex rate and number of rows and columns) and
control the operation of the device. The device may have
one of two slave addresses. The only difference between
these slave addresses is the least significant bit, which is
set by the logic level applied to SA0. The PCF8578 and
PCF8579 also have subaddresses. The subaddress of the
PCF8578 is only defined in mixed mode and is fixed at 0.
The RAM may only be accessed in mixed mode and data
is loaded as described for the PCF8579.
• Stand-alone row/column driver for small displays
(mixed mode)
• Row/column driver with cascaded PCF8579s
(mixed mode)
• Row driver with cascaded PCF8579s (mixed mode).
7.1
Mixed mode
In mixed mode, the device functions as both a row and
column driver. It can be used in small stand-alone
applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used).
See Table 1 for common display configurations.
7.2
Bias levels may be generated by an external potential
divider with appropriate decoupling capacitors. For large
displays, bias sources with high drive capability should be
used. A typical mixed mode system operating with up to
15 PCF8579s is shown in Fig.5 (a stand-alone system
would be identical but without the PCF8579s).
Row mode
In row mode, the device functions as a row driver with up
to 32 row outputs and provides the clock and
synchronization signals for the PCF8579. Up to 16
PCF8579s can normally be cascaded (32 when two slave
addresses are used).
Table 1
Possible displays configurations
APPLICATION
Stand alone
With PCF8579
MIXED MODE
ROW MODE
MULTIPLEX
RATE
ROWS
COLUMNS
ROWS
COLUMNS
1:8
8
32
−
−
1 : 16
16
24
−
−
1 : 24
24
16
−
−
1 : 32
32
8
−
−
1:8
8(1)
632(1)
8×
1 : 16
16(1)
624(1)
16 ×
1 : 24
24(1)
616(1)
24(2)
640(2)
1 : 32
32(1)
608(1)
24(2)
640(2)
TYPICAL APPLICATIONS
Notes
1. Using 15 PCF8579s.
2. Using 16 PCF8579s.
2003 Apr 14
8
4(2)
2(2)
640(2)
640(2)
small digital or
alphanumerical displays
alphanumeric displays and
dot matrix graphic displays
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
7.3
PCF8578
7.4
Multiplexed LCD bias generation
At power-on the PCF8578 resets to a defined starting
condition as follows:
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (Vth). Vth is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 2 shows the
optimum voltage bias levels for the PCF8578 as functions
of Vop (Vop = VDD − VLCD), together with the discrimination
ratios (D) for the different multiplex rates. A practical value
for Vop is obtained by equating Voff(rms) with Vth. Figure 4
shows the first 4 rows of Table 2 as graphs. Table 3 shows
the relative values of the resistors required in the
configuration of Fig.5 to produce the standard multiplex
rates.
Table 2
Power-on reset
1. Display blank
2. 1 : 32 multiplex rate, row mode
3. Start bank, 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I2C-bus interface is initialized.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
Optimum LCD voltages
MULTIPLEX RATE
PARAMETER
1:8
1 : 16
1 : 24
1 : 32
MSA838
1.0
V2
--------V op
0.739
0.800
0.830
V bias
0.850
V2
Vop
0.8
V3
--------V op
0.522
0.600
0.661
0.700
V3
0.6
V4
--------V op
0.478
V5
--------V op
0.261
V off ( rms )
---------------------V op
0.297
0.400
0.339
0.300
0.4
0.200
0.170
V4
0.150
0.2
V5
0.245
0.214
0.193
0
V on ( rms )
--------------------V op
0.430
V on ( rms )
D = --------------------V off ( rms )
1.447
1.291
1.230
1.196
V op
--------V th
3.370
4.080
4.680
5.190
Table 3
0.316
0.263
1:8
1:16
1:24
1:32
multiplex rate
0.230
Vbias = V2, V3, V4, V5. See Table 2.
Fig.4
Multiplex rates and resistor values for Fig.5
MULTIPLEX RATE (n)
RESISTORS
n=8
n = 16, 24, 32
R1
R
R
R2
( n – 2 )R
R
R3
( 3 – n )R
( n – 3 )R
2003 Apr 14
9
Vbias/Vop as a function of the multiplex rate.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
n
rows
V DD
40 n
columns
V DD
C
40
columns
R1
Philips Semiconductors
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14
LCD DISPLAY
V2
C
R2
V3
HOST
MICROCONTROLLER
C
R3
10
V4
SCL
C
SDA
PCF8578
R2
V DD
V DD
VLCD
VLCD
VSS
VSS
VSS / V DD
SA0
SDA
V5
C
A0
A1
PCF8579
A2
subaddress 1
VSS / V DD
A3
SCL CLK SYNC V4
V3
R1
V
LCD
VSS
VSS
VLCD
SA0
VSS / V DD
OSC
R OSC
SDA SCL CLK SYNC
PCF8578
Fig.5 Typical mixed mode configuration.
Product specification
MSA843
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
T frame
0
ROW 0
COLUMN
1
2
3
ON
4
5
6
OFF
7
VDD
V2
V3
V4
V5
V LCD
1:8
VDD
V2
V3
V4
V5
V LCD
SYNC
0
ROW 0
COLUMN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VDD
V2
V3
V4
V5
V LCD
1:16
VDD
V2
V3
V4
V5
V LCD
SYNC
0
ROW 0
COLUMN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
VDD
V2
V3
V4
V5
V LCD
1:24
VDD
V2
V3
V4
V5
V LCD
SYNC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
ROW 0
COLUMN
VDD
V2
V3
V4
V5
V LCD
1:32
VDD
V2
V3
V4
V5
V LCD
SYNC
MSA841
Fig.6 LCD row/column waveforms.
2003 Apr 14
11
column
display
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
T frame
ROW 1
R1 (t)
VDD
V2
V3
V4
V5
V LCD
ROW 2
R2 (t)
VDD
V2
V3
V4
V5
V LCD
COL 1
C1 (t)
VDD
V2
V3
V4
V5
V LCD
COL 2
C2 (t)
VDD
V2
V3
V4
V5
V LCD
state 1 (OFF)
state 2 (ON)
dot matrix
1:8 multiplex rate
V op
0.261 Vop
V state 1 (t)
0V
0.261 Vop
V op
V op
0.478 Vop
0.261 Vop
V state 2 (t)
0V
0.261 Vop
0.478 Vop
V op
MSA840
V state 1 (t) = C1(t)
Von(rms)
V op
=
1
8
V state 2 (t) = C2(t)
Voff(rms)
V op
=
general relationship (n = multiplex rate)
R1(t):
8
8 (
1
8
1)
= 0.430
R2(t):
2 ( 8 1)
= 0.297
8 ( 8 1) 2
Von(rms)
V op
=
Voff(rms)
=
V op
1
n
n 1
n ( n 1)
2 ( n 1)
n ( n 1) 2
Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.
2003 Apr 14
12
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
state 1 (OFF)
state 2 (ON)
T frame
ROW 1
R1 (t)
VDD
V2
V3
V4
V5
V LCD
ROW 2
R2 (t)
VDD
V2
V3
V4
V5
V LCD
COL 1
C1 (t)
VDD
V2
V3
V4
V5
V LCD
COL 2
C2 (t)
dot matrix
1:16 multiplex rate
VDD
V2
V3
V4
V5
V LCD
V op
0.2 Vop
V state 1 (t)
0V
0.2 Vop
V op
V op
0.6 Vop
V state 2 (t)
0.2 Vop
0V
0.2 Vop
0.6 Vop
V op
MSA836
V state 1 (t) = C1(t)
Von(rms)
V op
=
V op
=
Von(rms)
1
16 1
= 0.316
16 16 ( 16 1 )
V state 2 (t) = C2(t)
V off(rms)
general relationship (n = multiplex rate)
R1(t):
V op
R2(t):
=
Voff(rms)
=
V op
2 ( 16 1)
= 0.254
16 ( 16 1 ) 2
1
n
n 1
n ( n 1)
2 ( n 1)
n ( n 1) 2
Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.
2003 Apr 14
13
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
7.5
PCF8578
Internal clock
7.6
The clock signal for the system may be generated by the
internal oscillator and prescaler. The frequency is
determined by the value of the resistor ROSC, see Fig.9.
For normal use a value of 330 kΩ is recommended.
The clock signal, for cascaded PCF8579s, is output at
CLK and has a frequency 1⁄6 (multiplex rate 1 : 8, 1 : 16
and 1 : 32) or 1⁄8 (multiplex rate 1 : 24) of the oscillator
frequency.
If an external clock is used, OSC must be connected to
VDD and the external clock signal to CLK. Table 4
summarizes the nominal CLK and SYNC frequencies.
7.7
f OSC
7.8
(kHz)
10
102
103
104
R OSC (kΩ )
Using a 1 : 16 multiplex rate, two sets of row outputs are
driven, thus facilitating split-screen configurations, i.e. a
row select pulse appears simultaneously at R0 and
R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
rate of 1 : 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
to the LCD. Unused outputs should be left open-circuit.
In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are
rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32
R0 to R31/C31 are rows.
To avoid capacitive coupling, which could adversely affect oscillator
stability, ROSC should be placed as closely as possible to the OSC
pin. If this proves to be a problem, a filtering capacitor may be
connected in parallel to ROSC.
Fig.9
Table 4
Row/column drivers
Outputs R0 to R7 and C32 to C39 are fixed as row and
column drivers respectively. The remaining 24 outputs
R8/C8 to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmable outputs (R8/C8 to R31/C31) are defined as
row drivers and the outputs C32 to C39 should be left
open-circuit.
10 2
1
10
Timing generator
The timing generator of the PCF8578 organizes the
internal data flow of the device and generates the LCD
frame synchronization pulse SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
relationship between the PCF8578 and PCF8579s in the
system.
MSA837
10 3
External clock
Oscillator frequency as a function of
external oscillator resistor, ROSC.
Signal frequencies required for nominal 64 Hz frame frequency; note 1.
OSCILLATOR
FREQUENCY
fOSC(2) (Hz)
FRAME FREQUENCY
fSYNC (Hz)
MULTIPLEX RATE (n)
DIVISION
RATIO
CLOCK FREQUENCY
fCLK (Hz)
12288
64
1 : 8, 1 : 16, 1 : 32
6
2048
12288
64
1 : 24
8
1536
Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
2. ROSC = 330 kΩ.
2003 Apr 14
14
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
7.9
PCF8578
7.15
Display mode controller
RAM operations are only possible when the PCF8578 is
in mixed mode.
The configuration of the outputs (row or column) and the
selection of the appropriate driver waveforms are
controlled by the display mode controller.
7.10
In this event its hardware subaddress is internally fixed at
0000 and the hardware subaddresses of any PCF8579
used in conjunction with the PCF8578 must start at 0001.
Display RAM
The PCF8578 contains a 32 × 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks
of 40 bytes (4 × 8 × 40 bits). During RAM access, data is
transferred to/from the RAM via the I2C-bus. The first
eight columns of data (0 to 7) cannot be displayed but
are available for general data storage and provide
compatibility with the PCF8579. There is a direct
correspondence between X-address and column output
number.
7.11
There are three RAM ACCESS modes:
• Character
• Half-graphic
• Full-graphic.
These modes are specified by bits G1 to G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.10).
Data pointer
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.11):
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I2C-bus.
7.12
• Device subaddress (specified by the DEVICE SELECT
command)
• RAM X-address (specified by the LOAD X-ADDRESS
command)
• RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
Subaddress counter
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage takes
place only when the contents of the subaddress counter
agree with the hardware subaddress. The hardware
subaddress of the PCF8578, valid in mixed mode only, is
fixed at 0000.
7.13
Subsequent data bytes will be written or read according to
the chosen RAM ACCESS mode. Device subaddresses
are automatically incremented between devices until the
last device is reached. If the last device has
subaddress 15, further display data transfers will lead to a
wrap-around of the subaddress to 0.
I2C-bus controller
7.16
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8578 acts as an
I2C-bus slave transmitter/receiver in mixed mode, and as
a slave receiver in row mode. A slave device cannot
control bus communication.
7.14
RAM access
Display control
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.12. This feature is useful when scrolling in
alphanumeric applications.
Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.17
TEST pin
The TEST pin must be connected to VSS.
2003 Apr 14
15
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
driver 1
driver 2
driver k
bank 0
bank 1
RAM
4 bytes
bank 2
bank 3
PCF8578/PCF8579 system RAM
1 k 16
40-bits
1 byte
0
1
2
3
4
5
6
7
8
LSB
Philips Semiconductors
PCF8579
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14
PCF8578/PCF8579
9 10 11
character mode
16
MSB
0
2
4
6
8 10 12 14 16 18 20 22
1
3
5
7
9 11 13 15 17 19 21 23
2 bytes
half-graphic mode
0
4
8 12 16 20 24 28 32 36 40 44
1
5
9 13 17 21 25 29 33 37 41 45
2
6 10 14 18 22 26 30 34 38 42 46
3
7 11 15 19 23 27 31 35 39 43 47
4 bytes
Fig.10 RAM ACCESS mode.
MSA849
Product specification
full-graphic mode
PCF8578
RAM data bytes are
written or read as
indicated above
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
RAM ACCESS:
bank 0
character mode
bank 1
bank 1
RAM
bank 2
Philips Semiconductors
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14
DEVICE SELECT:
subaddress 12
bank 3
LOAD X-ADDRESS: X-address = 8
R/ W
slave address
17
READ
S
S 0 1 1 1 1 0 A 1 A
DATA
A
0
R/W
slave address
S
DEVICE SELECT
LOAD X-ADDRESS
RAM ACCESS
S
0 1 1 1 1 0 A 0 A 1 1 1 0 1 1 0 0 A 1 0 0 0 1 0 0 0 A 0 1 1 1 0 0 0 1 A
0
last command
WRITE
DATA
A
DATA
A
MSA835
Product specification
PCF8578
Fig.11 Example of commands specifying initial data byte RAM locations.
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
RAM
bank 0
top of LCD
bank 1
LCD
bank 2
bank 3
MSA851
Fig.12 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.
2003 Apr 14
18
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
8
PCF8578
In READ mode, indicated by setting the read/write bit
HIGH, data bytes may be read from the RAM following the
slave address acknowledgement. After this
acknowledgement the master transmitter becomes a
master receiver and the PCF8578 becomes a slave
transmitter. The master receiver must acknowledge the
reception of each byte in turn. The master receiver must
signal an end of data to the slave transmitter, by not
generating an acknowledge on the last byte clocked out of
the slave. The slave transmitter then leaves the data line
HIGH, enabling the master to generate a stop condition
(P).
I2C-BUS PROTOCOL
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8578 and PCF8579. The least
significant bit of the slave address is set by connecting
input SA0 to either 0 (VSS) or 1 (VDD). Therefore, two types
of PCF8578 or PCF8579 can be distinguished on the
same I2C-bus which allows:
1. One PCF8578 to operate with up to 32 PCF8579s on
the same I2C-bus for very large applications
2. The use of two types of LCD multiplex schemes on the
same I2C-bus.
Display bytes are written into, or read from, the RAM at the
address specified by the data pointer and subaddress
counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be
transferred either to, or from, the intended devices.
In most applications the PCF8578 will have the same slave
address as the PCF8579.
The I2C-bus protocol is shown in Fig.13.
All communications are initiated with a start condition (S)
from the I2C-bus master, which is followed by the desired
slave address and read/write bit. All devices with this slave
address acknowledge in parallel. All other devices ignore
the bus transfer.
In multiple device applications, the hardware subaddress
pins of the PCF8579s (A0 to A3) are connected to VSS or
VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
each device must be allocated a unique hardware
subaddress.
In WRITE mode (indicated by setting the read/write bit
LOW) one or more commands follow the slave address
acknowledgement. The commands are also
acknowledged by all addressed devices on the bus.
The last command must clear the continuation bit C.
After the last command a series of data bytes may follow.
The acknowledgement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte
has been acknowledged, the I2C-bus master issues a stop
condition (P).
2003 Apr 14
19
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
acknowledge
by A0, A1, A2 and A3
selected PCF8578s /
PCF8579s only
acknowledge by
all addressed
PCF8578s / PCF8579s
R/ W
slave address
S
S 0 1 1 1 1 0 A 0 A C
1 byte
A
COMMAND
0
n
0 byte(s)
DISPLAY DATA
n
P
0 byte(s)
MSA830
(a)
A
update data pointers
and if necessary,
subaddress counter
acknowledge by
all addressed
PCF8578s / PCF8579s
slave address
S
acknowledge
from master
slave address
S
0 1 1 1 1 0 A 0 A C
0
no acknowledge
from master
S
A
COMMAND
n
S 0 1 1 1 1 0 A 1 A
DATA
A
DATA
0
1 byte
n bytes
R/ W
1
P
last byte
R/W
at this moment master
transmitter becomes a
master receiver and
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter
update data pointers
and if necessary
subaddress counter
MSA832
(b)
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
from master
no acknowledge
from master
slave address
S
S 0 1 1 1 1 0 A 1 A
0
MSA831
R/ W
DATA
n bytes
(c)
A
DATA
1
P
last byte
update data pointers
and if necessary,
subaddress counter
Fig.13 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string
(WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ
mode).
2003 Apr 14
20
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
8.1
PCF8578
Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. The most-significant bit of a
command is the continuation bit C (see Fig.14). When this
bit is set, it indicates that the next byte to be transferred will
also be a command. If the bit is reset, it indicates the
conclusion of the command transfer. Further bytes will be
regarded as display data. Commands are transferred in
WRITE mode only.
MSB
C
REST OF OPCODE
MSA833
C = 0; last command.
C = 1; commands continue.
The five commands available to the PCF8578 are defined
in Tables 5 and 6.
Table 5
LSB
Fig.14 General information of command byte.
Summary of commands
OPCODE(1)
COMMAND
DESCRIPTION
SET MODE
C
1
0
D
D
D
D
D
multiplex rate, display status, system type
SET START BANK
C
1
1
1
1
1
D
D
defines bank at top of LCD
DEVICE SELECT
C
1
1
0
D
D
D
D
defines device subaddress
RAM ACCESS
C
1
1
1
D
D
D
D
graphic mode, bank select (D D D D ≥ 12 is not
allowed; see SET START BANK opcode)
LOAD X-ADDRESS
C
0
D
D
D
D
D
D
0 to 39
Note
1. C = command continuation bit. D = may be a logic 1 or 0.
2003 Apr 14
21
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
Table 6
PCF8578
Definition of PCF8578/PCF8579 commands
COMMAND
SET MODE
OPCODE
C
1
0
T
OPTIONS
E1 E0 M1 M0 see Table 7
1
1
DESCRIPTION
defines LCD drive mode
see Table 8
defines display status
see Table 9
defines system type
SET START BANK
C
1
1
1
B1 B0 see Table 10
DEVICE SELECT
C
1
1
0
A3 A2 A1 A0 see Table 11
four bits of immediate data, bits
A0 to A3, are transferred to the
subaddress counter to define one of
sixteen hardware subaddresses
RAM ACCESS
C
1
1
1
G1 G0 Y1 Y0 see Table 12
defines the auto-increment behaviour of
the address for RAM access
see Table 13
LOAD X-ADDRESS
2003 Apr 14
C
0
X5 X4 X3 X2 X1 X0 see Table 14
22
defines pointer to RAM bank
corresponding to the top of the LCD;
useful for scrolling, pseudo-motion and
background preparation of new display
two bits of immediate data, bits Y0 to
Y1, are transferred to the X-address
pointer to define one of forty display
RAM columns
six bits of immediate data, bits
X0 to X5, are transferred to the
X-address pointer to define one of forty
display RAM columns
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
Table 7
PCF8578
Set mode option 1
Table 11 Device select option 1
DESCRIPTION
BITS
LCD DRIVE MODE
M1
MUX (8 rows)
0
1
1 : 16
MUX (16 rows)
1
0
1 : 24
MUX (24 rows)
1
1
1 : 32
MUX (32 rows)
0
0
Table 8
Decimal value 0 to 15
M0
1:8
BITS
A3
A2
A1
A0
Table 12 RAM access option 1
BITS
RAM ACCESS MODE
Set mode option 2
BITS
DISPLAY STATUS
G1
G0
Character
0
0
Half-graphic
0
1
Full-graphic
1
0
Not allowed (note 1)
1
1
E1
E0
Blank
0
0
Note
Normal
0
1
1. See opcode for SET START BANK in Table 6.
All segments on
1
0
Inverse video
1
1
Table 13 Device select option 1
DESCRIPTION
Table 9
Set mode option 3
Decimal value 0 to 3
SYSTEM TYPE
Y1
Y0
BIT T
PCF8578 row only
0
PCF8578 mixed mode
1
Table 14 Device select option 1
DESCRIPTION
Decimal value 0 to 39
Table 10 Set start bank option 1
BITS
START BANK POINTER
B1
B0
Bank 0
0
0
Bank 1
0
1
Bank 2
1
0
Bank 3
1
1
2003 Apr 14
BITS
23
BITS
X5 X4 X3 X2 X1 X0
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
9
PCF8578
9.4
CHARACTERISTICS OF THE I2C-BUS
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
9.1
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
9.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the STOP condition (P).
9.3
Acknowledge
System configuration
A device transmitting a message is a 'transmitter', a device
receiving a message is the 'receiver'. The device that
controls the message flow is the 'master' and the devices
which are controlled by the master are the 'slaves'.
SDA
SCL
change
of data
allowed
data line
stable;
data valid
Fig.15 Bit transfer.
2003 Apr 14
24
MBA607
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBA608
Fig.16 Definition of start and stop condition.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.17 System configuration.
clock pulse for
acknowledgement
START
condition
handbook, full pagewidth
SCL FROM
MASTER
1
2
8
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
MBA606 - 1
The general characteristics and detailed specification of the I2C-bus are available on request.
Fig.18 Acknowledgement on the I2C-bus.
2003 Apr 14
25
9
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
10 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+8.0
V
VLCD
LCD supply voltage
VDD − 11
VDD
V
VI1
input voltage SDA, SCL, CLK, TEST, SA0 and OSC
VSS − 0.5
VDD + 0.5
V
VI2
input voltage V2 to V5
VLCD − 0.5 VDD + 0.5
V
Vo1
output voltage SYNC and CLK
VSS − 0.5
VDD + 0.5
V
Vo2
output voltage R0 to R7, R8/C8 to R31/C31 and C32 to C39
VLCD − 0.5 VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
IDD, ISS, ILCD
VDD, VSS or VLCD current
−50
+50
mA
Ptot
total power dissipation per package
−
400
mW
Po
power dissipation per output
−
100
mW
Tstg
storage temperature
−65
+150
°C
11 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ).
2003 Apr 14
26
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
12 DC CHARACTERISTICS
VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
2.5
−
6.0
V
VLCD
LCD supply voltage
VDD − 9
−
VDD − 3.5 V
IDD1
supply current external clock
fCLK = 2 kHz; note 1
−
6
15
µA
IDD2
supply current internal clock
ROSC = 330 kΩ
−
20
50
µA
VPOR
power-on reset level
note 2
0.8
1.3
1.8
V
VSS
−
0.3VDD
V
Logic
VIL
LOW level input voltage
VIH
HIGH level input voltage
0.7VDD
−
VDD
V
IOL1
LOW level output current at SYNC
and CLK
VOL = 1 V; VDD = 5 V
1
−
−
mA
IOH1
HIGH level output current at SYNC
and CLK
VOH = 4 V; VDD = 5 V
−
−
−1
mA
VOL = 0.4 V; VDD = 5 V
IOL2
LOW level output current at SDA
3
−
−
mA
IL1
leakage current at SDA, SCL, SYNC, Vi = VDD or VSS
CLK, TEST and SA0
−
−
+1
mA
IL2
leakage current at OSC
Vi = VDD
−
−
+1
µA
Ci
input capacitance at SCL and SDA
note 3
−
−
5
pF
Vi = VDD or VLCD
−2
−
+2
µA
−
±20
−
mV
LCD outputs
IL3
leakage current at V2 to V5
VDC
DC component of LCD drivers
R0 to R7, R8/C8 to R31/C31 and
C32 to C39
RROW
output resistance R0 to R7 and
R8/C8 to R31/C31
row mode; note 4
−
1.5
3
kΩ
RCOL
output resistance R8/C8 to R31/C31
and C32 to C39
column mode; note 4
−
3
6
kΩ
Notes
1. Outputs are open; inputs at VDD or VSS; I2C-bus inactive; external clock with 50% duty factor.
2. Resets all logic when VDD < VPOR.
3. Periodically sampled; not 100% tested.
4. Resistance measured between output terminal (R0 to R7, R8/C8 to R31/C31 and C32 to C39) and bias input
(V2 to V5, VDD and VLCD) when the specified current flows through one output under the following conditions
(see Table 2):
a) Vop = VDD − VLCD = 9 V.
b) Row mode, R0 to R7 and R8/C8 to R31/C31: V2 − VLCD ≥ 6.65 V; V5 − VLCD ≤ 2.35 V; ILOAD = 150 µA.
c) Column mode, R8/C8 to R31/C31 and C32 to C39: V3 − VLCD ≥ 4.70 V; V4 − VLCD ≤ 4.30 V; ILOAD = 100 µA.
2003 Apr 14
27
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
13 AC CHARACTERISTICS
All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V;
VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fCLK1
clock frequency at multiplex rates of 1 : 8, ROSC = 330 kΩ; VDD = 6 V
1 : 16 and 1 : 32
1.2
2.1
3.3
kHz
fCLK2
clock frequency at multiplex rates of
1 : 24
0.9
1.6
2.5
kHz
tPSYNC
SYNC propagation delay
−
−
500
ns
tPLCD
driver delays
−
−
100
µs
ROSC = 330 kΩ; VDD = 6 V
VDD − VLCD = 9 V;
with test loads
I2C-bus
fSCL
SCL clock frequency
−
−
100
kHz
tSW
tolerable spike width on bus
−
−
100
ns
tBUF
bus free time
4.7
−
−
µs
tSU;STA
start condition set-up time
4.7
−
−
µs
tHD;STA
start condition hold time
4.0
4.0
−
µs
tLOW
SCL LOW time
4.7
−
−
µs
tHIGH
SCL HIGH time
4.0
−
−
µs
tr
SCL and SDA rise time
−
−
1
µs
tf
SCL and SDA fall time
−
−
0.3
µs
tSU;DAT
data set-up time
250
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tSU;STO
stop condition set-up time
4.0
−
−
µs
handbook, full pagewidth
repeated start codes only
3.3 kΩ
SYNC, CLK
1.5 kΩ
0.5 VDD
SDA
VDD
MSA829
C39 to C32,
R31/C31 to R8/C8
and R7 to R0
1 nF
Fig.19 AC test loads.
2003 Apr 14
28
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
1/ f CLK
0.7 VDD
CLK
0.3 V DD
0.7 VDD
SYNC
0.3 V DD
t PSYNC
t PSYNC
0.5 V
C39 to C32,
R31/C31 to R8/C8
and R7 to R0
(V DD
V LCD = 9 V)
0.5 V
t PLCD
MSA834
Fig.20 Driver timing waveforms.
handbook, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t
HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
MGA728
t SU;STA
Fig.21 I2C-bus timing waveforms.
2003 Apr 14
29
t SU;STO
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
R2
R3
R4
R5
R6
R7
LCD row/column driver for
dot matrix graphic displays
APPLICATION INFORMATION
R0 R1
Philips Semiconductors
14
2003 Apr 14
LCD DISPLAY
R8/ R9/ R10/ R11/ R12/ R13/ R14/ R15/ R16/ R17/ R18/ R19/ R20/ R21/ R22/ R23/ R24/ R25/ R26/ R27/
C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27
PCF8578
30
SDA SCL SYNC CLK
VSS
SA0
TEST
OSC V DD V2
V3
V4
R31/ R30/ R29/ R28/
V5 VLCD n.c. n.c. C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28
R OSC
MSA844
Product specification
PCF8578
Fig.22 Stand-alone application using 8 rows and 32 columns.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
R7
b
g
one line of 24 digits 7 segment
one line of 12 digits star-burst
(mux 1:16)
Total: 384 segments
c
dp
d
LCD
R8
R15
12
1
AM
R
EE
DISPLAY
RAM
PCF8578
C16
C17
,,
,
,
,,
,,,,
16
0
FR
31
(Using 1:16 mux, the first
character data must be
loaded in bank 0 and 1
starting at byte number 16)
Philips Semiconductors
f
e
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14
PCF8578: Segment Driver
Application
a
R0
C39
,,
,,,,
,,
,,
39
17
Bank
0
1
ALTERNATE DISPLAY BANK
(1)
ALTERNATE DISPLAY BANK
a LSB
b
f
g
c
e
d
dp
MSB
2
3
MLB423
1-byte
Product specification
Fig.23 Segment driver application for up to 384 segments.
PCF8578
(1) Can be used for creating blinking characters.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
V DD
C
V2
C
R
C
(4 2 3)R
V4
R
R
SA0
32
VSS
VSS
40
columns
unused columns
VSS
VLCD
VLCD
16)
8
PCF8578
(ROW MODE)
V5
C
LCD DISPLAY
rows
V3
C
1:32 multiplex rate
32 x 40 x k dots (k
(20480 dots max.)
32
R
Philips Semiconductors
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14
V DD
V DD
V DD
SDA SCL CLK SYNC
VSS
V DD
V DD
VLCD
A2
V3
A0
V DD
V DD
A0
A2
V3
A3
V4
VSS SYNC CLK SCL SDA SA0
A3
V4
VSS SYNC CLK SCL SDA SA0
V4
VSS SYNC CLK SCL SDA SA0
VSS
VSS
VSS
1
PCF8579
A1
subaddress k 1
VLCD
V3
R OSC
A0
40
columns
subaddress 1
A1
VLCD
OSC
40
columns
subaddress 0
VSS
2
PCF8579
VSS
k
PCF8579
A1
A2
A3
VSS
V DD
SCL
SDA
MSA845
Product specification
PCF8578
Fig.24 Typical LCD driver system with 1 : 32 multiplex rate.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
V4
2
PCF8579
A1
VLCD
SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
k
V4
PCF8579
A1
V LCD
A0
V DD
subaddress k 1
A0
V DD
40
columns
V DD
33
R
subaddress 1
C
R
V2
16
rows
V3
C
R
C
R
V4
PCF8578
(ROW MODE)
V5
C
R
SA0
V LCD
VLCD
VSS
VSS
LCD DISPLAY
rows
8
40
columns
unused columns
V DD
VSS / V DD
V DD
SDA SCL CLK SYNC
1:16 multiplex rate
16 x 40 x k dots (k
(10240 dots max.)
16)
A0
V DD
V DD
A1
V DD
V4
VLCD
V DD
40
columns
V DD
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
VSS
VSS
VSS
VSS
VLCD
A2
V3
A0
A3
2
PCF8579
A1
subaddress k 1
V3
1
PCF8579
VSS
V DD
40
columns
subaddress 1
A0
1
PCF8579
A0
V DD
subaddress 0
40
columns
subaddress 0
A2
A2
V4
VSS
16)
SA0 SDA SCL CLK SYNC VSS
A3
V3
VLCD
V3
R OSC
1:16 multiplex rate
16 x 40 x k dots (k
(10240 dots max.)
VSS
A1
VLCD
OSC
V DD
40
columns
16
V DD
C
V DD
VSS
Philips Semiconductors
V DD
VSS
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14
V DD
k
PCF8579
A1
A2
VSS
V DD
SCL
SDA
MSA847
Product specification
PCF8578
Fig.25 Split screen application with 1 : 16 multiplex rate for improved contrast.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
V4
2
PCF8579
A1
VLCD
SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
k
V4
PCF8579
A1
V LCD
A0
V DD
V DD
34
C
R
C
R
rows
V3
PCF8578
(ROW MODE)
V5
C
R
SA0
V LCD
VLCD
VSS
VSS
1:32 multiplex rate
32 x 40 x k dots (k
(20480 dots max.)
16)
1:32 multiplex rate
32 x 40 x k dots (k
(20480 dots max.)
16)
VSS
SA0 SDA SCL CLK SYNC VSS
A3
V3
A2
V4
1
PCF8579
A1
VLCD
A0
V DD
V DD
V DD
40
columns
subaddress 0
32
C
V4
40
columns
32
(4 2 3)R
R
V DD
subaddress 1
LCD DISPLAY
V2
C
A0
V DD
40
columns
subaddress k 1
V DD
V DD
VSS
Philips Semiconductors
V DD
VSS
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14
V DD
8
40
columns
unused columns
V DD
VSS / V DD
V DD
SDA SCL CLK SYNC
V DD
A0
V DD
V DD
V3
A3
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
V4
A3
VSS SYNC CLK SCL SDA SA0
VSS
VSS
VSS
1
PCF8579
VSS
2
PCF8579
A1
VLCD
A2
V3
A0
A2
V4
R OSC
V DD
subaddress k 1
VLCD
V3
VSS
A0
40
columns
subaddress 1
A1
VLCD
OSC
40
columns
subaddress 0
VSS
k
PCF8579
A1
A2
VSS
V DD
SCL
SDA
MSA846
Product specification
PCF8578
Fig.26 Split screen application with 1 : 32 multiplex rate.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
SDA
V DD
V
LCD
R0
(4 2 3)R
R
R
R OSC
R
R
n.c.
n.c.
LCD DISPLAY
Philips Semiconductors
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14
VSS
SCL
PCF8578
35
R31/C31
C0
C27
C28
PCF8579
C39
C0
C27
C28
C39
PCF8579
c.
n.
c.
n.
Fig.27 Example of single plane wiring, single screen with 1 : 32 multiplex rate (PCF8578 in row driver mode).
Product specification
MSA852
PCF8578
to other
PCF8579s
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
15 CHIP DIMENSIONS AND BONDING PAD LOCATIONS
OSC
4.88
mm
SA0
TEST
VSS
CLK
SYNC
SCL
SDA
R0
R1
R2
R3
R4
y
7
6
5
4
3
2
1
54
53
52
51
50
8
VDD
9
V2
10
V3
11
V4
12
V5
13
VLCD
14
R5
48
R6
47
R7
46
R8/C8
45
R9/C9
44
R10/C10
43
R11/C11
42
R12/C12
41
R13/C13
40
R14/C14
39
R15/C15
38
R16/C16
37
R17/C17
36
R18/C18
35
R19/C19
34
R20/C20
0
0
C39
15
C38
16
C37
17
C36
18
33
R21/C21
C35
19
32
R22/C22
R31/C31
R30/C30
27
28
29
30
31
R23/C23
C32
26
R24/C24
C33
25
R25/C25
24
R26/C26
23
R27/C27
22
R28/C28
21
R29/C29
20
C34
PCF8578
3.06 mm
Chip area: 14.93 mm2.
Bonding pad dimensions: 120 µm × 120 µm.
The numbers given in the small squares refer to the pad numbers.
Fig.28 Bonding pad locations.
2003 Apr 14
49
36
MBH589
x
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
Table 15 Bonding pad locations (dimensions in µm); all x/y coordinates are referenced to centre of chip, see Fig.28
PINS
PAD NUMBER
SYMBOL
x
y
VSO56
LQFP64
1
SDA
174
2241
1
7
2
SCL
−30
2241
2
8
3
SYNC
−234
2241
3
9
4
CLK
−468
2241
4
10
5
VSS
−726
2241
5
11
6
TEST
−1014
2241
6
12
7
SA0
−1308
2241
7
13
8
OSC
−1308
1917
8
16
9
VDD
−1308
1113
9
20
10
V2
−1308
873
10
21
11
V3
−1308
663
11
22
12
V4
−1308
459
12
23
13
V5
−1308
255
13
24
14
VLCD
−1308
51
14
25
15
C39
−1308
−1149
17
29
16
C38
−1308
−1353
18
30
17
C37
−1308
−1557
19
31
18
C36
−1308
−1773
20
32
19
C35
−1308
−1995
21
33
20
C34
−1308
−2241
22
34
21
C33
−1014
−2241
23
35
22
C32
−726
−2241
24
37
23
R31/C31
−468
−2241
25
38
24
R30/C30
−234
−2241
26
39
25
R29/C29
−30
−2241
27
40
26
R28/C28
174
−2241
28
41
27
R27/C27
468
−2241
29
42
28
R26/C26
672
−2241
30
43
29
R25/C25
876
−2241
31
44
30
R24/C24
1080
−2241
32
45
31
R23/C23
1308
−2241
33
46
32
R22/C22
1308
−1977
34
48
33
R21/C21
1308
−1731
35
49
34
R20/C20
1308
−1515
36
50
35
R19/C19
1308
−1305
37
51
36
R18/C18
1308
−1101
38
52
37
R17/C17
1308
−897
39
53
38
R16/C16
1308
−693
40
54
2003 Apr 14
37
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
PINS
PAD NUMBER
SYMBOL
x
y
VSO56
LQFP64
39
R15/C15
1308
−489
41
55
40
R14/C14
1308
−285
42
56
41
R13/C13
1308
−81
43
57
42
R12/C12
1308
123
44
58
43
R11/C11
1308
351
45
59
44
R10/C10
1308
603
46
60
45
R9/C9
1308
1101
47
61
46
R8/C8
1308
1305
48
62
47
R7
1308
1515
49
63
48
R6
1308
1731
50
64
49
R5
1308
1977
51
1
50
R4
1308
2241
52
2
51
R3
1080
2241
53
3
52
R2
876
2241
54
4
53
R1
672
2241
55
5
54
R0
468
2241
56
6
−
n.c.
−
−
15, 16
14, 15, 17 to 19,
26 to 28, 36, 47
2003 Apr 14
38
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
VSS
CLK
SYNC
SCL
SA
O
R
O
SC
0
SC
SDA
A2
A1
A0
0
D
V
D
CLK
L
A
SD
SYNC
V
3
C
SC
2
N
R
c.
LK
1
SY
R
VSS
n.
V
V 5
LC
D
ST
0
C
S
VS
A
R
V4
VLCD
TE
SD
V
4
SA
C
L
SC
V
V 2
3
LK
C
V
D
A3
D
ST
TE
S
VS
N
SY
V3
Philips Semiconductors
V4
VLCD
LCD row/column driver for
dot matrix graphic displays
VDD
V3
16 CHIP-ON-GLASS INFORMATION
2003 Apr 14
VDD
0
V
V 4
LC
D
C
SCL
1
C
C
38
C
39
SDA
C
C
37
C
38
39
39
PCF8578
PCF8579
R0 to R31
C1
C2
MSA850
If inputs SA0 and A0 to A3 are left unconnected they are internally pulled to VDD.
Fig.29 Typical chip-on-glass application (viewed from the underside of the chip).
PCF8578
LCD
DISPLAY
Product specification
C0
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
17 PACKAGE OUTLINES
VSO56: plastic very small outline package; 56 leads
SOT190-1
D
E
A
X
c
y
HE
v M A
Z
56
29
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
detail X
28
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
3.3
0.3
0.1
3.0
2.8
0.25
0.42
0.30
0.22
0.14
21.65
21.35
11.1
11.0
0.75
15.8
15.2
2.25
1.6
1.4
1.45
1.30
0.2
0.1
0.1
0.90
0.55
0.13
0.012
0.004
0.12
0.11
0.01
0.017 0.0087 0.85
0.012 0.0055 0.84
inches
0.44
0.62
0.0295
0.43
0.60
0.063
0.089
0.055
0.057
0.035
0.008 0.004 0.004
0.051
0.022
θ
Notes
1. Plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
97-08-11
03-02-19
SOT190-1
2003 Apr 14
EUROPEAN
PROJECTION
40
o
7
0o
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
1
detail X
16
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
1.45
1.05
7
0o
1.45
1.05
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT314-2
136E10
MS-026
2003 Apr 14
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
41
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
If wave soldering is used the following conditions must be
observed for optimal results:
18 SOLDERING
18.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
18.2
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferably be kept:
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
• below 220 °C for all the BGA packages and packages
with a thickness ≥ 2.5mm and packages with a
thickness <2.5 mm and a volume ≥350 mm3 so called
thick/large packages
18.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
• below 235 °C for packages with a thickness <2.5 mm
and a volume <350 mm3 so called small/thin packages.
18.3
Wave soldering
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 Apr 14
Manual soldering
42
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
18.5
PCF8578
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO, VSSOP
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Apr 14
43
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
19 DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
20 DEFINITIONS
21 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Apr 14
44
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 Apr 14
45
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
NOTES
2003 Apr 14
46
Philips Semiconductors
Product specification
LCD row/column driver for
dot matrix graphic displays
PCF8578
NOTES
2003 Apr 14
47
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/05/pp48
Date of release: 2003
Apr 14
Document order number:
9397 750 11026