INTEGRATED CIRCUITS DATA SHEET PCF2105 LCD controller/driver Product specification Supersedes data of 1997 Dec 08 File under Integrated Circuits, IC12 1998 Jul 30 Philips Semiconductors Product specification LCD controller/driver PCF2105 CONTENTS 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.6.1 9.6.2 9.7 9.8 9.9 9.10 9.11 Display control D C B Cursor/display shift Function set DL (parallel mode only) N and M Set CGRAM address Set DDRAM address Read busy flag and address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM 10 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) 11 INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 11.2 11.3 11.4 11.5 11.6 Characteristics of the I2C-bus Bit transfer START and STOP conditions System configuration Acknowledge I2C-bus protocol 12 LIMITING VALUES 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 3.1 3.2 Packages Available types 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 PAD FUNCTIONS 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 RS: Register Select (parallel control) R/W: read/write (parallel control) E: data bus clock (parallel control) DB7 to DB0: data bus (parallel control) C60 to C1: column driver outputs R32 to R1: row driver outputs VLCD: LCD power supply OSC: oscillator SCL: serial clock line SDA: serial data line SA0: address input T1: test input 8 FUNCTIONAL DESCRIPTION 13 HANDLING 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 LCD bias voltage generator Oscillator External clock Power-on reset Registers Busy flag Address Counter (AC) Display Data RAM (DDRAM) Character Generator ROM (CGROM) Character Generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Programming of the MUX rate 1 : 16 Programming of the MUX rate 1 : 32 Reset function 14 DC CHARACTERISTICS 15 AC CHARACTERISTICS 16 TIMING DIAGRAMS 17 APPLICATION INFORMATION 17.1 17.3 17.4 17.5 4-bit operation, 2 × 12 display using internal reset 8-bit operation, 2 × 12 display using internal reset 8-bit operation, 2 × 24 display I2C-bus operation, 2 × 12 display Initializing by instruction 18 BONDING PAD LOCATIONS 19 DEFINITIONS 20 LIFE SUPPORT APPLICATIONS 9 INSTRUCTIONS 21 PURCHASE OF PHILIPS I2C COMPONENTS 9.1 9.2 9.3 9.3.1 9.3.2 Clear display Return home Entry mode set I/D S 1998 Jul 30 17.2 2 Philips Semiconductors Product specification LCD controller/driver 1 PCF2105 FEATURES • Single chip Liquid Crystal Display (LCD) controller/driver • 1 or 2-line display of up to 24 characters per line, or 2 or 4-line display of up to 12 characters per line • 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese syllabary) and user-defined symbols • On-chip generation of intermediate LCD bias voltages Furthermore, a fast I2C-bus interface (400 kHz) is provided. • On-chip oscillator requires no external components (external clock also possible) The PCF2105 is optimized for chip-on-glass applications. • Display data RAM: 80 characters A specific letter code ‘M’ for a character set is programmed in the Character Generator ROM (CGROM) (see Fig.5). • Character generator ROM: 240 characters The PCF2105 is a low power CMOS LCD controller/driver, designed to drive a split screen dot matrix LCD of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with a 5 × 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages which results in a minimum of external components and lower system power consumption. To allow partial VDD shutdown the ESD protection system of the SCL and SDA pads does not use a diode connected to VDD. • Character generator RAM: 16 characters • 4 or 8-bit parallel bus or 2-wire I2C-bus interface (400 kHz) • CMOS and TTL compatible • 32 row, 60 column outputs • Multiplex (MUX) rates 1 : 32 and 1 : 16 • Uses common 11-code instruction set • Logic supply voltage range: VDD − VSS = 2.5 to 6 V • Display supply voltage range: VDD − VLCD = 3.5 to 9 V • I2C-bus address selection (SA0): 011101. The chip contains a character generator and displays alphanumeric and kana characters. The PCF2105 interfaces to most microcontrollers via a 4 or 8-bit parallel bus, or via the 2-wire I2C-bus. 2 3.1 • Low power consumption APPLICATIONS • PCF2105MU/2: chip with bumps in tray. • Telecom equipment • Portable instruments 3.2 • Point-of-sale terminals. 3 Packages Available types • PCF2105MU/2: character set ‘M’ in CGROM. GENERAL DESCRIPTION The PCF2105 integrated circuit is similar to the PCF2114x (described in the “PCF2116 family” data sheet) but does not contain the high voltage generator of that device. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF2105MU/2 1998 Jul 30 − DESCRIPTION chip with bumps in tray 3 VERSION − Philips Semiconductors Product specification LCD controller/driver 5 PCF2105 BLOCK DIAGRAM R32 to R1 C60 to C1 handbook, full pagewidth 21 to 80 (1) 60 V LCD 111 BIAS VOLTAGE GENERATOR 32 ROW DRIVERS COLUMN DRIVERS 60 6 32 SHIFT REGISTER 32-BIT DATA LATCHES 60 SHIFT REGISTER 5 x 12-bit 5 PCF2105 CURSOR + DATA CONTROL VDD V SS T1 5 2 CHARACTER GENERATOR RAM (CGRAM) 16 CHARACTERS 4 101 CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS OSCILLATOR 1 TIMING GENERATOR 8 DISPLAY DATA RAM (DDRAM) 80 CHARACTERS 7 7 DISPLAY ADDRESS COUNTER ADDRESS COUNTER (AC) 7 POWER - ON RESET INSTRUCTION DECODER 8 8 DATA REGISTER (DR) 8 BUSY FLAG INSTRUCTION REGISTER (IR) 7 8 I/O BUFFER 8 102 to 109 98 100 99 97 110 3 MGK846 DB7 to DB0 E R/W RS (1) Pads 5 to 8 and 9 to 12 correspond with symbols R8 to R5 and R32 to R29. Pads 13 to 20 and 81 to 88 correspond with symbols R24 to R17 and R9 to R16. Pads 89 to 92 and 93 to 96 correspond with symbols R25 to R28 and R1 to R4. Fig.1 Block diagram. 1998 Jul 30 4 SCL SDA SA0 OSC Philips Semiconductors Product specification LCD controller/driver 6 PCF2105 PINNING SYMBOL PAD I/O DESCRIPTION OSC 1 I oscillator/external clock input VDD 2 − logic supply voltage SA0 3 I I2C-bus address selection input 4 − logic ground R8 to R5 5 to 8 O LCD row driver outputs R32 to R29 9 to 12 O LCD row driver outputs R24 to R17 13 to 20 O LCD row driver outputs C60 to C1 21 to 80 O LCD column driver outputs R9 to R16 81 to 88 O LCD row driver outputs R25 to R28 89 to 92 O LCD row driver outputs R1 to R4 VSS 93 to 96 O LCD row driver outputs SCL 97 I I2C-bus serial clock input E 98 I data bus clock input RS 99 I register select input R/W 100 I read/write input T1 101 I test input DB7 to DB0 102 to 109 I/O 8-bit bidirectional data bus input/output SDA 110 I/O I2C-bus serial data input/output VLCD 111 I 7 7.1 LCD supply voltage input PAD FUNCTIONS 7.4 The bidirectional, 3-state data bus transfers data between the system controller and the PCF2105. DB7 acts as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations, DB7 to DB4 are used and DB3 to DB0 must be left open-circuit. There is an internal pull-up resistor on each of the data lines. Note that pads DB7 to DB0 must be left open-circuit when I2C-bus control is used. RS: Register Select (parallel control) Bit RS selects the register to be accessed for read and write when the device is controlled by the parallel interface. RS = 0 selects the instruction register for write and the busy flag and address counter for read. RS = 1 selects the data register for both read and write. There is an internal pull-up resistor on pad RS. 7.2 R/W: read/write (parallel control) 7.5 R/W selects either the read (R/W = 1) or write (R/W = 0) operation when control is by the parallel interface. There is an internal pull-up resistor on pad R/W. 7.3 DB7 to DB0: data bus (parallel control) C60 to C1: column driver outputs Pads C60 to C1 output the data for pairs of columns. This arrangement permits optimized Chip-On-Glass (COG) layout for 4-line by 12 characters. E: data bus clock (parallel control) 7.6 Pad E should be HIGH to signal the start of a read or write operation when the device is controlled by the parallel interface. Data is clocked in or out of the chip on the falling edge of the clock. Note that pad E must be connected to VSS (logic 0) when I2C-bus control is used. R32 to R1: row driver outputs Pads R32 to R1 output the row select waveforms to the left and right halves of the display. 7.7 VLCD: LCD power supply Negative power supply for the liquid crystal display. 1998 Jul 30 5 Philips Semiconductors Product specification LCD controller/driver 7.8 PCF2105 8.2 OSC: oscillator Oscillator When the on-chip oscillator is used, pad OSC must be connected to VDD. An external clock signal, if used, is input at pad OSC. The on-chip oscillator provides the clock signal for the display system. No external components are required. Pad OSC must be connected to VDD. 7.9 8.3 SCL: serial clock line Pad SCL is input for the I2C-bus clock signal. 7.10 If an external clock is to be used, it must be input at pad OSC. The resulting display frame frequency is given f osc by f frame = -----------2304 A clock signal must always be present, otherwise the LCD may be frozen in a DC state. SDA: serial data line Pad SDA is input/output for the I2C-bus data line. 7.11 SA0: address input The hardware subaddress line is used to program the device subaddress for 2 different PCF2105s on the same I2C-bus. 7.12 8.4 T1: test input 8.5 Figure 1 shows the block diagram for the PCF2105. Details are explained in subsequent sections. The IR stores instruction codes such as ‘clear display’ and ‘cursor shift’, and address information for the DDRAM and CGRAM. The system controller can write data to but can not read data from the instruction register. LCD bias voltage generator The intermediate bias voltages for the LCD are generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system power consumption. The optimum levels depend on the multiplex (MUX) rate and are selected automatically when the number of lines in the display is defined. The DR temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM (corresponding to the address in the address counter) is written to the DR prior to being read by the ‘read data’ instruction. The optimum value of the LCD operating voltage VOP depends on the MUX rate, the LCD threshold voltage Vth and the number of bias levels. The relationships, together with the discrimination ratio (D) are given in Table 1. 8.6 Busy flag The Busy Flag (BF) indicates the free or busy status of the PCF2105. Bit BF = 1 indicates that the chip is busy and further instructions will not be accepted. The BF is output at pad DB7 when bit RS = 0 and bit R/W = 1. Instructions should only be written after checking that BF = 0 or waiting for the required number of clock cycles. Using a 5-level bias scheme for MUX rate 1 : 16 allows VOP < 5 V for most LCDs. The effect on the display contrast is negligible. Table 1 Registers The PCF2105 has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select (RS) signal determines which register will be accessed. FUNCTIONAL DESCRIPTION 8.1 Power-on reset The Power-on reset block initializes the chip after power-on or power failure. Pad T1 must be connected to VSS. Not user accessible. 8 External clock Optimum values for VOP 8.7 MUX RATE NUMBER OF BIAS LEVELS v OP ---------v th V on D = --------V off 1 : 16 5 3.67 1.277 1 : 32 6 5.19 1.196 1998 Jul 30 Address Counter (AC) The AC assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions ‘set CGRAM address’ and ‘set DDRAM address’. After a read/write operation the AC is automatically incremented or decremented by 1. The AC contents are output to the bus (pads DB6 to DB0) when bit RS = 0 and bit R/W =1. 6 Philips Semiconductors Product specification LCD controller/driver 8.8 PCF2105 8.11 Display Data RAM (DDRAM) Cursor control circuit The DDRAM stores up to 80 characters of display data, represented by 8-bit character codes. DDRAM locations not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping scheme is shown in Fig.2. With no display shift, the characters represented by the codes in the first 12 or 24 DDRAM locations, starting at address 00 in line 1, are displayed. Subsequent lines display data starting at addresses 20, 40, or 60 hexadecimal (hex). Figures 3 and 4 show the DDRAM-to-display mapping scheme when the display is shifted. The cursor control circuit generates the cursor (underline and/or character blink as shown in Fig.7) at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited. The address range for a 1-line display is 00 to 4F; for a 2-line display from 00 to 27 (line 1) and 40 to 67 (line 2); for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and 60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and 4-line displays the end address of one line and the start address of the next line are not successive. When the display is shifted each line wraps around independently of the others (see Figs 3 and 4). 8.13 8.12 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. LCD row and column drivers The PCF2105 contains 32 row drivers and 60 column drivers. They connect the appropriate LCD bias voltages in sequence to the display, in accordance with the data to be displayed. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 8 and 9 show typical waveforms. In the 1-line display (MUX rate 1 : 16), the row outputs are driven in pairs, for example R1/R17 and R2/R18. This allows the output pairs to be connected in parallel, thereby providing greater drive capability. When data is written to the DDRAM, wrap-around occurs from 4F to 00 in 1-line display and from 27 to 40 and 67 to 00 in 2-line display; from 13 to 20, 33 to 40, 53 to 60 and 73 to 00 in 4-line display. Unused outputs should be left unconnected. 8.9 Character Generator ROM (CGROM) The CGROM generates 240 character patterns in 5 × 8 dot format from 8-bit character codes. Figure 5 shows the character set currently available. 8.10 Character Generator RAM (CGRAM) Up to 16 user-defined characters may be stored in the CGRAM. The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.5). Figure 6 shows the addressing principle for the CGRAM. 1998 Jul 30 7 Philips Semiconductors Product specification LCD controller/driver PCF2105 Display handbook, 4 columns 1 Position (decimal) 2 3 4 5 22 23 24 00 01 02 03 04 DDRAM Address (hex) non-displayed DDRAM addresses 15 16 17 18 19 4C 4D 4E 4F 1-line display non-displayed DDRAM address DDRAM Address (hex) 00 01 02 03 04 15 16 17 18 19 24 25 26 27 line 1 40 41 42 43 44 55 56 57 58 59 64 65 66 67 line 2 MLA792 2-line display non-displayed DDRAM addresses handbook, 4 columns 1 2 3 4 5 6 7 8 9 10 11 12 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 line 1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 line 2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 line 3 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 line 4 DDRAM Address (hex) 4 line display MLA793 Fig.2 DDRAM-to-display mapping; no shift. 1998 Jul 30 8 Philips Semiconductors Product specification LCD controller/driver Display Position (decimal) DDRAM Address (hex) DDRAM Address (hex) 1 2 3 4 PCF2105 5 22 23 24 4F 00 01 02 03 14 15 16 Display Position (decimal) DDRAM Address (hex) 1-line display 27 00 01 02 03 14 15 16 line 1 67 40 41 42 43 54 55 56 line 2 2 3 4 22 23 24 01 02 03 04 05 16 17 18 1-line display 01 02 03 04 05 16 17 18 line 1 41 42 43 44 45 56 57 58 line 2 2-line display 1 2 8 9 10 11 12 MLA815 3 4 5 6 7 8 9 10 11 12 13 00 01 02 03 04 05 06 07 08 09 0A line 1 01 02 03 04 05 06 07 08 09 0A 0B 0C line 1 33 20 21 22 23 24 25 26 27 28 29 2A line 2 21 22 23 24 25 26 27 28 29 2A 2B 2C line 2 DDRAM DDRAM Address (hex) Address (hex) 53 40 41 42 43 44 45 46 47 48 49 4A line 3 41 42 43 44 45 46 47 48 49 4A 4B 4C line 3 73 60 61 62 63 64 65 66 67 68 69 6A line 4 61 62 63 64 65 66 67 68 69 6A 6B 6C line 4 4-line display MLA803 4-line display Fig.3 DDRAM-to-display mapping; right shift. 1998 Jul 30 5 MLA802 2-line display 1 2 3 4 5 6 7 DDRAM Address (hex) 1 MLA816 Fig.4 DDRAM-to-display mapping; left shift. 9 Philips Semiconductors Product specification LCD controller/driver PCF2105 handbook, full pagewidth upper 4 bits 0000 xxxx 0000 CG RAM 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 4 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MGK847 Fig.5 Character set ‘M’ in CGROM. 1998 Jul 30 10 Philips Semiconductors Product specification LCD controller/driver character codes (DDRAM data) handbook, full pagewidth 7 6 5 4 3 2 higher order bits 0 0 PCF2105 0 0 0 0 CGRAM address 1 0 6 lower order bits 0 0 0 0 0 0 0 0 5 4 3 2 higher order bits 0 1 0 0 0 0 0 0 character patterns (CGRAM data) 1 0 lower order bits 0 1 4 3 higher order bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 2 1 0 lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 1 cursor position character pattern example 2 MGA800 - 1 Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in this figure. CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data is logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ instruction. Bit 6 can be set using the ‘set DDRAM address’ instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address’ instruction. Fig.6 Relationship between CGRAM addresses, data and display patterns. 1998 Jul 30 11 Philips Semiconductors Product specification LCD controller/driver PCF2105 cursor MGA801 5 x 7 dot character font alternating display cursor display example blink display example Fig.7 Cursor and blink display examples. 1998 Jul 30 12 Philips Semiconductors Product specification LCD controller/driver PCF2105 frame n handbook, full pagewidth frame n 1 state 1 (ON) state 2 (ON) VDD V2 V3 /V4 V5 V LCD ROW 1 VDD V2 ROW 9 V3 /V4 V5 V LCD 1-line display (1:16) VDD V2 V3 /V4 V5 V LCD ROW 2 VDD V2 V3 /V4 V5 V LCD COL 1 VDD V2 V3 /V4 V5 V LCD COL 2 VOP 0.25 VOP state 1 0 V 0.25 VOP VOP VOP 0.25 VOP state 2 0 V 0.25 VOP VOP MGA802 - 1 1 2 3 16 1 2 3 Fig.8 Typical LCD waveforms; 1-line display. 1998 Jul 30 13 16 Philips Semiconductors Product specification LCD controller/driver PCF2105 frame n 1 frame n handbook, full pagewidth ROW 1 V DD V2 V3 V4 V5 V LCD ROW 9 V DD V2 V3 V4 V5 V LCD ROW 2 V DD V2 V3 V4 V5 V LCD COL 1 V DD V2 V3 V4 V5 V LCD COL 2 V DD V2 V3 V4 V5 V LCD state 1 (ON) state 2 (ON) 2-line display (1:32) VOP state 1 0.15 VOP 0V 0.15 VOP VOP VOP state 2 0.15 VOP 0V 0.15 VOP VOP MGA803 - 1 123 32 1 2 3 32 Fig.9 Typical LCD waveforms; 2-line display. 1998 Jul 30 14 Philips Semiconductors Product specification LCD controller/driver 8.14 PCF2105 To program the MUX rate 1 : 16, bits M and N of the ‘function set’ instruction must be set to logic 0 (see Table 3). Figures 10, 11 and 12 show the DDRAM addresses of the display characters. The second row of each figure corresponds to either the right half of a 1-line display or to the second line of a 2-line display. Wrap around of data during display shift or when writing data is non-standard. Programming of the MUX rate 1 : 16 With the MUX rate 1 : 16 the PCF2105 can be used in the following ways: • To drive a 1-line display of 24 characters • To drive a 2-line display of 12 characters, resulting in better contrast. The internal data flow of the chip is optimized for this purpose. handbook, full pagewidth display position 1 2 3 4 5 6 7 8 9 10 11 12 DDRAM address 00 01 02 03 04 05 06 07 08 09 0A 0B 24 display position 13 14 15 16 17 18 19 20 21 22 23 DDRAM address 0C 0D 0E 0F 10 11 12 13 14 15 16 17 MLB899 Fig.10 DDRAM-to-display mapping; no shift. handbook, full pagewidth display position DDRAM address 1 2 3 4 5 6 7 8 9 10 11 12 4F 00 01 02 03 04 05 06 07 08 09 0A display position 13 14 15 16 17 18 19 20 21 22 23 24 DDRAM address 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 MLB900 Fig.11 DDRAM-to-display mapping; right shift. handbook, full pagewidth display position 1 2 3 4 5 6 7 8 9 10 11 12 DDRAM address 01 02 03 04 05 06 07 08 09 0A 0B 0C 24 display position 13 14 15 16 17 18 19 20 21 22 23 DDRAM address 0D 0E 0F 10 11 12 13 14 15 16 17 18 MLB901 Fig.12 DDRAM-to-display mapping; left shift. 1998 Jul 30 15 Philips Semiconductors Product specification LCD controller/driver 8.15 PCF2105 Instructions are of 4 categories, those that: Programming of the MUX rate 1 : 32 With the MUX rate 1 : 32 the PCF2105 can be used in the following ways: 1. Designate PCF2105 functions such as display format, data length, etc. • To drive a 2-line display of 24 characters, use instruction ‘function set’ to set bit M to logic 0 and bit N to logic 1 2. Set internal RAM addresses • To drive a 4-line display of 12 characters, use instruction ‘function set’ to set both bits M and N to logic 1. 4. Others. 8.16 3. Perform data transfer with internal RAM In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, thus enabling the designer to develop systems in minimum time with maximum programming efficiency. Reset function The PCF2105 automatically initializes (resets) when power is turned on. The state after reset is given in Table 2 (see Tables 3 and 4 for the description of the bits). Table 2 State after reset STEP During internal operation, no instruction other than the ‘read busy flag and address’ will be executed. DESCRIPTION 1 clear display 2 function set: Because the busy flag is set to logic 1 while an instruction is being executed, it is advisable to ensure that the flag is set to logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 3. An instruction sent while the busy flag is HIGH will not be executed. bit DL = 1: 8-bit interface bits M and N = 0: 1-line display bit G = 0: not used 3 display control: bit D = 0: display off 9.1 bit C = 0: cursor off ‘Clear display’ writes space code 20 (hexadecimal) into all DDRAM addresses (the character pattern for character code 20 must be a blank pattern), sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. Consequently, the display disappears and the cursor or blink position goes to the left edge of the display (the first line if 2 or 4 lines are displayed) and sets bit I/D of ‘entry mode set’ to logic 1 (increment mode). Bit S of ‘entry mode set’ does not change. bit B = 0: blink off 4 entry mode set: bit I/D = 1: +1(increment) bit G = 0: not used 9 5 default address pointer to DDRAM; the busy flag indicates the busy state (BF = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 10 and 11. 6 I2C-bus interface reset The instruction ‘clear display’ requires extra execution time. This may be allowed for checking the Busy Flag (BF) or by waiting until 2 ms has elapsed. The latter must be applied where no read-back options are available, as in some Chip-On-Glass (COG) applications. INSTRUCTIONS Only two PCF2105 registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF2105 operation is controlled by the instructions shown in Table 3 together with their execution time. Details are explained in subsequent sections. 1998 Jul 30 Clear display 9.2 Return home ‘Return home’ sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the display (the first line if 2 or 4 lines are displayed). Bits I/D and S of ‘entry mode set’ do not change. 16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... INSTRUCTION REQUIRED CLOCK CYCLES(2) R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NOP 0 0 0 0 0 0 0 0 0 0 no operation Clear display 0 0 0 0 0 0 0 0 0 1 clears entire display and sets DDRAM address 00 in Address Counter (AC) 165 Return home 0 0 0 0 0 0 0 0 1 0 sets DDRAM address 00 in the AC; also returns shifted display to original position; DDRAM contents remain unchanged 3 Entry mode set 0 0 0 0 0 0 0 1 I/D S sets cursor move direction and specifies shift of display; these operations are performed during data write and read 3 Display control 0 0 0 0 0 0 1 D C B sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B) 3 Cursor/display shift 0 0 0 0 0 1 S/C R/L 0 0 moves cursor and shifts display without changing DDRAM contents 3 Function set 0 0 0 0 1 DL N M G 0 sets interface data length (DL), number of display lines (N, M) and voltage generator control (G); bit G is not used 3 Set CGRAM address 0 0 0 1 sets CGRAM address 3 Set DDRAM address 0 0 1 ADD sets DDRAM address 3 Read busy flag and address 0 1 BF AC reads BF indicating internal operation is being performed and reads AC contents 0 Read data 1 1 read data reads data from CGRAM or DDRAM 3 Write data 1 0 write data writes data to CGRAM or DDRAM 3 17 RS ACG DESCRIPTION 0 1 2. Example: fosc = 150 kHz, T cy = -------- = 6.67 µs ; 3 cycles = 20 µs; 165 cycles = 1.1 ms. f osc PCF2105 1. In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed. In the I2C-bus mode a control byte is required when bit RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0. Product specification Notes Philips Semiconductors Instructions (note 1) LCD controller/driver 1998 Jul 30 Table 3 Philips Semiconductors Product specification LCD controller/driver Table 4 PCF2105 Command bit identities, used in Table 3 BIT LOGIC 0 LOGIC 1 I/D decrement increment S display freeze display shift D display off display on C cursor off cursor on B character at cursor position does not blink character at cursor position blinks S/C cursor move display shift R/L left shift right shift DL 4 bits 8 bits N (M = 0) 2 lines × 12 characters; MUX rate 1 : 16 2 lines × 24 characters; MUX rate 1 : 32 N (M = 1) reserved 4 lines × 12 characters; MUX rate 1 : 32 BF end of internal operation internal operation in progress Co last control byte, only data bytes to follow next two bytes are a data byte and another control byte 9.3 9.3.1 Entry mode set 9.4.3 I/D B When bit I/D = 1 (0), the DDRAM or CGRAM address increments (decrements) by 1 when data is written to or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor and blink are inhibited when the CGRAM is accessed. The character indicated by the cursor blinks when bit B = 1. The blink is displayed by switching between display characters and all dots on with a period of 1 second when fosc = 150 kHz (see Fig.7). At other clock frequencies the blink period is equal to 150 kHz ---------------------f osc 9.3.2 The cursor and the blink can be set to display simultaneously. S When bit S = 1, the entire display shifts either to the right (bit I/D = 0) or to the left (I/D = 1) during a DDRAM write. Consequently, it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = 0 the display does not shift. 9.4 9.4.1 9.5 ‘Cursor/display shift’ moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In the 2 or 4-line display, the cursor moves to the next line when it passes the last position of the line (40 or 20 decimal). When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift. Display control D The display is on when bit D = 1 and off when D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D to logic 1. 9.4.2 C The cursor is displayed when bit C = 1 and inhibited when C = 0. Even if the cursor disappears, the display functions, I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.7). 1998 Jul 30 Cursor/display shift 18 Philips Semiconductors Product specification LCD controller/driver 9.6 PCF2105 Function set 9.6.1 9.9 ‘Read busy flag and address’ reads the Busy Fag (BF). When bit BF = 1 it indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0, so BF should be checked before sending another instruction. DL (PARALLEL MODE ONLY) Bit DL sets the interface data length. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit length is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 are left open (internal pull-ups). At the same time, the value of the AC expressed in binary A[6] to A[0] is read out. The address counter is used by both CGRAM and DDRAM and its value is determined by the previous instruction. DL can not be set to logic 0 from the I2C-bus interface. If DL has been set to logic 0 via the parallel bus, programming via the I2C-bus interface is complicated. 9.6.2 9.10 Whether the CGRAM or DDRAM is to be written to is determined by the previous specification of CGRAM or DDRAM address setting. After writing, the address automatically increments or decrements by 1, in accordance with the ‘entry mode set‘. Only bits D[4] to D[0] of CGRAM data are valid, bits D[7] to D[5] are ‘don’t care’. Set CGRAM address ‘Set CGRAM address’ sets bits 0 to 5 of the CGRAM address (ACG in Table 3) into the AC (binary A[5] to A[0]). Data can then be written to or read from the CGRAM. Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ instruction. Bit 6 can be set using the ‘set DDRAM address’ instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address’ instruction. 9.8 9.11 The most recent ‘set address’ instruction determines whether the CGRAM or DDRAM is to be read. The ‘read data’ instruction gates the content of the Data Register (DR) to the bus while pad E = HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. ‘Set DDRAM address’ sets the DDRAM address (ADD in Table 3) into the AC (binary A[6] to A[0]). Data can then be written to or read from the DDRAM. Hexadecimal address ranges ADDRESS Read data from CGRAM or DDRAM ‘Read data’ reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM. Set DDRAM address Table 5 Write data to CGRAM or DDRAM ‘Write data’ writes binary 8-bit data (D[7] to D[0]) to the CGRAM or the DDRAM. N AND M Bits N and M set the number of display lines. 9.7 Read busy flag and address Remark: the only three instructions that update the DR are: FUNCTION 00 to 4F 1 line of 24 characters • ‘Set CGRAM address’ 00 to 0B and 0C to 4F 2 lines of 12 characters • ‘Set DDRAM address’ 00 to 27 and 40 to 67 2 lines of 24 characters • ‘Read data’ from CGRAM or DDRAM. 00 to 13, 20 to 33, 40 to 53 4 lines of 12 characters and 60 to 73 1998 Jul 30 Other instructions (e.g. ‘write data’, ‘cursor/display shift’, ‘clear display’, ‘return home’) will not change the data register content. 19 Philips Semiconductors Product specification LCD controller/driver PCF2105 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. The 4-bit mode is selected by instruction. See Figs 13, 14 and 15 for examples of bus protocol. 10 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) The PCF2105 can send data in either two 4-bit modes or one 8-bit mode and can thus interface to 4 or 8-bit microcontrollers. In the 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. The control lines E, RS, and R/W are required. In the 4-bit mode, the pads DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally. In the 4-bit mode data is transferred in two cycles of 4-bits each. The higher order bits (corresponding to DB7 to DB4 RS R/W E DB7 IR7 IR3 BF AC3 DR7 DR3 DB6 IR6 IR2 AC6 AC2 DR6 DR2 DB5 IR5 IR1 AC5 AC1 DR5 DR1 DB4 IR4 IR0 AC4 AC0 DR4 DR0 instruction write busy flag and address counter read Fig.13 4-bit transfer example. 1998 Jul 30 20 data register read MGA804 Philips Semiconductors Product specification LCD controller/driver PCF2105 RS R/W E internal internal operation DB7 IR7 IR3 busy instruction write not busy AC3 busy flag check AC3 D7 busy flag check D3 instruction write MGA805 IR7 and IR3: instruction 7th bit and 3rd bit. AC3: address counter 3rd bit. Fig.14 An example of 4-bit data transfer timing sequence. RS R/W E internal DB7 internal operation data instruction write busy busy flag check busy busy flag check not busy busy flag check Fig.15 Example of busy flag check timing sequence. 1998 Jul 30 21 data instruction write MGA806 Philips Semiconductors Product specification LCD controller/driver PCF2105 11 INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 Characteristics of the 11.5 The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.19). I2C-bus The I2C-bus is for bidirectional, 2-line communication between different ICs or modules. The 2 lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 11.2 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH-level period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.16). 11.3 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Fig.17). 11.4 Acknowledge 11.6 I2C-bus protocol Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2105 read and write cycles is illustrated in Figs 20, 21 and 22. System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Fig.18). handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed Fig.16 Bit transfer. 1998 Jul 30 22 MBC621 Philips Semiconductors Product specification LCD controller/driver PCF2105 handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig.17 Definition of START and STOP conditions. MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL MGA807 Fig.18 System configuration. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.19 Acknowledgement on the I2C-bus. 1998 Jul 30 23 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors LCD controller/driver 1998 Jul 30 acknowledgement from PCF2105 S S 0 1 1 1 0 1 A 0 A 1 CONTROL BYTE A A 0 DATA CONTROL BYTE A DATA 0 R/W Co 2n ≥ 0 bytes 1 byte Co n ≥ 0 bytes update data pointer S 0 1 1 1 0 1 A 0 0 MGK848 PCF2105 slave address R/W Product specification Fig.20 Master transmits to slave receiver; write mode. PCF2105 handbook, full pagewidth 24 slave address A P This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... S S 0 1 1 1 0 1 A 0 A 1 CONTROL BYTE A DATA A 0 1 1 CONTROL DATA A (1) Philips Semiconductors LCD controller/driver 1998 Jul 30 acknowledgement from PCF2105 A 0 slave address R/W Co 2 bytes 2n ≥ 0 bytes Co 25 acknowledgement from PCF2105 S SLAVE ADDRESS S A 1 A 0 no acknowledgement from master DATA n bytes A DATA 1 P last byte R/W MGK849 Product specification Fig.21 Master reads after setting word address; write word address, set RS and R/W; read data. PCF2105 (1) Last data byte is a dummy byte (may be omitted). handbook, full pagewidth update data pointer Philips Semiconductors Product specification LCD controller/driver PCF2105 acknowledgement from PCF2105 handbook, full pagewidth S SLAVE ADDRESS S A 1 A 0 acknowledgement from master DATA A n bytes no acknowledgement from master DATA 1 P last byte R/W update data pointer MGK850 Fig.22 Master reads slave immediately after first byte; read mode (RS previously defined). 12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD logic supply voltage −0.5 +8.0 V VLCD LCD supply voltage VDD − 11 VDD V VI(n) input voltage on pads OSC, RS, R/W, E and DB0 to DB7 VSS − 0.5 VDD + 0.5 V VO(n) output voltage on pads R1 to R32, C1 to C60 and VLCD VLCD − 0.5 VDD + 0.5 V II(n) DC input current on every pad −10 +10 mA IO(n) DC output current on every pad −10 +10 mA In current on VDD, VSS and VLCD −50 +50 mA Ptot total power dissipation − 400 mW P/out power dissipation per output − 100 mW Tstg storage temperature −65 +150 °C 13 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ). 1998 Jul 30 26 Philips Semiconductors Product specification LCD controller/driver PCF2105 14 DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD logic supply voltage 2.5 − 6.0 VLCD LCD supply voltage VDD − 9 − VDD − 3.5 V IDD(ext) external supply current note 1 − 200 500 µA VDD = 5 V; VOP = 9 V; fosc = 150 kHz; Tamb = 25 °C − 200 300 µA VDD = 3 V; VOP = 5 V; fosc = 150 kHz; Tamb = 25 °C − 150 200 µA V II(LCD) input current on VLCD note 1 − 50 100 µA VPOR Power-on reset voltage level note 2 − 1.3 1.8 V Logic VIL LOW-level input voltage on pads E, RS, R/W, DB7 to DB0 and SA0 VSS − 0.3VDD V VIH HIGH-level input voltage on pads E, RS, R/W, DB7 to DB0 and SA0 0.7VDD − VDD V VIL(OSC) LOW-level input voltage on pad OSC VSS − VDD − 1.5 V VIH(OSC) HIGH-level input voltage on pad OSC VDD − 0.1 − VDD V Ipu pull-up current on pads DB7 to DB0, RS and R/W pads set to logic 0 (VSS) 0.04 0.15 1.00 µA IOL(DB) LOW-level output current on pads DB7 to DB0 VOL = 0.4 V; VDD = 5 V 1.6 − − mA IOH(DB) HIGH-level output current on pads DB7 to DB0 VOH = 4 V; VDD = 5 V −1.0 − − mA IL leakage current on pads DB7 to DB0, OSC, E, RS, R/W and SA0 pads set to logic 0 (VSS) or logic 1 (VDD) −1 − +1 µA I2C-bus SDA and SCL VIL LOW-level input voltage note 3 VSS − 0.3VDD V VIH HIGH-level input voltage note 3 0.7VDD − VDD V IL leakage current pads set to logic 0 (VSS) or logic 1 (VDD) −1 − +1 µA Ci input capacitance note 4 − − 7 pF IOL(SDA) LOW-level output current on SDA VOL = 0.4 V; VDD = 5 V 3 − − mA 1998 Jul 30 27 Philips Semiconductors Product specification LCD controller/driver SYMBOL PARAMETER PCF2105 CONDITIONS MIN. TYP. MAX. UNIT LCD outputs Ro(ROW) row output resistance on pads R32 to R1 note 5 − 1.5 3 kΩ Ro(COL) column output resistance on pads C60 to C1 note 5 − 3 6 kΩ Vbias(tol) bias voltage tolerance on pads R32 to R1 and C60 to C1 note 6 − ±20 ±130 mV Notes 1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive; internal or external clock with duty factor 50%. 2. Resets all logic when VDD < VPOR. 3. When the voltages are above VDD or below VSS, an input current may flow; this current must not exceed ±0.5 mA. 4. Tested on sample basis. 5. Resistance of output terminals (R32 to R1 and C60 to C1) with load current IL = 150 µA; VOP = VDD − VLCD = 9 V; outputs measured one at a time. 6. LCD outputs open-circuit. 15 AC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER ffr(LCD) LCD frame frequency (internal clock) fosc oscillator frequency (external clock) CONDITIONS note 1 MIN. TYP. MAX. UNIT 40 65 100 Hz 90 150 225 kHz Bus timing characteristics: Parallel Interface; notes 1 and 2 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2105); see Fig.23 Tcy(en) enable cycle time 500 − − ns tW(en) enable pulse width 220 − − ns tsu(A) address set-up time 50 − − ns th(A) address hold time 25 − − ns tsu(D) data set-up time 60 − − ns th(D) data hold time 25 − − ns READ OPERATION (READING DATA FROM PCF2105 TO MICROCONTROLLER); see Fig.24 Tcy(en) enable cycle time 500 − − ns tW(en) enable pulse width 220 − − ns tsu(A) address set-up time 50 − − ns th(A) address hold time 25 − − ns td(D) data delay time − − 150 ns th(D) data hold time 20 − 100 ns 1998 Jul 30 28 Philips Semiconductors Product specification LCD controller/driver SYMBOL PARAMETER PCF2105 CONDITIONS MIN. TYP. MAX. UNIT Timing characteristics: I2C-bus interface; note 2; see Fig.25 fSCL SCL clock frequency − − 400 kHz tSW tolerable spike width on bus − − 50 ns tBUF bus free time 1.3 − − µs tSU;STA set-up time for a repeated START condition 0.6 − − µs tHD;STA START condition hold time 0.6 − − µs tLOW SCL LOW time 1.3 − − µs tHIGH SCL HIGH time 0.6 − − µs tr SCL and SDA rise time note 3 − 20 + RCL 300 ns tf SCL and SDA fall time note 3 − 20 + RCL 300 ns tSU;DAT data set-up time note 4 100 − − ns tHD;DAT data hold time notes 5 and 6 0 − 0.9 µs tSU;STO set-up time for STOP condition 0.6 − − µs CL load capacitance for each bus line − − 400 pF Notes 1. VDD = 5.0 V. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 3. CL = total capacitance of one bus line in pF and R = 100 Ω. 4. A fast mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. 5. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 6. The maximum tHD;DAT has only to be met if the device does not stretch tLOW of the SCL signal. 1998 Jul 30 29 Philips Semiconductors Product specification LCD controller/driver PCF2105 16 TIMING DIAGRAMS handbook, full pagewidth RS VIH VIL VIH VIL tsu(A) R/W th(A) VIL VIL th(A) tW(en) E VIL VIH VIH VIL VIL th(D) tsu(D) VIH VIL valid data DB0 to DB7 VIH VIL MGK851 Tcy(en) Fig.23 Parallel bus write operation sequence; writing data from microcontroller to PCF2105. handbook, full pagewidth RS VIH VIL VIH VIL tsu(A) R/W th(A) VIH VIH tW(en) E VIL VIH th(A) VIH VIL td(D) DB0 to DB7 VIL th(D) VOH VOL VOH VOL Tcy(en) MGK852 Fig.24 Parallel bus read operation sequence; reading data from PCF2105 to microcontroller. 1998 Jul 30 30 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) BIT 0 LSB R/W ACKNOWLEDGE (A) Philips Semiconductors LCD controller/driver 1998 Jul 30 PROTOCOL STOP CONDITION (P) SDA 31 t BUF t LOW tr SCL t HD;STA tf Product specification Fig.25 I2C-bus timing diagram; rise and fall times refer to VIL and VIH. MGA811 - 1 PCF2105 handbook, full pagewidth t HIGH t SU;STO t/fSCL Philips Semiconductors Product specification LCD controller/driver PCF2105 17 APPLICATION INFORMATION handbook, 4 columns P20 RS P21 R/W P22 E 32 R1 to R32 to LCD PCF2105 P80CL51 60 C1 to C60 DB0 to DB7 8 P10 to P17 MGK853 Fig.26 Direct connection to 8-bit microcontroller; 8-bit bus. handbook, 4 columns P10 RS P11 R/W P12 E 32 P80CL51 R1 to R32 to LCD PCF2105 60 C1 to C60 DB4 to DB7 4 P14 to P17 MGK854 Fig.27 Direct connection to 8-bit microcontroller; 4-bit bus. handbook, full pagewidth VLCD VLCD 100 nF VDD 100 nF R7 to R16 R25 to R32 16 R1 to R8 R17 to R24 2 x 24-CHARACTER LCD DISPLAY (SPLIT SCREEN) VDD OSC 16 PCF2105 60 60 VSS C1 to C60 V SS 60 MGK855 8 DB0 to DB7 E RS R/W Fig.28 Typical application using parallel interface. 1998 Jul 30 32 Philips Semiconductors Product specification LCD controller/driver PCF2105 16 handbook, full pagewidth VLCD VLCD R1 to R16 100 nF VDD VDD R17 to R24 OSC 100 nF 16 2 x 24-CHARACTER LCD DISPLAY (SPLIT SCREEN) PCF2105 60 C1 to C60 VDD VDD 60 V SS V SS SCL SDA SA0 VDD VLCD VLCD 100 nF VDD VDD R1 to R16 100 nF OSC 16 2 x 12-CHARACTER LCD DISPLAY PCF2105 60 C1 to C60 V SS MGK856 V SS SCL SDA SA0 VSS SCL SDA MASTER TRANSMITTER PCF84C81 Fig.29 Application using I2C-bus interface. 1998 Jul 30 33 Philips Semiconductors Product specification LCD controller/driver 17.1 PCF2105 4-bit operation, 2 × 12 display using internal reset 17.3 For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 8). It should be noted that both lines of the display are always shifted together, data does not shift from one line to the other. The program must set functions prior to 4-bit operation. Table 6 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2105 attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB3 to DB0, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 6 step 3). 17.4 Thus, DB7 to DB4 of the ‘function set’ are written twice. 17.2 I2C-bus operation, 2 × 12 display A control byte is required with most instructions (see Table 9). 8-bit operation, 2 × 12 display using internal reset 17.5 Table 7 shows an example of a 1-line display in 8-bit operation. The PCF2105 functions must be set by the ‘function set’ instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes the display position only DDRAM contents remain unchanged. Display data entered first can be displayed when the ‘return home’ instruction is performed. 1998 Jul 30 8-bit operation, 2 × 24 display Initializing by instruction If the power supply conditions for correctly operating the internal reset circuit are not met, the PCF2105 must be initialized by instruction. Tables 10 and 11 show how this may be performed for 8-bit and 4-bit operation. 34 Philips Semiconductors Product specification LCD controller/driver Table 6 PCF2105 Example of 4-bit operation; 1-line display; using internal reset STEP INSTRUCTION DISPLAY OPERATION 1 power supply on (PCF2105 is initialized by the internal reset circuit) initialized; no display appears 2 function set sets to 4-bit operation; in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write RS 0 3 0 1 0 R/W DB7 DB6 DB5 DB4 0 0 0 1 0 sets to 4-bit operation; selects 2 × 12 display 0 0 0 0 0 0 4-bit operation starts from this point and resetting is needed display control R/W DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 0 1 1 1 0 _ turns display and cursor on entire display is blank after initialization entry mode set RS 6 0 0 RS 5 0 function set RS 4 R/W DB7 DB6 DB5 DB4 R/W DB7 DB6 DB5 DB4 0 0 0 0 0 0 0 0 0 1 1 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM display is not shifted write data to CGRAM or DDRAM RS R/W DB7 DB6 DB5 DB4 1 0 1 1 0 1 1 0 0 1 1 0 1998 Jul 30 P_ writes ‘P’; the DDRAM has already been selected by initialization at power-on the cursor is incremented by 1 and shifted to the right 35 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... STEP INSTRUCTION 1 power supply on (PCF2105 is initialized by the internal reset function) initialized; no display appears 2 function set sets to 8-bit operation; selects 2 × 12 display RS 0 3 0 0 5 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 36 1 0 0 0 0 0 0 1 1 writes ‘P’; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right PH_ writes ‘H’ R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 1 0 0 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 HILIPS_ writes space ILIPS M_ writes ‘M’ 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 0 0 0 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 0 1 1 0 1 Product specification 1 sets mode for display shift at the time of write R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 write data to CGRAM or DDRAM RS PHILIPS_ PCF2105 1 writes ‘S’ 1 write data to CGRAM or DDRAM RS PHILIPS_ R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 entry mode set RS 11 P_ 0 write data to CGRAM or DDRAM 1 10 sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DDRAM or CGRAM; display is not shifted | | | RS 9 _ R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 7 8 turns display and cursor on; entire display is blank after initialization 0 write data to CGRAM or DDRAM RS _ R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 write data to CGRAM or DDRAM RS 6 0 entry mode set RS OPERATION R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 display control RS 4 DISPLAY Philips Semiconductors Example of 8-bit operation; 1-line display; using internal reset (character set ‘M’) LCD controller/driver 1998 Jul 30 Table 7 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... DISPLAY 12 13 | | | write data to CGRAM or DDRAM RS 1 14 0 0 16 1 37 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 shifts only the cursor position to the left MICROKO shifts only the cursor position to the left ICROCO writes ‘C’ (correction); the display moves to the left MICROCO shifts the display and cursor to the right MICROCO_ shifts only the cursor to the right ICROCOM_ writes ‘M’ 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 1 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 0 1 1 0 1 20 | | | return home 0 PHILIPS M R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 0 returns both display and cursor to the original position (address 0) PCF2105 RS Product specification 21 MICROKO R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 write data to CGRAM or DDRAM RS writes ‘O’ 1 cursor or display shift RS 19 1 cursor or display shift RS 18 1 write data to CGRAM or DDRAM RS 17 0 cursor or display shift RS MICROKO R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 cursor or display shift RS 15 OPERATION Philips Semiconductors INSTRUCTION LCD controller/driver 1998 Jul 30 STEP This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... STEP INSTRUCTION 1 power supply on (PCF2105 is initialized by the internal reset function) initialized; no display appears 2 function set sets to 8-bit operation; selects 2 × 24 display RS 0 3 0 0 5 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CGRAM or DDRAM; display is not shifted P_ writes ‘P’; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 0 write data to CGRAM or DDRAM RS turns display and cursor on; entire display is blank after initialization R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 entry mode set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 1 0 1 0 0 0 0 38 6 7 | | | write data to CGRAM or DDRAM RS 1 8 0 0 1 1 0 1 0 0 1 1 PHILIPS sets DDRAM address to position the cursor at the head of the 2nd line R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 _ 0 1 1 0 0 0 0 0 0 PHILIPS writes ‘M’ R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M_ 0 1 1 0 0 1 1 0 1 write data to CGRAM or DDRAM RS 1 PHILIPS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCO_ 0 1 1 0 0 1 1 1 1 writes ‘O’ PCF2105 | | | Product specification 10 11 writes ‘S’ 1 write data to CGRAM or DDRAM RS PHILIPS_ R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 set DDRAM address RS 9 OPERATION R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 display control RS 4 DISPLAY Philips Semiconductors Example of 8-bit operation; 2-line display; using internal reset LCD controller/driver 1998 Jul 30 Table 8 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... write data to CGRAM or DDRAM RS PHILIPS 0 0 0 0 0 0 1 1 HILIPS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ICROCOM_ 1 0 1 1 0 0 1 1 0 | | | return home RS PHILIPS returns both display and cursor to the original position R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCOM (address 0) 0 Table 9 0 0 0 0 39 1 2 slave address for write 5 0 1 0 DISPLAY start initialized; no display appears SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W 0 1 1 1 0 1 0 0 during the acknowledge cycle SDA will be pulled-down by the PCF2105 Ack 1 send a control byte for function set Co RS 0 0 OPERATION R/W 0 control byte sets RS and R/W for following data bytes Ack 1 function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 X 0 0 0 0 Ack 1 display control DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 1 1 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 1 0 turns display and cursor on; entire display shows character hexadecimal 20 (blank in ASCII-like character sets) _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted Ack 1 entry mode set DB7 _ Ack 1 Product specification DB7 selects 1-line display; SCL pulse during acknowledge cycle starts execution of instruction PCF2105 6 0 INSTRUCTION I2C-bus 4 0 Example of I2C-bus operation; 1-line display; using internal reset (assuming SA0 = VSS); note 1 STEP 3 writes ‘M’; display is shifted to the left; the first and second lines shift together 1 14 15 sets mode for display shift at the time of write 1 write data to CGRAM or DDRAM RS OPERATION R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MICROCO_ 0 13 DISPLAY Philips Semiconductors 12 INSTRUCTION LCD controller/driver 1998 Jul 30 STEP This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 7 8 slave address for write 9 10 11 DISPLAY start _ SA5 SA4 SA3 SA2 SA1 SA0 R/W 0 1 1 1 0 1 0 0 Ack 1 send a control byte for write data RS 0 1 R/W _ Ack 0 1 write data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 1 0 0 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 0 1 0 0 0 1 40 PHILIPS_ DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 0 1 0 0 1 1 I2C-bus 18 control byte Co RS 1 0 I2C-bus Ack 1 start + slave address for PHILIPS_ PHILIPS_ R/W 0 Ack 1 return home DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 control byte for read RS 0 1 I2C-bus start R/W 1 PHILIPS sets DDRAM address 0 in AC; also returns shifted display to original position; DDRAM contents unchanged; this instruction does not update the DR PHILIPS DDRAM content will be read from following instructions; the R/W has to be set to logic 1 while still in I2C-bus write mode Ack 1 Ack 1 PHILIPS Product specification DB7 Co writes ‘S’ PCF2105 21 writes ‘H’ Ack write data to DDRAM (optional stop) write (as step 8) 20 PH_ | | | | 17 19 writes ‘P’; the DDRAM has been selected at power-up; the cursor is incremented by 1 and shifted to the right 1 write data to DDRAM DB7 P_ Ack 12 to 15 16 for writing data to DDRAM, RS must be set to logic 1; therefore a control byte is needed _ SA6 Co OPERATION Philips Semiconductors INSTRUCTION I2C-bus LCD controller/driver 1998 Jul 30 STEP This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 23 24 25 26 DISPLAY slave address for read SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W 0 1 1 1 0 1 0 1 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X X X DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 1 0 0 0 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 1 0 0 1 I2C-bus stop PHILIPS 8 × SCL; content loaded into interface during previous acknowledge cycle and shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface PHILIPS 8 × SCL; code of letter ‘H’ is read first; during master acknowledge code of letter ‘I’ is loaded into the I2C-bus interface PHILIPS no master acknowledge; after the content of the I2C-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register; DR is not updated; AC is not incremented and cursor is not shifted Ack 1 Ack 0 read data: 8 × SCL + no master acknowledge; note 2 DB7 during the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface and to be shifted out; in the previous instruction neither a ‘set address’ nor a ‘read data’ has been performed; therefore the content of the DR was unknown 1 read data: 8 × SCL + master acknowledge; note 2 DB7 PHILIPS Ack read data: 8 × SCL + master acknowledge; note 2 DB7 OPERATION Ack 1 Philips Semiconductors 22 INSTRUCTION LCD controller/driver 1998 Jul 30 STEP PHILIPS 41 Notes 1. X = don’t care. 2. SDA is left at high-impedance by the microcontroller during the READ acknowledge. Product specification PCF2105 Philips Semiconductors Product specification LCD controller/driver PCF2105 Table 10 Initialization by instruction; 8-bit interface (note 1) STEP DESCRIPTION Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function 0 0 0 1 1 X X X X set (interface is 8-bits long) | Wait 2 ms | RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function 0 0 0 1 1 X X X X set (interface is 8-bits long) | Wait more than 40 µs | RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction; function 0 0 0 1 1 X X X X set (interface is 8-bits long) | | | | RS 0 RS 0 RS 0 RS 0 BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 function set (interface is 8-bits long); specify the 0 0 0 1 1 N M X 0 number of display lines R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 display off 0 0 0 0 0 1 0 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 clear display 0 0 0 0 0 0 0 0 1 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 entry mode set 0 0 0 0 0 0 1 I/D S | Initialization ends Note 1. X = don’t care. 1998 Jul 30 42 Philips Semiconductors Product specification LCD controller/driver PCF2105 Table 11 Initialization by instruction; 4-bit interface; not applicable for I2C-bus operation STEP DESCRIPTION Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS 0 R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits long) 0 0 0 1 1 | Wait 2 ms | RS 0 R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits long) 0 0 0 1 1 | Wait 40 µs | RS 0 R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction; function set (interface is 8-bits long) 0 0 0 1 1 | | | RS 0 RS 0 RS 0 RS 0 0 RS BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) R/W DB7 DB6 DB5 DB4 function set (set interface to 4-bits long); interface is 8-bits long 0 0 0 1 0 R/W DB7 DB6 DB5 DB4 function set (interface is 4-bits long) 0 0 0 1 0 R/W DB7 DB6 DB5 DB4 specify number of display lines and voltage generator characteristic 0 N M 0 0 R/W DB7 DB6 DB5 DB4 display off 0 0 0 0 0 0 1 0 0 0 R/W DB7 DB6 DB5 DB4 clear display 0 0 0 0 0 0 0 0 1 0 0 0 RS R/W DB7 DB6 DB5 DB4 entry mode set 0 0 0 0 0 0 0 0 0 1 I/D S | Initialization ends 1998 Jul 30 43 Philips Semiconductors Product specification LCD controller/driver PCF2105 86 85 84 83 82 81 R15 R16 R25 ≈ 5.63 mm C22 C21 C20 C18 C19 C17 C15 C16 C14 C13 C11 C12 C10 C8 C9 C7 C5 C6 C3 C4 C2 88 89 90 R27 91 R28 92 R2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 87 R26 R1 C1 R9 R10 R11 R13 handbook, full pagewidth R12 R14 18 BONDING PAD LOCATIONS 93 94 R3 95 R4 96 C23 57 C24 56 C25 55 C26 54 C27 53 C28 52 C29 51 C30 50 C31 49 C32 48 C33 SCL 97 47 C34 E RS 98 46 C35 99 45 C36 44 C37 43 C38 42 C39 41 C40 40 C41 39 C42 38 C43 37 C44 36 C45 35 C46 DB1 108 34 C47 DB0 109 33 C48 32 C49 31 C50 30 C51 29 C52 28 C53 R/W 100 x T1 101 0 0 DB7 102 DB6 103 y DB5 104 DB4 105 PCF2105 DB3 106 DB2 107 SDA 110 R31 C54 R32 C55 R5 C56 R7 R6 C57 R8 44 C58 VSS Fig.30 Bonding pad locations. C59 SA0 Chip dimensions: approximately 5.10 × 5.63 mm. Gold bump dimensions: approximately 89 × 89 × 25 µm. C60 VDD ≈ 5.10 mm R17 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 R18 9 R19 8 R20 7 R21 6 R22 5 R23 4 R24 3 R29 2 R30 1 OSC VLCD 111 1998 Jul 30 58 MGK857 Philips Semiconductors Product specification LCD controller/driver PCF2105 Table 12 Bonding pad locations (dimensions in µm). All x/y coordinates are referenced to centre of chip, see Fig.30. SYMBOL PAD x y SYMBOL PAD x y OSC 1 −2184.5 −2637 C42 39 2350 −685 VDD 2 −2024.5 −2637 C41 40 2350 −525 SA0 3 −1864.5 −2637 C40 41 2350 −365 VSS 4 −1704.5 −2637 C39 42 2350 −205 R8 5 −1339 −2637 C38 43 2350 −45 R7 6 −1179 −2637 C37 44 2350 115 R6 7 −1019 −2637 C36 45 2350 275 R5 8 −859 −2637 C35 46 2350 435 R32 9 −699 −2637 C34 47 2350 595 R31 10 −539 −2637 C33 48 2350 755 R30 11 −379 −2637 C32 49 2350 915 R29 12 −219 −2637 C31 50 2350 1075 R24 13 −59 −2637 C30 51 2350 1235 R23 14 101 −2637 C29 52 2350 1395 R22 15 261 −2637 C28 53 2350 1555 R21 16 421 −2637 C27 54 2350 1715 R20 17 581 −2637 C26 55 2350 1875 R19 18 741 −2637 C25 56 2350 2035 R18 19 901 −2637 C24 57 2350 2195 R17 20 1061 −2637 C23 58 2350 2355 C60 21 1221 −2637 C22 59 2185 2637.5 C59 22 1381 −2637 C21 60 2025 2637.5 C58 23 1541 −2637 C20 61 1865 2637.5 C57 24 1701 −2637 C19 62 1705 2637.5 C56 25 1861 −2637 C18 63 1545 2637.5 C55 26 2021 −2637 C17 64 1385 2637.5 C54 27 2181 −2637 C16 65 1225 2637.5 C53 28 2350 −2445 C15 66 1065 2637.5 C52 29 2350 −2285 C14 67 905 2637.5 C51 30 2350 −2125 C13 68 745 2637.5 C50 31 2350 −1965 C12 69 585 2637.5 C49 32 2350 −1805 C11 70 425 2637.5 C48 33 2350 −1645 C10 71 265 2637.5 C47 34 2350 −1485 C9 72 105 2637.5 C46 35 2350 −1325 C8 73 −55 2637.5 C45 36 2350 −1165 C7 74 −215 2637.5 C44 37 2350 −1005 C6 75 −375 2637.5 C43 38 2350 −845 C5 76 −535 2637.5 1998 Jul 30 45 Philips Semiconductors Product specification LCD controller/driver SYMBOL PCF2105 PAD x y C4 77 −695 2637.5 C3 78 −855 2637.5 C2 79 −1015 2637.5 C1 80 −1175 2637.5 R9 81 −1385 2637.5 R10 82 −1545 2637.5 R11 83 −1705 2637.5 R12 84 −1865 2637.5 R13 85 −2025 2637.5 R14 86 −2185 2637.5 R15 87 −2349 2308 R16 88 −2349 2148 R25 89 −2349 1988 R26 90 −2349 1828 R27 91 −2349 1668 R28 92 −2349 1508 R1 93 −2349 1348 R2 94 −2349 1188 R3 95 −2349 1028 R4 96 −2349 868 SCL 97 −2349 632 E 98 −2349 472 RS 99 −2349 312 R/W 100 −2349 142 T1 101 −2349 −34 DB7 102 −2349 −233 DB6 103 −2349 −393 DB5 104 −2349 −668 DB4 105 −2349 −828 DB3 106 −2349 −1103 DB2 107 −2349 −1263 DB1 108 −2349 −1538 DB0 109 −2349 −1698 SDA 110 −2349 −1933 VLCD 111 −2349 −2453 − −2327.5 2427.5 RECPAT ‘C’ − −2027.5 −2512.5 RECPAT ‘C’ − 1982.5 2297.5 RECPAT ‘F’ 1998 Jul 30 46 Philips Semiconductors Product specification LCD controller/driver PCF2105 19 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Jul 30 47 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 415106/1200/02/pp48 Date of release: 1998 Jul 30 Document order number: 9397 750 04198