INTEGRATED CIRCUITS DATA SHEET PCF2113x LCD controllers/drivers Product specification Supersedes data of 1997 Apr 04 File under Integrated Circuits, IC12 2001 Dec 19 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x CONTENTS 1 FEATURES 1.1 Note 2 APPLICATIONS 3 GENERAL DESCRIPTION 9.5 9.6 9.7 9.8 9.9 9.10 9.11 4 ORDERING INFORMATION 10 INTERFACES TO MICROCONTROLLER 5 BLOCK DIAGRAM 6 PINNING 10.1 10.2 Parallel interface I2C-bus interface 7 FUNCTIONAL DESCRIPTION 11 LIMITING VALUES 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 LCD supply voltage generator LCD bias voltage generator Oscillator External clock Power-on reset Power-down mode Registers Busy flag Address Counter (AC) Display Data RAM (DDRAM) Character Generator ROM (CGROM) Character Generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Reset function 12 HANDLING INSTRUCTIONS 13 DC CHARACTERISTICS 14 AC CHARACTERISTICS 15 DEVICE PROTECTION CIRCUITS 16 APPLICATION INFORMATION 16.1 16.2 16.4 16.5 General application information 4-bit operation, 1-line display using internal reset 8-bit operation, 1-line display using internal reset 8-bit operation, 2-line display I2C-bus operation, 1-line display 17 BONDING PAD INFORMATION 18 TRAY INFORMATION 8 INSTRUCTIONS 19 PACKAGE OUTLINE 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 Clear display Return home Entry mode set Display control (and partial Power-down mode) Cursor or display shift Function set Set CGRAM address Set DDRAM address Read busy flag and read address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM 20 SOLDERING 20.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 9 9.1 9.2 9.3 9.4 16.3 20.2 20.3 20.4 20.5 Direct mode Voltage multiplier control Screen configuration Display configuration Temperature control Set VLCD Reducing current consumption 21 DATA SHEET STATUS 22 DEFINITIONS EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES 23 DISCLAIMERS 24 BARE DIE DISCLAIMER New instructions Icon control Bit IM Bit IB 25 PURCHASE OF PHILIPS I2C COMPONENTS 2001 Dec 19 2 Philips Semiconductors Product specification LCD controllers/drivers 1 PCF2113x FEATURES • Single-chip LCD controller/driver • 2-line display of up to 12 characters + 120 icons, or 1-line display of up to 24 characters + 120 icons • 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese) and user defined symbols 1.1 • Icon mode: reduced current consumption while displaying Note Icon mode is used to save current. When only icons are displayed, a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. • Icon blink function • On-chip: – Configurable 4, 3 or 2 voltage multiplier generating LCD supply voltage, independent of VDD, programmable by instruction (external supply also possible) 2 APPLICATIONS • Telecom equipment – Temperature compensation of on-chip generated VLCD: −0.16 to −0.24 %/K (programmable by instruction) • Portable instruments • Point-of-sale terminals. – Generation of intermediate LCD bias voltages – Oscillator requires no external components (external clock also possible). 3 The PCF2113x is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2-line by 12 or 1-line by 24 characters with 5 × 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2113x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter ‘x’ in PCF2113x characterizes the built-in character set. Various character sets can be manufactured on request. • Display data RAM: 80 characters • Character generator ROM: 240, 5 × 8 characters • Character generator RAM: 16, 5 × 8 characters; 3 characters used to drive 120 icons, 6 characters used if icon blink feature is used in application • 4 or 8-bit parallel bus and 2-wire I2C-bus interface • CMOS compatible • 18 row and 60 column outputs • Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for single line operation) and 1 : 2 (for icon only mode) • Uses common 11 code instruction set (extended) • Logic supply voltage range VDD1 − VSS1 = 1.8 to 5.5 V (chip may be driven with two battery cells) • VLCD generator supply voltage range VDD2 − VSS2 = 2.2 to 4.0 V • Display supply voltage range VLCD − VSS2 = 2.2 to 6.5 V • Direct mode to save current consumption for icon mode and Mux 1 : 9 (depending on VDD2 value and LCD liquid properties) • Very low current consumption (20 to 200 µA): – Icon mode: <25 µA – Power-down mode: <2 µA. 2001 Dec 19 GENERAL DESCRIPTION 3 Philips Semiconductors Product specification LCD controllers/drivers 4 PCF2113x ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCF2113AU/10/F4 − chip on flexible film carrier − PCF2113DU/10/F4 − chip on flexible film carrier − PCF2113DU/F4 − chip in tray − PCF2113DH/F4 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 PCF2113DU/2/F4 − chip with bumps in tray − PCF2113EU/2/F4 − chip with bumps in tray − PCF2113WU/2/F4 − chip with bumps in tray − 2001 Dec 19 4 Philips Semiconductors Product specification LCD controllers/drivers 5 PCF2113x BLOCK DIAGRAM handbook, full pagewidth C1 to C60 R1 to R18 18 60 COLUMN DRIVERS BIAS VOLTAGE GENERATOR VLCD1 ROW DRIVERS 60 18 DATA LATCHES VLCDSENSE VLCD GENERATOR VLCD2 SHIFT REGISTER 18-BIT 60 SHIFT REGISTER 5 × 12 BIT 5 OSC OSCILLATOR CURSOR AND DATA CONTROL 5 VDD1 VDD2 CHARACTER GENERATOR RAM (128 × 5) (CGRAM) 16 CHARACTERS VDD3 CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS TIMING GENERATOR VSS1 8 VSS2 DISPLAY DATA RAM (DDRAM) 80 CHARACTERS/BYTES 7 T1 PD T2 7 T3 7 DISPLAY ADDRESS COUNTER ADDRESS COUNTER (AC) 7 7 INSTRUCTION DECODER PCF2113x DATA REGISTER (DR) 8 INSTRUCTION REGISTER(IR) BUSY FLAG 8 POWER-ON RESET 8 I/O BUFFER DB0 to DB3/SA0 DB4 to DB7 E R/W RS SCL SDA Fig.1 Block diagram. 2001 Dec 19 5 MGE990 Philips Semiconductors Product specification LCD controllers/drivers 6 PCF2113x PINNING PIN PCF2113DH PAD(1) PCF2113XU TYPE VDD1 1 1 P supply voltage 1 for all except VLCD generator OSC 2 2 I oscillator/external clock input; note 2 PD 3 3 I power-down select input; for normal operation PD is LOW SYMBOL DESCRIPTION T3 − 4 I test pad; open circuit and not user accessible T1 4 5 I test pin; must be connected to VSS1 T2 − 6 I test pad; must be connected to VSS1 VSS1 5 7 P ground 1 for all except VLCD generator VSS2 6 8 P ground 2 for VLCD generator VLCD2 7 9 O VLCD output if VLCD is generated internally; note 7 VLCDSENSE − 10 I input (VLCD) for voltage multiplier regulation; notes 3 and 7 VLCD1 8 11 I input for generation of LCD bias levels; note 7 9 to 16 12 to 19 O LCD row driver outputs 9 to 16 R9 to R16 R18 17 20 O LCD row driver output 18 C60 to C53 18 to 25 21 to 28 O LCD column driver outputs 60 to 53 dummy pad − 29 − dummy pad − 30 − C52 to C28 26 to 50 31 to 55 O dummy pad − 56 − dummy pad − 57 − C27 to C3 LCD column driver outputs 52 to 28 51 to 75 58 to 82 O dummy pad − 83 − dummy pad − 84 − C2 76 85 O LCD column driver output 2 C1 77 86 O LCD column driver output 1 78 to 85 87 to 94 O LCD row driver outputs 8 to 1 R17 86 95 O LCD row driver output 17 SCL 87 96 I I2C-bus serial clock input; note 4 SDA 88 97 I/O E 89 98 I data bus clock input; note 4 RS 90 99 I register select input R/W 91 100 I read/write input DB7 92 101 I/O 8-bit bidirectional data bus bit 7; note 5 DB6 93 102 I/O 8-bit bidirectional data bus bit 6 DB5 94 103 I/O 8-bit bidirectional data bus bit 5 DB4 95 104 I/O 8-bit bidirectional data bus bit 4 DB3/SA0 96 105 I/O 8-bit bidirectional data bus bit 3 or I2C-bus address pin; notes 4 and 5 DB2 97 106 I/O 8-bit bidirectional data bus bit 2 DB1 98 107 I/O 8-bit bidirectional data bus bit 1 R8 to R1 2001 Dec 19 LCD column driver outputs 27 to 3 I2C-bus serial data input/output; note 4 6 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x PIN PCF2113DH PAD(1) PCF2113XU TYPE DB0 99 108 I/O VDD2 100 109 P supply voltage 2 for VLCD generator; note 6 VDD3 − 110 P supply voltage 3 for VLCD generator; notes 3 and 6 SYMBOL DESCRIPTION 8-bit bidirectional data bus bit 0 Notes 1. Bonding pad location information is given in Chapter 17. 2. When the on-chip oscillator is used this pad must be connected to VDD1. 3. In the LQFP100 version this signal is connected internally and can not be accessed at any pin. 4. When the I2C-bus is used, the parallel interface pin E must be LOW. In the I2C-bus read mode DB7 to DB0 should be connected to VDD1 or left open-circuit. When the parallel bus is used, the pins SCL and SDA must be connected to VSS1 or VDD1; they must not be left open-circuit. When the 4-bit interface is used without reading out from the PCF2113x (R/W is set permanently to logic 0), the unused ports DB0 to DB4 can either be set to VSS1 or VDD1 instead of leaving them open-circuit. 5. DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the four higher order lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I2C-bus operations (see note 4). 6. VDD2 and VDD3 should always be equal. 7. When VLCD is generated internally, pins VLCD1, VLCD2 and VLCDSENSE must be connected together. When external VLCD is supplied, pin VLCD2 should be left open-circuit to avoid any stray current, pins VLCD1 and VLCDSENSE must be connected together. 2001 Dec 19 7 Philips Semiconductors Product specification 76 C2 77 C1 78 R8 79 R7 81 R5 80 R6 82 R4 83 R3 84 R2 85 R1 86 R17 87 SCL 88 SDA 89 E 90 RS 91 R/W 92 DB7 93 DB6 94 DB5 PCF2113x 95 DB4 97 DB2 98 DB1 99 DB0 100 VDD2 handbook, full pagewidth 96 DB3/SA0 LCD controllers/drivers VDD1 1 75 C3 OSC 2 74 C4 PD 3 73 C5 T1 4 72 C6 VSS1 5 71 C7 VSS2 6 70 C8 VLCD2 VLCD1 7 69 C9 8 68 C10 R9 9 67 C11 R10 10 66 C12 R11 11 65 C13 R12 12 64 C14 PCF2113x R13 13 63 C15 R14 14 62 C16 R15 15 61 C17 R16 16 60 C18 R18 17 59 C19 C60 18 58 C20 C59 19 57 C21 C58 20 56 C22 Fig.2 Pin configuration (LQFP100). 2001 Dec 19 8 C28 50 C29 49 C30 48 C31 47 C32 46 C33 45 C34 44 C35 43 C36 42 C37 41 C38 40 C39 39 C40 38 C41 37 C42 36 C43 35 C44 34 C45 33 51 C27 C46 32 C53 25 C47 31 52 C26 C48 30 53 C25 C54 24 C49 29 C55 23 C50 28 54 C24 C51 27 55 C23 C56 22 C52 26 C57 21 MGE989 Philips Semiconductors Product specification LCD controllers/drivers 7 PCF2113x The generated VLCD is independent of VDD and is temperature compensated. When the VLCD generator and the direct mode are switched off, an external voltage may be supplied at connected pins VLCD1 and VLCD2. VLCD1 and VLCD2 may be higher or lower than VDD2. FUNCTIONAL DESCRIPTION 7.1 LCD supply voltage generator The LCD supply voltage may be generated on-chip. The VLCD generator is controlled by two internal 6-bit registers: VA and VB. The nominal LCD operating voltage at room temperature is given by the relationship: During direct mode (program DM register bit) the internal VLCD generator is turned off and the VLCD2 output voltage is directly connected to VDD2. This reduces the current consumption during icon mode and Mux 1 : 9 (depending on VDD2 value and LCD liquid properties). VOP(nom) = (integer value of register × 0.08) + 1.82 7.1.1 PROGRAMMING RANGES Programmed value: 1 to 63. Voltage: 1.90 to 6.86 V. Tref = 27 °C. The VLCD generator ensures that, as long as VDD is in the valid range (2.2 to 4 V), the required peak voltage VOP = 6.5 V can be generated at any time. Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the VLCD tolerance and temperature coefficient must be taken into account. 7.2 LCD bias voltage generator The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the different multiplex rates are shown in Table 1. These bias levels are automatically set to the given values when switching to the corresponding multiplex rate. Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed. Value 0 for VA and VB switches the generator off (i.e. VA = 0 in character mode, VB = 0 in icon mode). Usually register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode. When VLCD is generated on-chip the VLCD pins should be decoupled to VSS with a suitable capacitor. Table 1 Bias levels as a function of multiplex rate; note 1 MULTIPLEX NUMBER RATE OF LEVELS V1 V2 V3 V4 V5 V6 3/ 4 3/ 4 2/ 3 1/ 2 1/ 2 2/ 3 1/ 2 1/ 2 1/ 3 1/ 4 1/ 4 1/ 3 VSS 1 : 18 5 VLCD 1:9 5 VLCD 1:2 4 VLCD Note 1. The values in the table are given relative to VLCD − VSS, e.g. 3/4 means 3/4 × (VLCD − VSS). 2001 Dec 19 9 VSS VSS Philips Semiconductors Product specification LCD controllers/drivers 7.3 PCF2113x The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the ‘read data’ instruction. Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pin must be connected to VDD1. 7.4 External clock 7.8 If an external clock is to be used this input is at the OSC pin. The resulting display frame frequency is given by: f OSC f frame = ------------3 072 The busy flag indicates the internal status of the PCF2113x. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pin DB7 when bit RS = 0 and bit R/W = 1. Instructions should only be written after checking that the busy flag is at logic 0 or waiting for the required number of cycles. Only in the Power-down mode is the clock allowed to be stopped (OSC connected to VSS), otherwise the LCD is frozen in a DC state. 7.5 7.9 Power-on reset Power-down mode The chip can be put into Power-down mode by applying an external active HIGH level to the PD pin. In Power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS). 7.10 Registers The PCF2113x has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select (RS) signal determines which register will be accessed. The instruction register stores instruction codes such as ‘display clear’, ‘cursor shift’, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM).The instruction register can be written to but not read from by the system controller. Table 2 Display Data RAM (DDRAM) The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Fig.3. With no display shift the characters represented by the codes in the first 24 RAM locations starting at address 00H in line 1 are displayed. Figures 4 and 5 show the display mapping for right and left shift respectively. During power-down, information in the RAMs and the chip state are preserved. Instruction execution during power-down is possible when pin OSC is externally clocked. 7.7 Address Counter (AC) The address counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands ‘set CGRAM address’ and ‘set DDRAM address’. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter contents are output to the bus (DB6 to DB0) when bit RS = 0 and bit R/W = 1. The on-chip Power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 3 oscillator cycles to be executed. 7.6 Busy flag When data is written to or read from the DDRAM, wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 2. Address space and wrap-around operation MODE Address space 1 × 24 2 × 12 1 × 12 00 to 4F 00 to 27; 40 to 67 00 to 27 Read/write wrap-around (moves to next line) 4F to 00 27 to 40; 67 to 00 27 to 00 Display shift wrap-around (stays within line) 4F to 00 27 to 00; 67 to 40 27 to 00 2001 Dec 19 10 Philips Semiconductors Product specification LCD controllers/drivers handbook, full pagewidth display position DDRAM address PCF2113x non-displayed DDRAM addresses 1 2 3 4 5 22 23 24 00 01 02 03 04 15 16 17 18 19 4C 4D 4E 4F 1-line display non-displayed DDRAM address DDRAM address 1 2 3 4 5 10 11 12 00 01 02 03 04 09 0A 0B 0C 0D 1 2 3 4 5 10 11 12 40 41 42 43 44 49 4A 4B 4C 4D 24 25 26 27 line 1 64 65 66 67 line 2 MGE991 2-line display Fig.3 DDRAM to display mapping; no shift. handbook,display halfpage position 1 5 22 23 24 DDRAM address 4F 00 01 02 03 2 3 4 14 15 16 1-line display 1 DDRAM address 5 10 11 12 27 00 01 02 03 2 3 08 09 0A 1 5 10 11 12 67 40 41 42 43 48 49 4A 2 3 4 4 line 1 line 2 MGE992 2-line display Fig.4 DDRAM to display mapping; right shift. handbook,display halfpage position DDRAM address 5 22 23 24 01 02 03 04 05 1 2 3 4 16 17 18 1-line display 1 DDRAM address 5 10 11 12 01 02 03 04 05 2 3 0A 0B 0C 1 5 10 11 12 41 42 43 44 45 4A 4B 4C 2 3 4 4 line 1 line 2 MGE993 2-line display Fig.5 DDRAM to display mapping; left shift. 2001 Dec 19 11 Philips Semiconductors Product specification LCD controllers/drivers 7.11 PCF2113x Character Generator ROM (CGROM) 7.14 The CGROM generates 240 character patterns in a 5 × 8 dot format from 8-bit character codes. Figures 7, 8, 9 and 10 show the character sets that are currently implemented. The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 7.15 7.12 Character Generator RAM (CGRAM) LCD row and column drivers The PCF2113x contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. Up to 16 user defined characters may be stored in the CGRAM. Some CGRAM characters (see Fig.16) are also used to drive icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both icon rows are used in the application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.7). Figure 11 shows the addressing principle for the CGRAM. 7.13 Timing generator The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 12, 13, 14 and 15 show typical waveforms. Unused outputs should be left unconnected. Cursor control circuit The cursor control circuit generates the cursor underline and/or cursor blink as shown in Fig.6 at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited. cursor MGA801 5 x 7 dot character font alternating display cursor display example blink display example Fig.6 Cursor and blink display examples. 2001 Dec 19 12 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x handbook, full pagewidth upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 4 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MGE994 Fig.7 Character set ‘A’ in CGROM. 2001 Dec 19 13 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x handbook, full pagewidth upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 4 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MGD688 Fig.8 Character set ‘D’ in CGROM. 2001 Dec 19 14 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x handbook, full pagewidth upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 4 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MGD689 Fig.9 Character set ‘E’ in CGROM. 2001 Dec 19 15 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x handbook, full pagewidth upper 4 bits 0000 xxxx 0000 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 4 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MGU204 Fig.10 Character set ‘W’ in CGROM. 2001 Dec 19 16 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x character codes handbook, full pagewidth CGRAM address (DDRAM data) 7 6 5 4 3 2 higher order bits 0 0 0 0 0 0 1 0 6 lower order bits 0 0 0 0 0 0 0 0 5 4 3 2 higher order bits 0 1 0 0 0 0 0 0 character patterns (CGRAM data) 1 0 4 lower order bits 0 1 3 higher order bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 2 1 character code (CGRAM data) 0 4 3 2 1 0 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 0 lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cursor position 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 1 character pattern example 2 MGE995 Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in this figure. As shown in Figs 7 and 8, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag’ and ‘address counter’ command. Fig.11 Relationship between CGRAM addresses, data and display patterns. 2001 Dec 19 17 Philips Semiconductors Product specification LCD controllers/drivers frame n handbook, full pagewidth ROW 1 PCF2113x frame n + 1 state 1 (ON) state 2 (OFF) VLCD V2 V3/V4 V5 VSS R1 R2 R3 R4 R5 ROW 9 R6 VLCD V2 V3/V4 V5 VSS ROW 2 VLCD V2 V3/V4 V5 VSS COL1 VLCD V2 V3/V4 V5 VSS COL2 VLCD V2 V3/V4 V5 VSS R7 R8 R9 VOP 0.5VOP 0.25VOP state 1 0 V −0.25VOP −0.5VOP −VOP VOP 0.5VOP 0.25VOP state 2 0 V −0.25VOP −0.5VOP −VOP MGE996 1 2 3 18 1 2 3 18 Fig.12 MUX 1 : 18 LCD waveforms; character mode. 2001 Dec 19 18 Philips Semiconductors Product specification LCD controllers/drivers frame n + 1 frame n handbook, full pagewidth ROW 1 PCF2113x state 1 (ON) state 2 (OFF) VLCD V2 V3/V4 V5 VSS R1 R2 R3 R4 R5 ROW 2 R6 VLCD V2 V3/V4 V5 VSS ROW 3 VLCD V2 V3/V4 V5 VSS COL1 VLCD V2 V3/V4 V5 VSS COL2 VLCD V2 V3/V4 V5 VSS R7 R8 R9 VOP 0.5VOP 0.25VOP state 1 0 V −0.25VOP −0.5VOP −VOP VOP 0.5VOP 0.25VOP state 2 0 V −0.25VOP −0.5VOP −VOP 1 2 3 9 1 2 3 9 R10 to R18 to be left open. Fig.13 MUX 1 : 9 LCD waveforms; character mode. 2001 Dec 19 19 MGU217 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x frame n + 1 frame n handbook, full pagewidth only icons are driven (MUX 1 : 2) VLCD ROW 17 2/3 1/3 VSS VLCD ROW 18 2/3 1/3 VSS VLCD ROW 1 to 16 2/3 1/3 VSS VLCD COL 1 ON/OFF 2/3 1/3 VSS VLCD COL 2 OFF/ON 2/3 1/3 VSS VLCD COL 3 ON/ON 2/3 1/3 VSS VLCD COL 4 OFF/OFF 2/3 1/3 VSS MGE997 Fig.14 MUX 1 : 2 LCD waveforms; icon mode. 2001 Dec 19 20 Philips Semiconductors Product specification LCD controllers/drivers handbook, full pagewidth V PIXEL PCF2113x frame n + 1 frame n state 1 (ON) state 1 COL 1 ROW 17 state 2 COL 2 ROW 17 VOP 2/3 VOP 1/3 VOP state 2 (OFF) R17 R18 0 R1-16 −1/3 VOP −2/3 VOP −VOP state 3 (OFF) VOP 2/3 VOP 1/3 VOP 0 −1/3 VOP −2/3 VOP −VOP VOP 2/3 VOP 1/3 VOP state 3 COL 1 0 ROW 1 to 16 −1/3 VOP −2/3 VOP −VOP MGE998 VON(rms) = 0.745VOP VOFF(rms) = 0.333VOP V ON D = ------------= 2.23 V OFF Fig.15 MUX 1 : 2 LCD waveforms; icon mode. 2001 Dec 19 21 Philips Semiconductors Product specification LCD controllers/drivers 7.16 PCF2113x Reset function The PCF2113x automatically initializes (resets) when power is turned on. The chip executes a reset sequence, including a ‘clear display’, requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 3. Table 3 State after reset STEP FUNCTION 1 clear display 2 entry mode set 3 4 display control function set CONTROL BIT STATE CONDITIONS I/D = 1 +1 (increment) S=0 no shift D=0 display off C=0 cursor off B=0 cursor character blink off DL = 1 8-bit interface M=0 1-line display H=0 normal instruction set SL = 0 MUX 1 : 18 mode 5 default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 17 and 18 6 icon control 7 display/screen configuration L = 0; P = 0; Q = 0 default configurations 8 VLCD temperature coefficient TC1 = 0; TC2 = 0 default temperature coefficient 9 set VLCD VA = 0; VB = 0 VLCD generator off 10 I2C-bus 11 Set HVgen stages S1 = 1; S0 = 0 VLCD generator voltage multiplier set at factor 4 2001 Dec 19 IM = 0; IB = 0; DM = 0 icons, icon blink and direct mode disabled interface reset 22 Philips Semiconductors Product specification LCD controllers/drivers 8 PCF2113x INSTRUCTIONS In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. Only two PCF2113x registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers, to allow interfacing to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs. During internal operation, no instructions other than the ‘read busy flag’ and ‘read address’ instructions will be executed. Because the busy flag is set to a logic 1 while an instruction is being executed, check to ensure it is a logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 5. An instruction sent while the busy flag is logic 1 will not be executed. The instruction set for I2C-bus commands is given in Table 4. The PCF2113x operation is controlled by the instructions shown in Table 5 together with their execution time. Details are explained in subsequent sections. Instructions are of 4 types, those that: 1. Designate PCF2113x functions such as display format, data length, etcetera. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. Table 4 Instruction set for I2C-bus commands CONTROL BYTE Co RS 0 0 0 0 COMMAND BYTE 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1 Note 1. R/W is set together with the slave address. 2001 Dec 19 I2C-BUS COMMANDS 23 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTION REQUIRE CLOCK CYCLES H = 0 or 1 NOP 0 0 0 0 0 0 0 0 0 0 no operation 3 Function set 0 0 0 0 1 DL 0 M SL H sets interface Data Length (DL), number of display lines (M), single line/MUX 1 : 9 (SL) and extended instruction set control (H) 3 Read busy flag and address counter 0 1 BF reads the Busy Flag (BF) indicating internal operating is being performed and reads Address counter (AC) contents 0 AC Read data 1 1 read data reads data from CGRAM or DDRAM 3 Write data 1 0 write data writes data from CGRAM or DDRAM 3 Clear display 0 0 0 0 0 0 0 0 0 1 clears entire display and sets DDRAM address 0 in address counter 165 Return home 0 0 0 0 0 0 0 0 1 0 sets DDRAM address 0 in address counter; also returns shifted display to original position; DDRAM contents remain unchanged 3 Entry mode set 0 0 0 0 0 0 0 1 I/D S sets cursor move direction (I/D) and specifies shift of display (S); these operations are performed during data write and read 3 Display control 0 0 0 0 0 0 1 D C B sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B); D = 0 (display off) puts chip into the Power-down mode 3 Cursor/display shift 0 0 0 0 0 1 S/C R/L 0 0 moves cursor or shifts display (S/C) to right or left (R/L) without changing DDRAM contents 3 Set CGRAM address 0 0 0 1 sets CGRAM address; bit DB6 is to be set by the command ‘set DDRAM address’; look at the description of the commands 3 Set DDRAM address 0 0 1 sets DDRAM address 3 Philips Semiconductors Instruction set with parallel bus commands LCD controllers/drivers 2001 Dec 19 Table 5 H=0 24 ACG Product specification PCF2113x ADD This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTION REQUIRE CLOCK CYCLES H=1 Reserved 0 0 0 0 0 0 0 0 0 1 do not use − Screen configuration 0 0 0 0 0 0 0 0 1 L set screen configuration (L) 3 Display configuration 0 0 0 0 0 0 0 1 P Q set display configuration, columns (P) and rows (Q) 3 Icon control 0 0 0 0 0 0 1 IM IB Temperature control 0 0 0 0 0 1 0 0 Set HVgen stages 0 0 0 1 0 0 0 0 Set VLCD 0 0 1 V voltage DM set Icon Mode (IM), Icon Blink (IB), Direct Mode (DM) TC1 TC2 set Temperature Coefficient (TCx) S1 S0 3 Philips Semiconductors RS LCD controllers/drivers 2001 Dec 19 INSTRUCTION 3 set internal VLCD generator voltage multiplier stages (S1 = 1 and S0 = 1 not allowed) 3 store VLCD in register VA or VB (V) 3 25 Product specification PCF2113x Philips Semiconductors Product specification LCD controllers/drivers Table 6 PCF2113x Explanations of symbols used in Tables 4 and 5. BIT LOGIC STATE 0 LOGIC STATE 1 Co last control byte; see Table 4 another control byte follows after data/command DL 4 bits 8 bits M (no impact, 1-line by 24 display if SL = 1) 2-line by 12 display SL MUX 1 : 18 (1 × 24 or 2 × 12 character display) MUX 1 : 9 (1 × 12 character display) H use basic instruction set use extended instruction set I/D decrement increment S display freeze display shift D display off display on C cursor off cursor on B cursor character blink off; character at cursor position does not blink cursor character blink on; character at cursor position blinks S/C cursor move display shift R/L left shift right shift L (no impact, if M = 1 or SL = 1) left/right screen: standard connection left/right screen; mirrored connection 1st 12 characters of 24; columns are from 1 to 60 1st 12 characters of 24; columns are from 1 to 60 P column data: left to right; column data is displayed column data; right to left; column data is displayed from 1 to 60 from 60 to 1 Q row data; top to bottom; row data is displayed from row data; bottom to top; row data is displayed 1 to 16 and icon row data is in 17 and 18 from 16 to 1 and icon row data is in 18 and 17 IM character mode; full display icon mode; only icons displayed IB icon blink disabled icon blink enabled DM direct mode disabled direct mode enabled V set VA set VB 8.1 2nd 12 characters of 24; columns are from 1 to 60 2nd 12 characters of 24; columns are from 60 to 1 Clear display 8.2 ‘Clear display’ writes character code 20H into all DDRAM addresses (the character pattern for character code 20H must be a blank pattern), sets the DDRAM address counter to logic 0 and returns the display to its original position, if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display. Sets entry mode I/D = 1 (increment mode). S of entry mode does not change. ‘Return home’ sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change. The instruction ‘clear display’ requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications. 2001 Dec 19 Return home 26 Philips Semiconductors Product specification LCD controllers/drivers 8.3 8.3.1 PCF2113x Entry mode set 8.4.3 BIT I/D The character indicated by the cursor blinks when B = 1. The cursor character blink is displayed by switching between display characters and all dots on with a period of f OSC approximately 1 second, with f blink = ---------------52 224 When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. 8.3.2 The cursor underline and the cursor character blink can be set to display simultaneously. 8.5 BIT S 8.4.1 Display control (and partial Power-down mode) The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the ‘cursor display shift’. BIT D The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D = 1. 8.6 8.6.1 When the display is off (D = 0) the chip is in partial Power-down mode: • The LCD generator and bias generator are turned off. Three oscillator cycles are required after sending the ‘display off’ instruction to ensure all outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running during partial Power-down mode (‘display off’) the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (OSC = VSS). BIT DL (PARALLEL MODE ONLY) ‘Function set’ from the I2C-bus interface sets the DL bit to logic 1. To ensure IDD < 1 µA, the parallel bus pins DB7 to DB0 should be connected to VDD; pins RS and R/W to VDD or left open-circuit and pin PD to VDD. Recovery from Power-down mode: PD back to VSS, if necessary pin OSC back to VDD and send a ‘display control’ instruction with D = 1. 8.6.2 BIT M Selects either 1-line by 24 display (M = 0) or 2-line by 12 display (M = 1). 8.6.3 BIT C BIT SL Selects MUX 1 : 9, 1-line by 12 display (independent of M and L). Only rows 1 to 8 and 17 are to be used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2-line by 12 display mode, however, the second line cannot be displayed. The cursor is displayed when C = 1 and inhibited when C = 0. Even if the cursor disappears, the display functions I/D, etcetera, remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.6). 2001 Dec 19 Function set Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left open-circuit (internal pull-ups). Hence in the first ‘function set’ instruction after power-on M, SL and H are set to logic 1. A second ‘function set’ must then be sent (2 nibbles) to set M, SL and H to their required values. • The LCD outputs are connected to VSS 8.4.2 Cursor or display shift ‘Cursor/display shift’ moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus it appears as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = 0, the display does not shift. 8.4 BIT B 27 Philips Semiconductors Product specification LCD controllers/drivers 8.6.4 PCF2113x 8.10 BIT H ‘Write data’ writes binary 8-bit data DB7 to DB0 to the CGRAM or the DDRAM. When H = 0 the chip can be programmed via the standard 11 instruction codes used in the PCF2116 and other LCD controllers. Whether the CGRAM or DDRAM is to be written into is determined by the previous ‘set CGRAM address’ or ‘set DDRAM address’ command. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits DB4 to DB0 of CGRAM data are valid, bits DB7 to DB5 are ‘don’t care’. When H = 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons. 8.7 Write data to CGRAM or DDRAM Set CGRAM address ‘Set CGRAM address’ sets bits DB5 to 0 of the CGRAM address ACG into the address counter (binary A5 to A0). Data can then be written to or read from the CGRAM. 8.11 Read data from CGRAM or DDRAM ‘Read data’ reads binary 8-bit data DB7 to DB0 from the CGRAM or DDRAM. Attention: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (binary A6 to A0). With the ‘set CGRAM address’ command, only bits DB5 to DB0 are set. Bit DB6 can be set using the ‘set DDRAM address’ command first, or by using the auto-increment feature during CGRAM write. All bits DB6 to DB0 can be read using the ‘read busy flag’ and ‘read address’ command. The most recent ‘set address’ command determines whether the CGRAM or DDRAM is to be read. The ‘read data’ instruction gates the content of the Data Register (DR) to the bus while pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. When writing to the lower part of the CGRAM, ensure that bit DB6 of the address is not set (e.g. by an earlier DDRAM write or read action). There are only three instructions that update the data register: 8.8 • ‘Set DDRAM address’ • ‘Set CGRAM address’ Set DDRAM address • ‘Read data’ from CGRAM or DDRAM. ‘Set DDRAM address’ sets the DDRAM address ADD into the address counter (binary A6 to A0). Data can then be written to or read from the DDRAM. 8.9 Other instructions (e.g. ‘write data’, ‘cursor/display shift’, ‘clear display’ and ‘return home’) do not modify the data register content. Read busy flag and read address ‘Read busy flag and address counter’ read the Busy Flag (BF) and Address Counter (AC). BF = 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0. It is recommended that the BF status is checked before the next write operation is executed. 9 9.1 New instructions H = 1 sets the chip into alternate instruction set mode. 9.2 At the same time, the value of the address counter expressed in binary A6 to A0 is read out. The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction. 2001 Dec 19 EXTENDED FUNCTION SET INSTRUCTIONS AND FEATURES Icon control The PCF2113x can drive up to 120 icons. See Fig.16 for CGRAM to icon mapping. 28 Philips Semiconductors Product specification LCD controllers/drivers handbook, full pagewidth display: PCF2113x COL 1 to 5 COL 6 to 10 COL 56 to 60 ROW 17 – 1 2 3 4 5 6 7 8 9 10 ROW 18 – 61 62 63 64 65 66 67 68 69 70 56 57 58 59 60 116 117 118 119 120 MGE999 block of 5 columns icon no. handbook, full pagewidth phase ROW/COL character codes 7 6 5 4 3 2 CGRAM address 1 MSB 0 6 LSB MSB 5 4 3 2 1 CGRAM data 0 4 3 2 1 LSB MSB icon view 0 LSB 1-5 even 17/1-5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 6-10 even 17/6-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 11-15 even 17/11-15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 56-60 even 17/56-60 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 61-65 even 18/1-5 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 116-120 even 18/56-60 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1 1-5 odd (blink) 17/1-5 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 116-120 odd (blink) 18/56-60 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 MGG001 CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled. Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled). Fig.16 CGRAM to icon mapping. 2001 Dec 19 29 Philips Semiconductors Product specification LCD controllers/drivers 9.3 PCF2113x When DM = 1, the chip is in direct mode. The internal VLCD generator is turned off and the VLCD2 output is directly connected to the VLCD generator supply voltage VDD2. Bit IM When IM = 0, the chip is in character mode. In the character mode characters and icons are driven (MUX 1 : 18). The VLCD generator, if used, produces the VLCD voltage programmed in register VA. The direct mode can be used to reduce the current consumption when the required VLCD2 output voltage is close to the VDD2 supply voltage. This can be the case in icon mode or in Mux 1:9 (depending on LCD liquid properties). When IM = 1, the chip is in icon mode. In the icon mode only the icons are driven (MUX 1 : 2) and the VLCD generator, if used, produces the VLCD voltage as programmed in register VB. Table 7 Normal/icon mode operation IM MODE Voltage multiplier control Bits S1 and S0 A software configurable voltage multiplier is incorporated in the VLCD generator and can be set via the ‘Set HVgen stages’ command. VLCD 0 character mode generates VA 1 icon mode generates VB 9.4 9.6 The voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages, depending on the required VLCD output voltage (see Table 8). Bit IB Icon blink control is independent of the cursor/character blink function. Table 8 When IB = 0, the icon blink is disabled. Icon data is stored in CGRAM character 0 to 2 (3 × 8 × 5 = 120 bits for 120 icons). S1 and S0 control of voltage multiplier S1 S0 DESCRIPTION 0 0 When IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). set VLCD generator stages to 1 (2 x voltage multiplier) 0 1 set VLCD generator stages to 2 (3 x voltage multiplier) 1 0 Icon states for the even phase are stored in CGRAM characters 0 to 2 (3 × 8 × 5 = 120 bits for 120 icons). These bits also define icon state when icon blink is not used (see Table 9). set VLCD generator stages to 3 (4 x voltage multiplier) 1 1 do not use 9.7 Icon states for the odd phase are stored in CGRAM character 4 to 6 (another 120 bits for the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters. 9.5 Bit L L = 0: the two halves of a split screen are connected in a standard way i.e. column 1/61, 2/62 to 60/120; default. L = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120, 2/119 to 60/61. This allows single layer PCB or glass layout. Direct mode When DM = 0, the chip is not in the direct mode. Either the internal VLCD generator or an external voltage may be used to achieve VLCD. Table 9 Screen configuration Blink effect for icons and cursor character blink PARAMETER EVEN PHASE ODD PHASE Cursor character blink block (all on) normal (display character) Icons state 1; CGRAM character 0 to 2 state 2; CGRAM character 4 to 6 2001 Dec 19 30 Philips Semiconductors Product specification LCD controllers/drivers 9.8 PCF2113x VLCD programming: Display configuration Bit P 1. Send ‘function set’ instruction with H = 1 P = 0: default. 2. Send ‘set VLCD’ instruction to write to voltage register: a) DB7, DB6 = 10: DB5 to DB0 are VLCD of character mode (VA) P = 1: mirrors the column data. Bit Q b) DB7, DB6 = 11: DB5 to DB0 are VLCD of icon mode (VB) Q = 0: default. Q = 1: mirrors the row data. c) DB5 to DB0 = 000000 switches VLCD generator off (when selected) 9.9 d) During ‘display off’ and power-down the VLCD generator is also disabled. Temperature control Default is TC1 = 0 and TC2 = 0. Selects the default temperature coefficient for the internally generated VLCD (see Table 10). 3. Send ‘function set’ instruction with H = 0 to resume normal programming. The ranges for TC are given in Chapter 13. 9.11 Table 10 TC1 and TC2 selection of VLCD temperature coefficient Reducing current consumption can be achieved by one of the options given in Table 11. TC1 TC2 0 0 VLCD temperature coefficient 0 0 VLCD temperature coefficient 1 0 1 VLCD temperature coefficient 2 1 1 VLCD temperature coefficient 3 9.10 When VLCD lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip generator than an external regulator. DESCRIPTION 1 Table 11 Reducing current consumption ORIGINAL MODE Set VLCD The VLCD value is programmed by instruction. Two on-chip registers, VA and VB hold VLCD values for the character mode and the icon mode respectively. The generated VLCD value is independent of VDD, allowing battery operation of the chip. 2001 Dec 19 Reducing current consumption 31 ALTERNATIVE MODE Character mode Icon mode (control bit IM) Display on Display off (control bit D) VLCD generator operating Direct mode Any mode power-down (PD pin) Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 10 INTERFACES TO MICROCONTROLLER 10.2 10.1 The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy. Parallel interface The PCF2113x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS and R/W are required (see Chapter 6). I2C-bus interface Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for the transaction. The higher order bits (corresponding to DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction, see Figs 17 to 19 for examples of bus protocol. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). In 4-bit mode, pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally. RS R/W E DB7 IR7 IR3 BF AC3 DR7 DR3 DB6 IR6 IR2 AC6 AC2 DR6 DR2 DB5 IR5 IR1 AC5 AC1 DR5 DR1 DB4 IR4 IR0 AC4 AC0 DR4 DR0 instruction write busy flag and address counter read Fig.17 4-bit transfer example. 2001 Dec 19 32 data register read MGA804 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x RS R/W E internal internal operation DB7 IR7 IR3 busy instruction write not busy AC3 busy flag check AC3 D7 busy flag check D3 instruction write MGA805 IR7, IR3: instruction 7th, 3rd bit. AC3: address counter 3rd bit. D7, D3: data 7th, 3rd bit. Fig.18 An example of 4-bit data transfer timing sequence. RS R/W E internal DB7 internal operation data busy instruction write busy flag check busy busy flag check not busy busy flag check Fig.19 Example of busy flag checking timing sequence. 2001 Dec 19 33 data instruction write MGA806 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 10.2.2 A master receiver must signal an end of data to the transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 10.2.1 DEFINITIONS • Transmitter: the device which sends the data to the bus • Receiver: the device which receives the data from the bus • Master: the device which initiates a transfer generates clock signals and terminates a transfer I2C-BUS PROTOCOL • Slave: the device addressed by a master Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the START procedure. The I2C-bus configuration for the different PCF2113x read and write cycles is shown in Figs 24 to 26. The slow down feature of the I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the PCF2113x. MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER • Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message • Arbitration: procedure to ensure that if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted • Synchronization: procedure to synchronize the clock signals of two or more devices. SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL MGA807 Fig.20 System configuration. handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed Fig.21 Bit transfer. 2001 Dec 19 34 MBC621 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig.22 Definition of START and STOP conditions. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.23 Acknowledgement on the I2C-bus. 2001 Dec 19 35 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors LCD controllers/drivers handbook, full pagewidth 2001 Dec 19 acknowledgement from PCF2113x S S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A DATA BYTE A 0 RS CONTROL BYTE A DATA BYTE A P 0 slave address R/W Co 2n ≥ 0 bytes 1 byte Co n ≥ 0 bytes update data pointer 36 MGG002 S 0 1 1 1 0 1 A 0 0 PCF2113x slave address R/W Product specification PCF2113x Fig.24 Master transmits to slave receiver; write mode. This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... S S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A DATA BYTE A 0 RS CONTROL BYTE A DATA BYTE(1) Philips Semiconductors LCD controllers/drivers handbook, full pagewidth 2001 Dec 19 acknowledgement A 0 slave address 2n R/W 0 bytes n ≥ 0 bytes 1 byte Co Co 37 acknowledgement S SLAVE ADDRESS S A 1 A 0 acknowledgement DATA BYTE A n bytes R/W Co no acknowledgement DATA BYTE 1 P last byte update data pointer update data pointer MGG003 Product specification Fig.25 Master reads after setting word address; writes word address, set RS; ‘read data’. PCF2113x Last data byte is a dummy byte (may be omitted). Philips Semiconductors Product specification LCD controllers/drivers PCF2113x acknowledgement from PCF2113x handbook, full pagewidth S SLAVE ADDRESS S A 1 A 0 acknowledgement from master DATA BYTE A no acknowledgement from master n bytes R/W Co 1 P DATA BYTE last byte update data pointer update data pointer MGG004 Fig.26 Master reads slave immediately after first byte; read mode (RS previously defined). 11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD1 logic supply voltage −0.5 +5.5 V VDD2, VDD3 VLCD generator supply voltages −0.5 +4 V VLCD LCD supply voltage −0.5 +6.5 V Vi/o(n) voltage on any VDD related input or output −0.5 VDD + 0.5 V any VLCD related input or output −0.5 VLCD + 0.5 V II DC input current −10 +10 mA IO DC output current −10 +10 mA IDD, ISS and ILCD VDD, VSS or VLCD supply current −50 +50 mA Ptot total power dissipation − 400 mW PO power dissipation per output − 100 mW Ves electrostatic handling voltage human body model; C = 100 pF; R = 1.5 kΩ − 2000 V electrostatic handling voltage machine model; C = 200 pF; L = 0.75 µH − 150 V −65 +150 °C Tstg storage temperature 12 HANDLING INSTRUCTIONS Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”). 2001 Dec 19 38 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 13 DC CHARACTERISTICS VDD1 = 1.8 to 5.5 V; VDD2 = VDD3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD1 logic supply voltage VDD2, VDD3 VLCD generator supply voltages VLCD LCD supply voltage VPOR Power-on reset voltage note 1 1.8 − 5.5 V internal VLCD generation (VDD2 and VDD3 < VLCD) 2.2 − 4.0 V 2.2 − 6.5 V 0.9 − 1.6 V − 70 120 µA note 1 and 2 GROUND SUPPLY CURRENT; EXTERNAL VLCD; note 3 ISS1 ground supply current 1 ISS3 ground supply current 3 VDD = 3 V; VLCD = 5 V; note 4 − 45 80 µA ISS4 ground supply current 4 icon mode; VDD = 3 V; VLCD = 2.5 V; note 4 − 25 45 µA ISS5 ground supply current 5 − Power-down mode; VDD = 3 V; VLCD = 2.5 V; DB7 to DB0, RS and R/W = 1; OSC = 0; PD = 1 2 5 µA − 190 400 µA GROUND SUPPLY CURRENT; INTERNAL VLCD; notes 3 and 5 ISS6 ground supply current 6 ISS8 ground supply current 8 VDD = 3 V; VLCD = 5 V; note 4 − 160 400 µA ISS9 ground supply current 9 icon mode; VDD = 2.5 V; VLCD = 2.5 V; note 4 − 120 − µA Logic VIL LOW-level input voltage VSS1 − 0.3VDD1 V VIH HIGH-level input voltage 0.7VDD1 − VDD1 V VIL(OSC) LOW-level input voltage on pin OSC VSS1 − VDD1 − 1.2 V VIH(OSC) HIGH-level voltage pin OSC VDD1 − 0.1 − VDD1 V IOL(DB) LOW-level output current on pins DB7 to DB0 VOL = 0.4 V; VDD1 = 5 V 1.6 4 − mA IOH(DB) HIGH-level output current on pins DB7 to DB0 VOH = 4 V; VDD1 = 5 V −1 −8 − mA Ipu pull-up current at pins DB7 to DB0 VI = VSS1 0.04 0.15 1 µA IL leakage current VI = VDD1 or VSS1 −1 − +1 µA 2001 Dec 19 39 Philips Semiconductors Product specification LCD controllers/drivers SYMBOL PCF2113x PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I2C-bus; pins SDA and SCL VIL LOW-level input voltage 0 − 0.3VDD1 V VIH HIGH-level input voltage 0.7VDD1 − 5.5 V ILI input leakage current VI = VDD1 or VSS1 −1 − +1 µA Ci input capacitance note 6 − 5 − pF IOL (SDA) LOW-level output current on pin SDA VOL = 0.4 V; VDD1 > 2 V 3 − − mA VOL = 0.2 VDD1; VDD1 < 2 V 2 − − mA LCD outputs RO(ROW) row output resistance of pins R1 to R18 note 7 − 10 30 kΩ RO(COL) column output resistance of pins C1 to C60 note 7 − 15 40 kΩ Vbias(tol) bias voltage tolerance on pins R1 to R18 and C1 to C60 note 8 − 20 130 mV VLCD2(tol) VLCD voltage tolerance Tamb = 25 °C; note 5 VLCD < 3 V − − 160 mV VLCD < 4 V − − 200 mV VLCD < 5 V − − 260 mV VLCD < 6 V − − 340 mV TC0 VLCD temperature coefficient 0 − −0.16 − %/K TC1 VLCD temperature coefficient 1 − −0.18 − %/K TC2 VLCD temperature coefficient 2 − −0.21 − %/K TC3 VLCD temperature coefficient 3 − −0.24 − %/K Notes 1. Spikes on VDD1 or VSS1 which cause VDD1 − VSS1 ≤ 1.6 V can cause a Power-on reset. 2. Resets all logic when VDD1 < VPOR; 3 OSC cycles required. 3. LCD outputs are open-circuit; inputs at VDD1 or VSS1; bus inactive. 4. Tamb = 25 °C; fOSC = 200 kHz. 5. LCD outputs are open-circuit; VLCD generator is on; load current IVLCD = 5 µA (at VLCD). 6. Tested on sample basis. 7. Resistance of output pins (R1 to R18 and C1 to C60) with a load current of 10 µA; outputs measured one at a time; external VLCD = 3 V, VDD1, 2, 3 = 3 V. 8. LCD outputs open-circuit; external VLCD. 2001 Dec 19 40 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 14 AC CHARACTERISTICS VDD1 = 1.8 to 5.5 V; VDD2 = VDD3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS VDD = 5.0 V MIN. TYP. MAX. UNIT fFR LCD frame frequency (internal clock) 45 95 147 Hz fosc oscillator frequency (not available at any pin) 140 250 450 kHz fOSC(ext) external clock frequency 140 − 450 kHz tosc(st) oscillator start-up time after power-down − 200 300 µs tW(PD) power-down HIGH-level pulse width 1 − − µs tSW(PD) tolerable spike width on PD pin − − 90 ns note 1 note 1 Timing characteristics of parallel interface; note 2 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2113X); see Fig.27 Tcy(en) enable cycle time 500 − − ns tW(en) enable pulse width 220 − − ns tsu(A) address set-up time 50 − − ns th(A) address hold time 25 − − ns tsu(D) data set-up time 60 − − ns th(D) data hold time 25 − − ns READ OPERATION (READING DATA FROM PCF2113X TO MICROCONTROLLER); see Fig.28 Tcy(en) enable cycle time 500 − − ns tW(en) enable pulse width 220 − − ns tsu(A) address set-up time 50 − − ns th(A) address hold time 25 − − ns td(D) data delay time VDD1 > 2.2 V − − 150 ns VDD1 > 1.5 V − − 250 ns th(D) data hold time 5 − 100 ns Timing characteristics of I2C-bus interface; see Fig.29; note 2 fSCL SCL clock frequency − − 400 kHz tLOW SCL clock LOW period 1.3 − − µs tHIGH SCL clock HIGH period 0.6 − − µs tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 0 − − ns tr SCL and SDA rise time note 1 and 3 15 + 0.1 Cb − 300 ns tf SCL and SDA fall time note 1 and 3 15 + 0.1 Cb − 300 ns Cb capacitive bus line load − − 400 pF tSU;STA set-up time for a repeated START condition 0.6 − − µs tHD;STA START condition hold time 0.6 − − µs 2001 Dec 19 41 Philips Semiconductors Product specification LCD controllers/drivers SYMBOL PCF2113x PARAMETER CONDITIONS MIN. TYP. tSU;STO set-up time for STOP condition 0.6 − tSW tolerable spike width on bus − tBUF bus free time between STOP and START condition 1.3 MAX. UNIT − µs − 50 ns − − µs Notes 1. Tested on sample base. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 3. Cb = total capacitance of one bus line in pF. handbook, full pagewidth RS VIH1 V IL1 VIH1 VIL1 t su(A) R/W t h(A) V IL1 VIL1 t h(A) tW(en) E VIH1 VIH1 VIL1 VIL1 VIL1 t h(D) t su(D) VIH1 valid data VIL1 DB0 to DB7 Tcy(en) VIH1 VIL1 MBK474 Fig.27 Parallel bus write operation sequence; writing data from microcontroller to PCF2113x. 2001 Dec 19 42 Philips Semiconductors Product specification LCD controllers/drivers handbook, full pagewidth PCF2113x VIH1 V IL1 RS VIH1 VIL1 tsu(A) t h(A) VIH1 VIH1 R/W tW(en) VIL1 E VIH1 t h(A) VIH1 VIL1 t h(D) t d(D) VOH1 VOL1 DB0 to DB7 VIL1 VOH1 VOL1 MBK475 Tcy(en) Fig.28 Parallel bus read operation sequence; writing data from PCF2113x to microcontroller. handbook, full pagewidth SDA t BUF tf t LOW SCL t HD;STA t HD;DAT tr t HIGH t SU;DAT SDA MGA728 t SU;STA Fig.29 I2C-bus timing diagram. 2001 Dec 19 43 t SU;STO Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 15 DEVICE PROTECTION CIRCUITS SYMBOL VDD1 PAD INTERNAL CIRCUIT 1 VDD1 VSS1 MGU200 VDD2 109 VDD2 VSS1 VSS2 MGU201 VDD3 110 VDD3 VSS1 MGU202 VSS1 7 VSS2 8 8 7 VSS2 VSS1 MGU203 VLCDSENSE 10 VLCD1 11 VLCD2 9 VSS1 MGU196 SCL 96 SDA 97 VDD1 VSS1 MGU198 2001 Dec 19 44 Philips Semiconductors Product specification LCD controllers/drivers SYMBOL PCF2113x PAD OSC 2 PD 3 T1 5 T2 6 INTERNAL CIRCUIT VDD1 T3 4 E 98 VSS1 RS 99 MGU199 R/W 100 DB0 to DB7 108 to 101 R1 to R8 94 to 87 R9 to R16 12 to 19 R17 95 R18 20 VLCD2 C1 to C2 86 to 85 C3 to 27 82 to 58 VSS1 C28 to C52 55 to 31 MGU197 C53 to C60 28 to 21 2001 Dec 19 45 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 16 APPLICATION INFORMATION handbook, full pagewidth P80CL51 P10 RS P11 R/W P12 E P17 to P14 2 R1 to R16 2 × 12 CHARACTER LCD DISPLAY PLUS 120 ICONS PCF2113x 16 C1 to C60 DB7 to DB4 4 R17, R18 60 MGG006 Fig.30 Direct connection to 8-bit microcontroller; 4-bit bus. handbook, full pagewidth P80CL51 P20 RS P21 R/W P22 E P17 to P10 2 R1 to R16 2 × 12 CHARACTER LCD DISPLAY PLUS 120 ICONS PCF2113x 16 C1 to C60 DB7 to DB0 8 R17, R18 60 MGG005 Fig.31 Direct connection to 8-bit microcontroller; 8-bit bus. handbook, full pagewidth OSC VDD R17, R18 2 R1 to R16 2 × 12 CHARACTER LCD DISPLAY PLUS 120 ICONS VDD PCF2113x 100 nF VSS 16 VLCD 100 nF C1 to C60 60 VSS 8 DB7 to DB0 E MGG007 RS R/W Fig.32 Typical application using parallel interface. 2001 Dec 19 46 Philips Semiconductors Product specification LCD controllers/drivers handbook, full pagewidth PCF2113x VDD VDD VDD OSC VDD DB3/SAO R17, R18 2 R1 to R16 2 × 12 CHARACTER LCD DISPLAY PLUS 120 ICONS VDD PCF2113x 100 nF 16 VLCD 100 nF VSS VSS C1 to C60 60 R17, R18 2 R1 to R16 1 × 24 CHARACTER LCD DISPLAY PLUS 120 ICONS SCL SDA VSS OSC VDD DB3/SAO VDD PCF2113x 470 nF 100 nF VSS SCL SDA 16 VLCD C1 to C60 VSS 60 SCL SDA MASTER TRANSMITTER PCF84C81A; P80CL410 MGG008 Fig.33 Application using I2C-bus interface. 16.1 Optimized values for these tracks are below 50 Ω for the supply and below 100 Ω for the I/O connections. Higher track resistance reduce performance and increase current consumption. General application information The required minimum value for the external capacitors in an application with the PCF2113x are: CExt for VLCD/VSS = 100 nF min., for VDD/VSS = 470 nF. Higher capacitor values are recommended for ripple reduction. To avoid accidental triggering of Power-on reset (especially in COG applications), the supplies must be adequately decoupled. Depending on power supply quality, VDD1 may have to be risen above the specified minimum. For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections. 2001 Dec 19 47 Philips Semiconductors Product specification LCD controllers/drivers 16.2 PCF2113x 4-bit operation, 1-line display using internal reset 16.4 For a 2-line display the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 15). It should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. The program must set functions prior to a 4-bit operation (see Table 12). When power is turned on, 8-bit operation is automatically selected and the PCF2113x attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 12 step 3). Thus, DB4 to DB7 of the ‘function set’ are written twice. 16.3 8-bit operation, 2-line display 16.5 I2C-bus operation, 1-line display A control byte is required with most commands (see Table 16). 8-bit operation, 1-line display using internal reset Tables 13 and 14 show an example of a 1-line display in 8-bit operation. The PCF2113x functions must be set by the ‘function set’ instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and the DDRAM contents remain unchanged, display data entered first can be displayed when the ‘return home’ operation is performed. Table 12 4-bit operation, 1-line display example using internal reset STEP INSTRUCTION 1 power supply on (PCF2113x is initialized by the internal reset) 2 function set 3 4 5 6 DISPLAY RS R/W DB7 DB6 DB5 DB4 0 0 0 0 1 0 OPERATION initialized; no display appears sets to 4-bit operation; in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write function set 0 0 0 0 1 0 0 0 0 0 0 0 sets to 4-bit operation, selects 1-line display and VLCD = V0; 4-bit operation starts from this point and resetting is needed display control 0 0 0 0 0 0 0 0 1 1 1 0 _ turns on display and cursor; entire display is blank after initialization _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM; display is not shifted P_ writes ‘P’; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right entry mode set 0 0 0 0 0 0 0 0 0 1 1 0 ‘write data’ to CGRAM/DDRAM 1 0 0 1 0 1 1 0 0 0 0 0 2001 Dec 19 48 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... INSTRUCTION DISPLAY 1 power supply on (PCF2113x is initialized by the internal reset) 2 function set 3 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 49 1 0 0 0 0 0 0 0 0 0 1 1 1 0 _ turns on display and cursor; entire display is blank after initialization 0 0 0 0 0 0 1 1 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted 0 0 0 0 P_ writes ‘P’; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right 1 0 0 0 PH_ ‘write data’ to CGRAM/DDRAM 1 6 1 entry mode set 0 5 sets to 8-bit operation, selects 1-line display and VLCD = V0 0 display control 0 4 initialized; no display appears 0 0 OPERATION Philips Semiconductors STEP LCD controllers/drivers 2001 Dec 19 Table 13 8-bit operation, 1-line display example; using internal reset (character set ‘A’) 0 0 1 0 1 ‘write data’ to CGRAM/DDRAM 1 0 0 1 0 7 to 10 0 writes ‘H’ | writes ‘ILIP’ | 11 ‘write data’ to CGRAM/DDRAM 1 12 1 0 1 0 0 1 1 PHILIPS_ writes ‘S’ 0 0 0 0 0 0 1 1 1 PHILIPS_ sets mode for display shift at the time of write 0 0 0 0 HILIPS _ writes space 1 1 0 1 ILIPS writes ‘M’ ‘write data’ to CGRAM/DDRAM 1 0 0 0 1 0 ‘write data’ to CGRAM/DDRAM 0 0 1 0 15 to 19 0 M_ | writes ‘ICROK’ | 20 ‘write data’ to CGRAM/DDRAM 1 0 0 1 0 0 1 1 1 1 MICROKO_ writes ‘O’ PCF2113x 1 Product specification 14 0 entry mode set 0 13 0 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 0 0 0 0 MICROKO shifts only the cursor position to the left 0 0 0 0 1 0 0 0 0 MICROKO shifts only the cursor position to the left 0 0 1 0 0 0 0 1 1 ICROCO writes ‘C’ correction; the display moves to the left 0 0 0 0 1 1 1 0 0 MICROCO shifts the display and cursor to the right 0 0 0 0 1 0 1 0 0 MICROCO_ shifts only the cursor to the right ‘write data’ to CGRAM/DDRAM 1 27 0 cursor/display shift 0 26 0 cursor/display shift 0 25 0 ‘write data’ to CGRAM/DDRAM 1 24 0 cursor/display shift 0 23 OPERATION cursor/display shift 0 22 DISPLAY Philips Semiconductors 21 INSTRUCTION LCD controllers/drivers 2001 Dec 19 STEP 0 0 1 0 0 1 1 0 1 ICROCOM_ writes ‘M’ 0 0 0 0 0 0 1 0 PHILIPS M returns both display and cursor to the original position (address 0) return home 0 0 50 Product specification PCF2113x This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... INSTRUCTION DISPLAY 1 power supply on (PCF2113x is initialized by the internal reset) 2 function set 3 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 0 0 0 0 sets to 8-bit operation, selects 1-line display and VLCD = V0 0 0 51 0 0 0 1 1 1 0 _ turns on display and cursor; entire display is blank after initialization 0 0 0 0 0 0 1 1 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted 0 0 0 0 0 0 _ sets the CGRAM address to position of character 0; the CGRAM is selected 0 1 0 1 0 _ writes data to CGRAM for icon even phase; icons appears 1 0 0 0 0 _ sets the CGRAM address to position of character 4; the CGRAM is selected 0 1 0 1 0 _ writes data to CGRAM for icon odd phase set CGRAM address 0 6 1 entry mode set 0 5 0 display mode on/off control 0 4 initialized; no display appears 0 0 OPERATION Philips Semiconductors STEP LCD controllers/drivers 2001 Dec 19 Table 14 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’) 0 0 1 ‘write data’ to CGRAM/DDRAM 1 0 0 0 0 7 | | 8 set CGRAM address 0 9 0 0 1 1 ‘write data’ to CGRAM/DDRAM 1 0 0 0 0 10 | | function set 12 0 0 1 1 0 0 0 1 _ sets H = 1 0 0 0 0 1 0 1 0 _ icons blink 0 0 1 1 0 0 0 1 _ sets H = 0 icon control 0 13 0 0 function set 0 0 PCF2113x 0 Product specification 11 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 0 1 0 0 0 0 0 0 0 sets the DDRAM address to the first position; DDRAM is selected 0 0 0 0 P_ writes ‘P’; the cursor is incremented by 1 and shifted to the right 1 0 0 0 PH_ writes ‘H’ ‘write data’ to CGRAM/DDRAM 1 16 OPERATION set DDRAM address 0 15 DISPLAY 0 0 1 0 1 ‘write data’ to CGRAM/DDRAM 1 0 0 1 0 17 to 21 0 | writes ‘ILIPS’ | 22 Philips Semiconductors 14 INSTRUCTION LCD controllers/drivers 2001 Dec 19 STEP return home 0 0 0 0 0 0 0 0 1 0 PHILIPS returns both display and cursor to the original position (address 0) 52 Product specification PCF2113x This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... INSTRUCTION DISPLAY 1 power supply on (PCF2113x is initialized by the internal reset) 2 function set 3 RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 sets to 8-bit operation; selects 2-line display and VLCD generator off 1 0 1 0 0 0 0 0 0 0 1 1 1 0 _ turns on display and cursor; entire display is blank after initialization 0 0 0 0 0 0 1 1 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM; display is not shifted 0 0 0 0 P_ writes ‘P’; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right ‘write data’ to CGRAM/DDRAM 1 53 1 entry mode set 0 5 0 display on/off control 0 4 initialized; no display appears 0 0 OPERATION Philips Semiconductors STEP LCD controllers/drivers 2001 Dec 19 Table 15 8-bit operation, 2-line display example; using internal reset 0 0 1 0 6 to 10 1 | writes ‘HILIP’ | 11 ‘write data’ to CGRAM/DDRAM 12 set DDRAM address 1 0 13 0 0 0 1 1 1 0 1 0 0 1 1 PHILIPS_ writes ‘S’ 0 0 0 0 0 0 PHILIPS _ sets DDRAM address to position the cursor at the head of the 2nd line 1 1 0 1 PHILIPS M_ writes ‘M’ ‘write data’ to CGRAM/ DDRAM 1 0 0 1 0 14 to 18 0 | writes ‘ICROC’ ‘write data’ to CGRAM/DDRAM 1 0 0 1 0 0 1 1 1 1 PHILIPS MICROCO_ writes ‘O’ Product specification 19 PCF2113x | This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 0 0 0 0 0 0 1 1 1 PHILIPS MICROCO_ sets mode for display shift at the time of write ‘write data’ to CGRAM/DDRAM 1 23 OPERATION ‘write data’ to CGRAM/DDRAM 0 21 DISPLAY 0 0 1 0 0 1 1 0 1 HILIPS ICROCOM_ writes ‘M’; display is shifted to the left; the first and second lines shift together 0 0 0 0 0 0 1 0 PHILIPS MICROCOM returns both display and cursor to the original position (address 0) return home 0 0 Philips Semiconductors 20 INSTRUCTION LCD controllers/drivers 2001 Dec 19 STEP 54 Product specification PCF2113x This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 I2C-bus 2 slave address for write DISPLAY start initialized; no display appears SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 3 4 1 1 1 0 1 0 0 1 during the acknowledge cycle SDA will be pulled-down by the PCF2113x control byte sets RS for following data bytes send a control byte for ‘function set’ Co RS 0 0 0 0 0 0 Ack 0 0 0 0 0 0 0 0 1 function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 5 0 1 X 0 0 0 0 display on/off control 0 0 0 0 1 1 1 0 55 0 0 0 7 I2C-bus start 8 slave address for write 0 1 1 0 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted _ for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed 1 SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 0 1 _ send a control byte for ‘write data’ Co RS 0 0 0 0 0 0 Ack 0 1 0 0 0 0 0 0 1 _ ‘write data’ to DDRAM 1 0 1 0 0 0 0 writes ‘P’; the DDRAM has been selected at power-up; the cursor is incremented by 1 and shifted to the right PH_ writes ‘H’ 1 ‘write data’ to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 1 Product specification 0 P_ PCF2113x DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 11 turns on display and cursor; entire display shows character 20H (blank in ASCII-like character sets) entry mode set 0 10 _ 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 9 selects 1-line display and VLCD = V0; SCL pulse during acknowledge cycle starts execution of instruction 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 6 OPERATION Philips Semiconductors I2C-BUS BYTE STEP LCD controllers/drivers 2001 Dec 19 Table 16 Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1) This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 12 to 15 | DISPLAY OPERATION | 16 ‘write data’ to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 1 1 17 (optional I2C-bus stop) I2C-bus start start + slave address for write (as step 8) 18 control byte 19 PHILIPS_ RS 0 0 0 0 0 0 Ack 1 0 0 0 0 0 0 0 1 0 0 0 56 20 I2C-bus start 21 slave address for read 0 0 1 0 1 1 PHILIPS 1 sets DDRAM address 0 in address counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the Data Register (DR) PHILIPS SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 0 1 0 1 PHILIPS during the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface to be shifted out; in the previous instruction neither a ‘set address’ nor a ‘read data’ has been performed; therefore the content of the DR was unknown; the R/W has to be set to 1 while still in I2C-write mode PHILIPS DDRAM content will be read from following instructions PHILIPS 8 × SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface PHILIPS 8 × SCL; code of letter ‘H’ is read first; during master acknowledge code of ‘I’ is loaded into the I2C-bus interface 1 control byte for read Co RS 0 0 0 0 0 0 Ack 0 1 1 0 0 0 0 0 1 ‘read data’: 8 × SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X X X X X 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 0 Product specification ‘read data’: 8 × SCL + master acknowledge; note 2 PCF2113x 24 PHILIPS_ return home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 23 writes ‘S’ 1 Co 0 22 PHILIPS_ Philips Semiconductors I2C-BUS BYTE LCD controllers/drivers 2001 Dec 19 STEP This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 25 ‘read data’: 8 × SCL + no master acknowledge; note 2 DISPLAY DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 26 1 I2C-bus stop 0 0 1 0 0 1 PHILIPS 1 OPERATION no master acknowledge; after the content of the I2C-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register, data register is not updated, address counter is not incremented and cursor is not shifted PHILIPS Notes 1. X = don’t care. 2. SDA is left at high-impedance by the microcontroller during the read acknowledge. Philips Semiconductors I2C-BUS BYTE LCD controllers/drivers 2001 Dec 19 STEP 57 Product specification PCF2113x This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... DESCRIPTION power-on or unknown state | wait 2 ms after internal reset has been applied | RS R/W DB7 DB6 DB5 0 0 0 0 1 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 1 X X X X function set (interface is 8 bits long) | wait 2 ms | RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 0 0 0 0 1 1 X X X X function set (interface is 8 bits long) DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 1 X X X X Philips Semiconductors STEP LCD controllers/drivers 2001 Dec 19 Table 17 Initialization by instruction, 8-bit interface (note 1) | wait more than 40 µs | 58 RS R/W DB7 DB6 DB5 0 0 0 0 1 | | RS R/W DB7 DB6 DB5 function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) DB4 DB3 DB2 DB1 DB0 function set (interface is 8 bits long); specify the number of display lines 0 0 0 0 1 1 0 M 0 H 0 0 0 0 0 0 1 0 0 0 display off 0 0 0 0 0 0 0 0 0 1 clear display 0 0 0 0 0 0 0 1 I/D S entry mode set | Initialization ends Product specification 1. X = don’t care. PCF2113x Note This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... DESCRIPTION power-on or unknown state | Wait 2 ms after internal reset has been applied | RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 0 0 0 0 1 1 function set (interface is 8 bits long) | Wait 2 ms | RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 0 0 0 0 1 1 function set (interface is 8 bits long) Philips Semiconductors STEP LCD controllers/drivers 2001 Dec 19 Table 18 Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation | Wait 40 µs | 59 RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 0 0 0 0 1 1 function set (interface is 8 bits long) | BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) RS R/W DB7 DB6 DB5 DB4 function set (set interface to 4 bits long) 0 0 0 0 1 0 interface is 8 bits long 0 0 0 1 0 function set (interface is 4 bits long) 0 0 0 M 0 H specify number of display lines 0 0 0 0 0 0 0 0 1 0 0 0 display off 0 0 0 0 0 0 clear display 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 I/D S | Initialization ends entry mode set PCF2113x 0 Product specification 0 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 17 BONDING PAD INFORMATION SYMBOL VDD1 OSC PD T3 T1 T2 VSS1 VSS2 VLCD2 VLCDSENSE VLCD1 R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59 C58 C57 C56 C55 C54 C53 dummy pad 1 dummy pad 2 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 2001 Dec 19 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 SYMBOL COORDINATES(1) X Y −1345 −1155 −1 055 −845 −765 −665 −525 −455 −295 −145 +15 +175 +245 +315 +385 +455 +525 +595 +665 +735 +805 +875 +995 +1065 +1135 +1205 +1275 +1345 +1435 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1550 −1395 −1255 −1155 −1055 −955 −735 −635 −535 −435 −335 −235 −135 −35 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 dummy pad 3 dummy pad 4 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 dummy pad 5 dummy pad 6 C2 60 PAD 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 COORDINATES(1) X Y +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1630 +1435 +1335 +1225 +1115 +1005 +765 +665 +565 +465 +365 +265 +165 +65 −35 −135 −235 −335 −435 −535 −635 −735 −835 −965 −1065 −1165 −1265 −1465 −1630 −1630 +65 +165 +265 +365 +465 +565 +665 +765 +865 +965 +1065 +1165 +1265 +1335 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1550 +1355 +1255 Philips Semiconductors Product specification LCD controllers/drivers SYMBOL C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 SCL SDA E RS R/W 2001 Dec 19 PAD 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PCF2113x COORDINATES(1) X Y −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 +1185 +1115 +1045 +975 +905 +835 +765 +695 +625 +555 +375 +305 +85 −15 −115 SYMBOL PAD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VDD2 VDD3 dummy pad 7 dummy pad 8 101 102 103 104 105 106 107 108 109 110 111 112 COORDINATES(1) X Y −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1630 −1465 −215 −315 −415 −515 −615 −715 −815 −915 −1015 −1235 −1395 −1550 Note 1. All x and y coordinates are referenced to centre of chip and dimensions are in µm (see Fig.34). 61 Philips Semiconductors Product specification C20 C21 C22 C23 C24 C25 C26 C27 dummy pad 4 63 62 61 60 59 58 57 C14 71 64 C13 72 C19 C12 73 65 C11 74 C18 C10 75 66 C9 76 C17 C8 77 67 C7 78 C16 C6 79 68 C5 80 C15 C4 81 69 C3 82 70 dummy pad 5 handbook, full pagewidth PCF2113x 83 LCD controllers/drivers y 56 dummy pad 3 55 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 dummy pad 6 C2 C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 84 SCL SDA 96 97 E 98 RS 99 RW 100 DB7 101 40 DB6 102 39 DB5 103 38 DB4 104 37 DB3 105 36 DB2 106 35 DB1 107 DB0 VDD2 109 VDD3 110 31 C49 C50 C51 C52 dummy pad 7 111 30 dummy pad 2 85 86 87 88 89 90 91 92 93 94 95 54 53 52 51 50 49 PC2113x 48 47 46 45 44 3.36 mm x 0 43 42 0 41 108 34 33 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VLCDSENSE VLCD1 R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59 C58 C57 C56 C55 C54 C53 dummy pad 1 29 9 VLCD2 8 7 6 T2 VSS1 VSS2 5 4 T3 T1 3 2 1 VDD1 OSC PD 112 dummy pad 8 32 3.52 mm MGU205 Fig.34 Bonding pad locations. 2001 Dec 19 62 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 18 TRAY INFORMATION x handbook, full pagewidth A C y D B F E MGU206 For dimensions see Table 19. Fig.35 Tray details. Table 19 Tray dimensions DIMENSION handbook, halfpage DESCRIPTION VALUE A pocket pitch x direction 6.35 mm B pocket pitch y direction 5.59 mm C pocket width x direction 3.82 mm D pocket width y direction 3.66 mm E tray width x direction 50.8 mm F tray width y direction 50.8 mm x pockets in x direction 7 y pockets in y direction 8 PC2113x Table 20 Bump size PARAMETER MGU207 Type Bump width Bump length Bump height Height difference in one die Convex deformation Pad size, aluminium Passivation opening CBB Wafer thickness The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. Fig.36 Tray alignment. 2001 Dec 19 63 VALUE galvanic pure Au 50 ±6 90 ±6 17.5 ±5 <2 <5 62 × 100 36 × 76 380 ±25 UNIT − µm µm µm µm µm µm µm µm Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 19 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X A 51 75 50 76 ZE e E HE A A2 (A 3) A1 w M θ bp Lp L pin 1 index 100 detail X 26 1 25 ZD e v M A w M bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 14.1 13.9 0.5 HD HE 16.25 16.25 15.75 15.75 L Lp v w y 1.0 0.75 0.45 0.2 0.08 0.08 Z D (1) Z E (1) θ 1.15 0.85 7 0o 1.15 0.85 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT407-1 136E20 MS-026 2001 Dec 19 EIAJ EUROPEAN PROJECTION ISSUE DATE 00-01-19 00-02-01 64 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x If wave soldering is used the following conditions must be observed for optimal results: 20 SOLDERING 20.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 20.2 – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. 20.3 20.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2001 Dec 19 Manual soldering 65 Philips Semiconductors Product specification LCD controllers/drivers 20.5 PCF2113x Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2001 Dec 19 66 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 21 DATA SHEET STATUS PRODUCT STATUS DATA SHEET STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 22 DEFINITIONS 23 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 24 BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 2001 Dec 19 67 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x 25 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2001 Dec 19 68 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x NOTES 2001 Dec 19 69 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x NOTES 2001 Dec 19 70 Philips Semiconductors Product specification LCD controllers/drivers PCF2113x NOTES 2001 Dec 19 71 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA73 © Koninklijke Philips Electronics N.V. 2001 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403502/03/pp72 Date of release: 2001 Dec 19 Document order number: 9397 750 06995