Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9575-100A BUK9675-100A GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope available in TO220AB and SOT404 . Using ’trench’ technology which features very low on-state resistance. It is intended for use in automotive and general purpose switching applications. QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V VGS = 10 V MAX. UNIT 100 23 99 175 V A W ˚C 75 55 mΩ mΩ PINNING TO220AB & SOT404 PIN PIN CONFIGURATION SYMBOL DESCRIPTION 1 gate 2 drain 3 source d tab mb g 2 1 tab/mb drain 3 SOT404 BUK9675-100A 1 2 3 TO220AB BUK9575-100A s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 100 100 15 23 16 91 98 175 V V V A A A W ˚C TYP. MAX. UNIT - 1.5 K/W in free air 60 - K/W Minimum footprint, FR4 board 50 - K/W THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient(TO220AB) Thermal resistance junction to ambient(SOT404) - Rth j-a Rth j-a October 2000 1 Rev 1.200 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9575-100A BUK9675-100A STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA; VGS(TO) MIN. TYP. MAX. UNIT VGS = 10 V; ID = 10 A VGS = 4.5 V; ID = 10 A 100 89 1 0.5 - 1.5 0.05 2 60 55 61 2.0 2.3 10 500 100 75 188 72 84 V V V V V µA µA nA mΩ mΩ mΩ mΩ MIN. TYP. MAX. UNIT Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 100 V; VGS = 0 V; IGSS RDS(ON) Gate source leakage current Drain-source on-state resistance VGS = ±10 V; VDS = 0 V VGS = 5 V; ID = 10 A Tj = 175˚C Tj = 175˚C DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1278 129 88 1704 155 120 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; Rload =1.2Ω; VGS = 5 V; RG = 10 Ω - 13 120 58 57 20 168 87 86 ns ns ns ns Ld Internal drain inductance - 4.5 - nH Ld Internal drain inductance - 3.5 - nH Ld Internal drain inductance - 2.5 - nH Ls Internal source inductance Measured from drain lead 6 mm from package to centre of die Measured from contact screw on tab to centre of die(TO220AB) Measured from upper edge of drain tab to centre of die(SOT404) Measured from source lead to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT - - 23 A IF = 10 A; VGS = 0 V IF = 23 A; VGS = 0 V - 0.85 1.1 92 1.2 - A V V IF = 23 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 63 0.22 - ns µC REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IDR IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge October 2000 CONDITIONS 2 Rev 1.200 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9575-100A BUK9675-100A AVALANCHE LIMITING VALUE SYMBOL 1 DSS W 120 PARAMETER CONDITIONS Drain-source non-repetitive unclamped inductive turn-off energy ID = 14.2 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C Normalised Power Derating PD% MIN. TYP. MAX. UNIT - - 100 mJ 100 RDS(ON)=VDS/ID 110 tp = 1us ID/A 100 90 80 10us 70 60 10 100us 50 40 DC 30 1ms 20 10 10ms 0 0 20 40 60 80 100 Tmb / C 120 140 160 1 180 10 100 1000 VDS/V Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 1 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% Zth/(K/W) 10 110 100 90 80 1 70 60 50 0.1 40 0.5 0.2 0.1 0.05 0.02 30 0 0.01 1E-07 20 10 1E-05 1E-03 1E-01 1E+01 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 t/s Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 1 For maximum permissible repetitive avalanche current see fig.18. October 2000 3 Rev 1.200 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9575-100A BUK9675-100A VGS/V = ID/A 5.0 10.0 75 4.0 3.8 3.6 3.4 50 40 3.2 30 3.0 RDS(ON) Ohm 60 70 65 60 2.8 20 2.6 10 55 2.4 2.2 50 0 0 2 4 6 8 3 10 4 5 6 7 VGS/V VDS/V RDS(ON)/mOhm Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 140 8 9 10 Fig.8. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS); conditions: ID = 25 A; 25 4.0 4.2 130 ID/A 20 120 110 4.4 100 15 4.6 4.8 5.0 90 10 80 Tj/C= 175 70 25 5 60 50 0 40 10 15 20 25 ID/A 30 35 0.0 40 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS); conditions: ID = 25 A; 1.0 2.0 VGS/V 3.0 4.0 Fig.9. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 40 75 RDS(ON) Ohm gfs/S 70 30 65 20 60 10 55 0 50 3 4 5 6 7 VGS/V 8 9 0 10 20 30 40 50 60 ID/A Fig.7. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS); conditions: ID = 25 A; October 2000 10 Fig.10. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V 4 Rev 1.200 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET Rds(on) normalised to 25degC a 3 BUK9575-100A BUK9675-100A 3.0 2.5 Capacitance / nF 2.5 2 1.5 Ciss 1.0 Coss Crss 0.0 0.01 -100 -50 0 50 100 Tmb / degC 150 0.1 1 VDS/V 200 Fig.11. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V 2.5 1.5 0.5 1 0.5 2.0 10 100 Fig.14. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz VGS(TO) / V 5 VGS / V max. 4 2 VDS = 14V VDS = 44V typ. 3 1.5 min. 2 1 1 0.5 0 0 -100 -50 0 50 Tj / C 100 150 0 200 10 15 20 25 QG / nC Fig.12. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.15. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 25 A; parameter VDS Sub-Threshold Conduction 1E-01 5 40 IF/A 30 1E-02 2% 1E-03 typ 25 Tj/C= 150 98% 20 1E-04 10 1E-05 0 1E-05 0.0 0 0.5 1 1.5 2 2.5 3 Fig.13. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS October 2000 0.2 0.4 0.6 0.8 VSDS/V 1.0 1.2 1.4 Fig.16. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 5 Rev 1.200 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 120 BUK9575-100A BUK9675-100A WDSS% 100 110 25ºC IAV 100 90 80 25ºC 10 70 60 50 Tj prior to avanche 150ºC 40 30 Tj prior to avalanche 150ºC 20 1 0.001 10 0.01 0.1 1 10 Avalanche Time, tAV (ms) 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.19. Maximum permissible repetitive avalanche current(IAV) versus avalanche time(tAV) for unclamped inductive loads. Fig.17. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A + VDD + L RD VDS VDS - VGS T.U.T. 0 RGS RG T.U.T. R 01 shunt Fig.18. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) October 2000 - VGS -ID/100 0 VDD Fig.20. Switching test circuit. 6 Rev 1.200 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9575-100A BUK9675-100A MECHANICAL DATA Dimensions in mm 4,5 max Net Mass: 2 g 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 0,9 max (3x) 2,54 2,54 0,6 2,4 Fig.21. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". October 2000 7 Rev 1.200 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9575-100A BUK9675-100A MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 OUTLINE VERSION D max. D1 E 11 1.60 1.20 10.30 9.70 e Lp HD Q 2.54 2.90 2.10 15.40 14.80 2.60 2.20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 SOT404 Fig.22. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". October 2000 8 Rev 1.200 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9575-100A BUK9675-100A MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.23. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2000 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 2000 9 Rev 1.200