Philips Semiconductors Product specification TrenchMOS transistor Logic level FET FEATURES PHP60N06LT, PHB60N06LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance QUICK REFERENCE DATA VDSS = 55 V d ID = 58 A RDS(ON) ≤ 20 mΩ (VGS = 5 V) g s RDS(ON) ≤ 18 mΩ (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP60N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB60N06LT is supplied in the SOT404 surface mounting package. PINNING SOT78 (TO220AB) PIN SOT404 DESCRIPTION tab tab 1 gate 2 drain1 3 source tab 2 drain 1 1 23 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature - 55 55 55 ± 13 58 40 232 150 175 V V V A A A W ˚C Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C 1 It is not possible to make connection to pin 2 of the SOT404 package. January 1998 1 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP60N06LT, PHB60N06LT THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint TYP. MAX. UNIT - 1.0 K/W 60 50 - K/W K/W MIN. MAX. UNIT - 2 kV ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS VC Human body model (100 pF, 1.5 kΩ) Electrostatic discharge capacitor voltage, all pins ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 0.25 mA; V(BR)GSS VGS(TO) Drain-source breakdown voltage Gate-source breakdown voltage Gate threshold voltage MIN. Tj = -55˚C IG = ±1 mA; VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A TYP. MAX. UNIT 55 50 10 - - V V V 1.0 0.5 20 - 1.5 15 16 52 0.02 0.05 - 2.0 2.3 20 18 42 1 20 10 500 V V V mΩ mΩ mΩ S µA µA µA µA RDS(ON) Drain-source on-state resistance gfs IGSS Forward transconductance VDS = 25 V; ID = 25 A Gate source leakage current VGS = ±5 V; VDS = 0 V IDSS Zero gate voltage drain current VDS = 55 V; VGS = 0 V; Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 50 A; VDD = 44 V; VGS = 5 V - 37 10 17 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 25 A; VGS = 5 V; RG = 10 Ω Resistive load - 28 110 95 70 40 160 135 90 ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1800 350 170 2400 420 235 pF pF pF Tj = 175˚C Tj = 175˚C January 1998 Tj = 175˚C 2 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP60N06LT, PHB60N06LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM MIN. TYP. MAX. UNIT - - 58 A - - 232 A IF = 25 A; VGS = 0 V IF = 40 A; VGS = 0 V - 0.95 1.0 1.2 - V V IF = 40 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 47 0.15 - ns µC AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS Drain-source non-repetitive ID = 45 A; VDD ≤ 25 V; VGS = 5 V; unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C energy WDSS 120 Normalised Power Derating PD% 120 110 110 100 100 90 90 80 80 70 70 60 60 50 50 40 40 30 30 20 20 10 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 MAX. UNIT - 110 mJ Normalised Current Derating ID% 0 180 0 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) January 1998 MIN. 20 40 60 80 100 Tmb / C 120 140 160 180 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 3 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP60N06LT, PHB60N06LT 1000 RDS(ON)/mOhm 24 23 ID/A RDS(ON) =VDS/ID 100 4 22 tp = 1 us 21 10us 20 VGS/V = 4.2 4.4 4.6 4.8 5 19 100 us 18 DC 10 17 1 ms 16 10ms 100ms 15 14 1 1 10 13 100 VDS/V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp 10 0 10 20 30 40 ID/A 50 60 70 80 90 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS Zth/(K/W) 100 ID/A 80 1 0.5 60 0.2 0.1 0.1 0.05 PD 0.02 0.01 tp D= 40 t T 0 tp T 20 Tj/C = 0.001 1E-06 0.0001 0.01 t/s 1 0 100 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 100 2 3 VGS/V 4 5 6 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj VGS/V = gfs/S 4.2 4.4 80 1 50 10 5 ID/A 0 25 175 40 4.0 3.8 60 30 3.6 3.4 40 3.2 20 2.8 20 3.0 0 0 2 4 VDS/V 6 8 10 2.6 2.4 2.2 10 2.0 0 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS January 1998 0 20 40 ID/A 60 80 100 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V 4 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK959-60 a 2.5 PHP60N06LT, PHB60N06LT 4 Rds(on) normlised to 25degC 3.5 3 Thousands pF 2 1.5 2.5 2 Ciss 1.5 1 1 .5 0.5 -100 -50 0 50 Tmb / degC 100 150 0 0.01 200 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V 2.5 1 VDS/V 10 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 6 BUK959-60 VGS(TO) / V 0.1 Coss Crss 100 VGS/V max. 5 VDS = 14V 2 VDS = 44V 4 typ. 1.5 3 min. 1 2 0.5 1 0 -100 -50 0 50 Tj / C 100 150 0 200 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 10 20 30 QG/nC 40 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS 100 Sub-Threshold Conduction 1E-01 0 IF/A 80 1E-02 2% 1E-03 typ 60 98% Tj/C = 175 25 40 1E-04 20 1E-05 0 1E-05 0 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS January 1998 0 0.2 0.4 0.6 0.8 VSDS/V 1 1.2 1.4 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 5 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 120 PHP60N06LT, PHB60N06LT WDSS% VDD + 110 100 L 90 80 VDS - 70 VGS 60 -ID/100 50 T.U.T. 0 40 30 20 RGS 10 R 01 shunt 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 45 A January 1998 6 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP60N06LT, PHB60N06LT MECHANICAL DATA Dimensions in mm 4,5 max Net Mass: 2 g 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 0,9 max (3x) 2,54 2,54 0,6 2,4 Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". January 1998 7 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP60N06LT, PHB60N06LT MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.18. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.19. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". January 1998 8 Rev 1.300 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET PHP60N06LT, PHB60N06LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1998 9 Rev 1.300