PHILIPS PHN110

DISCRETE SEMICONDUCTORS
DATA SHEET
PHN110
N-channel enhancement mode
MOS transistor
Product specification
Supersedes data of 1996 Jul 16
File under Discrete Semiconductors, SC13b
1997 Jun 17
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
FEATURES
DESCRIPTION
• High-speed switching
N-channel enhancement mode MOS transistor in an 8-pin
plastic SOT96-1 (SO8) package.
• No secondary breakdown
• Very low on-resistance.
APPLICATIONS
d d d d
handbook, halfpage
• Motor and actuator driver
• Power management
8
5
1
4
• Synchronized rectification.
PINNING - SOT96-1 (SO8)
PIN
SYMBOL
1
n.c
2
s
source
3
s
source
4
g
gate
5
d
drain
6
d
drain
7
d
drain
8
d
drain
MAM116
DESCRIPTION
n.c. s
s
g
not connected
Fig.1 Simplified outline and symbol.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
−
MAX.
VDS
drain-source voltage (DC)
VSD
source-drain diode forward voltage
VGS
gate-source voltage (DC)
VGSth
gate-source threshold voltage
ID = 1 mA; VDS = VGS
ID
drain current (DC)
Ts = 80 °C
−
4
A
RDSon
drain-source on-state resistance
ID = 2.2 A; VGS = 10 V
−
0.1
Ω
Ptot
total power dissipation
Ts = 80 °C
−
2.8
W
1997 Jun 17
IS = 1.25 A
2
30
UNIT
V
−
1.2
V
−
±20
V
1
2.8
V
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
drain-source voltage (DC)
−
30
V
VGS
gate-source voltage (DC)
−
±20
V
ID
drain current (DC)
Ts = 80 °C; note 1
−
4
A
IDM
peak drain current
note 2
−
16
A
Ptot
total power dissipation
Ts = 80 °C
−
2.8
W
Tamb = 25 °C; note 3
−
2.4
W
Tamb = 25 °C; note 4
−
1.1
W
Tstg
storage temperature
−65
+150
°C
Tj
operating junction temperature
−65
+150
°C
Source-drain diode
IS
source current (DC)
Ts = 80 °C
−
3.5
A
ISM
peak pulsed source current
note 2
−
14
A
Notes
1. Ts is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Value based on a printed-circuit board with a Rth a-tp (ambient to tie-point) of 27.5 K/W.
4. Value based on a printed-circuit board with a Rth a-tp (ambient to tie-point) of 90 K/W.
MBG848
MBG750
102
handbook, halfpage
6
handbook, halfpage
ID
(A)
Ptot
(W)
10
tp =
10 µs
(1)
4
100 µs
1 ms
1
10−1
0
50
100
150
Ts (oC)
10−2
10−1
200
DC
T
1
10
δ = 0.01; TS = 80 °C.
(1) RDSon limitation.
Fig.2 Power derating curve.
1997 Jun 17
Fig.3 SOAR.
3
100 ms
t
tp
0
10 ms
tp
δ= T
P
2
VDS (V)
102
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
THERMAL CHARACTERISTICS
SYMBOL
Rth j-s
PARAMETER
VALUE
UNIT
25
K/W
thermal resistance from junction to soldering point
MBG749
102
handbook, full pagewidth
Rth j−s
(K/W)
10
δ=
0.75
0.5
0.33
0.2
0.1
0.05
1
tp
δ= T
P
0.02
0.01
0
t
tp
T
10−1
10−6
10−5
10−4
10−3
10−2
10−1
tp (s)
1
Fig.4 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.
1997 Jun 17
4
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V(BR)DSS
drain-source breakdown voltage
VGS = 0; ID = 10 µA
30
−
−
V
VGSth
gate-source threshold voltage
VGS = VDS ; ID = 1 mA
1
−
2.8
V
IDSS
drain-source leakage current
VGS = 0; VDS = 24 V
−
−
100
nA
IGSS
gate leakage current
VGS = ±20 V; VDS = 0
−
−
±100
nA
RDSon
drain-source on-state resistance
VGS = 4.5 V; ID = 1 A
−
0.11
0.2
Ω
VGS = 10 V; ID = 2 A
−
0.08
0.1
Ω
Ciss
input capacitance
VGS = 0; VDS = 24 V; f = 1 MHz
−
250
−
pF
Coss
output capacitance
VGS = 0; VDS = 24 V; f = 1 MHz
−
140
−
pF
Crss
reverse transfer capacitance
VGS = 0; VDS = 24 V; f = 1 MHz
−
50
−
pF
Qg
total gate charge
VGS = 10 V; VDD = 15 V; ID = 2 A
−
10
30
nC
Qgs
gate-source charge
VGS = 10 V; VDD = 15 V; ID = 2 A
−
1
−
nC
Qgd
gate-drain charge
VGS = 10 V; VDD = 15 V; ID = 2 A
−
2.5
−
nC
VGS = 0 to 10 V; VDD = 15 V;
ID = 1 A; RL = 15 Ω; Rgen = 6 Ω
−
4.5
−
ns
−
3.5
−
ns
−
8
16
ns
−
15
−
ns
−
10
−
ns
−
25
50
ns
Switching times (see Fig.11)
td(on)
turn-on delay time
tf
fall time
ton
turn-on switching time
td(off)
turn-off delay time
tr
rise time
toff
turn-off switching time
VGS = 10 to 0 V; VDD = 15 V;
ID = 1 A; RL = 15 Ω; Rgen = 6 Ω
Source-drain diode
VSD
source-drain diode forward voltage
VGD = 0; IS = 1.25 A
−
−
1.2
V
trr
reverse recovery time
IS = 1.25 A; di/dt = −100 A/µs
−
35
100
ns
1997 Jun 17
5
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
MBE136
10
MBG748
18
handbook, halfpage
handbook, halfpage
VGS
ID
(A)
(V)
8
VGS =
10 V 6 V
16
5.5 V
4.5 V
6
12
4
8
4V
3.5 V
4
2
3V
2.5 V
0
0
2
4
0
6 Q (nC) 8
g
0
2
4
6
8
10
VDS (V)
VDD = 15 V: ID = 2 A.
Tj = 25 °C.
Fig.5
Gate-source voltage as a function of total
gate charge; typical values.
Fig.6 Output characteristics; typical values.
MBG747
16
MBG746
16
handbook, halfpage
handbook, halfpage
ID
(A)
IS
(A)
12
12
8
8
(1)
(2)
(3)
4
4
0
0
0
2
4
6 V
8
GS (V)
0
0.4
0.8
VSD (V)
1.2
VGD = 0.
(1) Tj = 150 °C.
(2) Tj = 25 °C.
(3) Tj = −65 °C.
VDS = 10 V; Tj = 25 °C.
Fig.8
Fig.7 Transfer characteristics; typical values.
1997 Jun 17
6
Source current as a function of source-drain
diode forward voltage; typical values.
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
MBG846
103
handbook, halfpage
MBG847
600
handbook, halfpage
ID= 100 mA
500 mA
1A
2A
4A
5.4 A
RDSon
(mΩ)
C
(pF)
400
102
Ciss
200
Coss
Crss
0
10
0
2
4
8
6
10
VGS (V)
0
8
16
VDS (V)
24
VDS ≥ ID × RDSon; Tj = 25 °C.
VGS = 0; f = 1 MHz; Tj = 25 °C.
Fig.9
Fig.10 Capacitance as a function of drain-source
voltage; typical values.
Drain-source on-resistance as a function of
gate-source voltage; typical values.
handbook, full pagewidth
90 %
VDD
Vin
RL
10 %
0
Vout
90 %
Vin
Vout
10 %
0
td(off)
td(on)
tf
ton
tr
toff
Fig.11 Switching time test circuit and input and output waveforms.
1997 Jun 17
7
MBH538
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
MBG745
1.2
MBG744
1.8
handbook, halfpage
handbook, halfpage
k
k
1.1
1.6
(1)
1.0
1.4
0.9
1.2
0.8
1.0
0.7
0.8
(2)
0.6
−75
−25
25
75
0.6
−75
125
175
Tj (oC)
−25
25
75
125
175
Tj (oC)
R DSon at T j
k = ---------------------------------------- Typical RDSon at:
R DSon at 25 °C
V GSth at T j
k = ------------------------------------V GSth at 25°C
Typical VGSth at VDS = GS; ID = 1 mA.
(1) ID = 2 A; VGS = 10 V.
(2) ID = 1 A; VGS = 4.5 V.
Fig.12 Temperature coefficient of gate-source
threshold voltage; typical values.
Fig.13 Temperature coefficient of drain-source
on-resistance; typical values.
1997 Jun 17
8
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
PACKAGE OUTLINE
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.050
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03S
MS-012AA
1997 Jun 17
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
9
o
8
0o
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
DEFINITIONS
Data Sheet Status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jun 17
10
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN110
NOTES
1997 Jun 17
11
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© Philips Electronics N.V. 1997
SCA54
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Printed in The Netherlands
137107/00/04/pp12
Date of release: 1997 Jun 17
Document order number:
9397 750 02385