DISCRETE SEMICONDUCTORS DATA SHEET PHC20512 Complementary enhancement mode MOS transistors Product specification Supersedes data of 1997 Jun 19 File under Discrete Semiconductors, SC13b 1997 Oct 22 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors FEATURES PHC20512 PINNING - SOT96-1 (SO8) • High-speed switching PIN SYMBOL DESCRIPTION • No secondary breakdown 1 s1 source 1 • Very low on-state resistance. 2 g1 gate 1 3 s2 source 2 APPLICATIONS 4 g2 gate 2 • Motor and actuator driver 5 d2 drain 2 • Power management 6 d2 drain 2 • Synchronized rectification. 7 d1 drain 1 8 d1 drain 1 DESCRIPTION One N-channel and one P-channel enhancement mode MOS transistor in an 8-pin plastic SOT96-1 (SO8) package. d1 d1 handbook, halfpage 8 5 1 4 d2 d2 CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. MAM118 g1 s1 s2 g2 Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per channel VDS VSD drain-source voltage (DC) N-channel − 30 V P-channel − −30 V − 1 V source-drain diode forward voltage N-channel IS = 1.25 A P-channel IS = −1.25 A VGS gate-source voltage (DC) VGSth gate-source threshold voltage ID RDSon Ptot 1997 Oct 22 − −1.3 V − ±20 V N-channel VDS = VGS; ID = 1 mA 1 2.8 V P-channel VDS = VGS ; ID = −1 mA −1 −2.8 V N-channel − 6.4 A P-channel − −4 A drain current (DC) Ts = 80 °C drain-source on-state resistance N-channel VGS = 10 V; ID = 3.2 A − 0.05 Ω P-channel VGS = −10 V ID = −2 A − 0.12 Ω Ts = 80 °C − 3.5 W total power dissipation 2 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per channel VDS drain-source voltage (DC) N-channel − 30 V P-channel − −30 V − ±20 V N-channel − 6.4 A P-channel − −4 A − 25 A VGS gate-source voltage (DC) ID drain current (DC) IDM Ts = 80 °C; note 1 peak drain current note 2 N-channel − −16 A Ts = 80 °C; note 3 − 3.5 W Tamb = 25 °C; note 4 − 2.6 W Tamb = 25 °C; note 5 − 1.1 W Tamb = 25 °C; note 6 − 1.5 W P-channel Ptot total power dissipation Tstg storage temperature −65 +150 °C Tj operating junction temperature −65 +150 °C N-channel − 3.5 A P-channel − −2.6 A N-channel − 14 A P-channel − −10 A Source-drain diode IS ISM Ts = 80 °C source current (DC) peak pulsed source current note 2 Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time. 4. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 27.5 K/W. 5. Maximum permissible dissipation per MOS transistor. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on printed-circuit board with an Rth a-tp (ambient to tie-point) of 90 K/W. 1997 Oct 22 3 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 MGG340 8 MGG341 102 handbook, halfpage handbook, halfpage Ptot ID (A) (W) 6 tp = 10 10 µs (1) 100 µs 4 1 δ= P 1 ms tp T 10 ms t 100 ms DC 2 tp 10−1 0 0 50 100 10−1 150 Ts (°C) T 1 10 VDS (V) δ = 0.01; Ts = 80 °C. (1) RDSon limitation. Fig.2 Power derating curve. Fig.3 SOAR; N-channel. MBH587 −102 handbook, halfpage ID (A) tp = −10 10 µs (1) 100 µs 1 ms −1 δ= P tp 10 ms T 100 ms DC t tp T −10−1 −10−1 −1 −10 VDS (V) −102 δ = 0.01; Ts = 80 °C. (1) RDSon limitation. Fig.4 SOAR; P-channel. 1997 Oct 22 4 102 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 THERMAL CHARACTERISTICS SYMBOL Rth j-s PARAMETER VALUE UNIT 20 K/W thermal resistance from junction to soldering point CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per channel V(BR)DSS VGSth IDSS IGSS RDSon Ciss Coss Crss QG QGS 1997 Oct 22 drain-source breakdown voltage N-channel VGS = 0; ID = 10 µA 30 − − V P-channel VGS = 0; ID = −10 µA −30 − − V N-channel VGS = VDS ; ID = 1 mA 1 − 2.8 V P-channel VGS = VDS ; ID = −1 mA −1 − −2.8 V N-channel VGS = 0; VDS = 24 V − − 100 nA P-channel VGS = 0; VDS = −24 V − − −100 nA N-channel − − ±100 nA P-channel − − ±100 nA − − 0.1 Ω gate-source threshold voltage drain-source leakage current gate leakage current VGS = ±20 V; VDS = 0 drain-source on-state resistance N-channel VGS = 4.5 V; ID = 1.6 A VGS = 10 V; ID = 3.2 A − − 0.05 Ω P-channel VGS = −4.5 V; ID = −1 A − − 0.25 Ω VGS = −10 V; ID = −2 A − − 0.12 Ω N-channel VGS = 0; VDS = 24 V; f = 1 MHz − 450 − pF P-channel VGS = 0; VDS = −24 V; f = 1 MHz − 450 − pF N-channel VGS = 0; VDS = 24 V; f = 1 MHz − 200 − pF P-channel VGS = 0; VDS = −24 V; f = 1 MHz − 200 − pF N-channel VGS = 0; VDS = 24 V; f = 1 MHz − 100 − pF P-channel VGS = 0; VDS = −24 V; f = 1 MHz − 100 − pF input capacitance output capacitance reverse transfer capacitance total gate charge N-channel VGS = 10 V; VDD = 15 V; ID = 3.2 A − 15 − nC P-channel VGS = −10 V; VDD = −15 V; ID = −2 A − 13 − nC gate-source charge N-channel VGS = 10 V; VDD = 15 V; ID = 3.2 A − 1 − nC P-channel VGS = −10 V; VDD = −15 V; ID = −2 A − 1 − nC 5 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors SYMBOL QGD td(on) td(off) tf tr ton toff PHC20512 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT gate-drain charge N-channel VGS = 10 V; VDD = 15 V; ID = 3.2 A − 5 − nC P-channel VGS = −10 V; VDD = −15 V; ID = −2 A − 4 − nC N-channel VGS = 0 to 10 V; VDD = 15 V; ID = 1 A; − Rgen = 6 Ω 7 − ns P-channel VGS = 0 to −10 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 6 − ns N-channel VGS = 10 to 0 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω − 20 − ns P-channel VGS = −10 to 0 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 29 − ns turn-on delay time turn-off delay time fall time N-channel VGS = 0 to 10 V; VDD = 15 V; ID = 1 A; − Rgen = 6 Ω 8 − ns P-channel VGS = −10 to 0 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 16 − ns N-channel VGS = 10 to 0 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω − 12 − ns P-channel VGS = 0 to −10 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 4 − ns rise time turn-on switching time N-channel VGS = 0 to 10 V; VDD = 15 V; ID = 1 A; − Rgen = 6 Ω 15 − ns P-channel VGS = 0 to −10 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 10 − ns N-channel VGS = 10 to 0 V; VDD = 15 V; ID = 1 A; Rgen = 6 Ω − 32 − ns P-channel VGS = −10 to 0 V; VDD = −15 V; ID = −1 A; Rgen = 6 Ω − 45 − ns N-channel VGD = 0; IS = 1.25 A − − 1 V P-channel VGD = 0; IS = −1.25 A − − −1.3 V N-channel IS = 1.25 A; di/dt = −100 A/µs − 45 − ns P-channel IS = −1.25 A; di/dt = 100 A/µs − 75 − ns turn-off switching time Source-drain diode VSD trr 1997 Oct 22 source-drain diode forward voltage reverse recovery time 6 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors handbook, full pagewidth PHC20512 VDD 90 % Vin RL 10 % 0 Vout 90 % Vout Vin 10 % 0 td(off) td(on) tf MAM274 tr ton toff Fig.5 Switching times test circuit with input and output waveforms; N-channel. 0 handbook, full pagewidth −VDD 10 % Vin 90 % RL Vout 0 10 % 10 % Vout Vin 90 % 90 % td(off) td(on) tr ton tf toff MGD391 Fig.6 Switching times test circuit with input and output waveforms; P-channel. 1997 Oct 22 7 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 MGG342 102 handbook, full pagewidth Rth js (K/W) (1) (2) 10 (3) (4) (5) (6) 1 δ= P tp T (7) (8) 10−1 10−6 T 10−5 10−4 (1) δ = 0.75. (2) δ = 0.5. (3) δ = 0.33. (4) δ = 0.2. (5) δ = 0.1. (6) δ = 0.05. (7) δ = 0.02. (8) δ = 0.01. Fig.7 t tp (9) 10−3 10−2 10−1 (9) δ = 0. Transient thermal resistance from junction to soldering point as a function of pulse time for N- and P-channels; typical values. 1997 Oct 22 8 tp (s) 1 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 MGG343 1250 C (pF) MGG352 1250 C (pF) handbook, halfpage handbook, halfpage 1000 1000 750 750 (1) 500 (1) 500 (2) (2) 250 250 (3) (3) 0 0 0 4 8 12 16 20 VDS (V) −4 0 −8 VGS = 0; f = 1 MHz; Tj = 25 °C. (1) Ciss. (2) Coss. (3) Crss. VGS = 0; f = 1 MHz; Tj = 25 °C. (1) Ciss. (2) Coss. (3) Crss. Fig.8 Fig.9 Capacitance as a function of drain-source voltage; N-channel typical values. MGG344 30 −16 −20 VDS (V) Capacitance as a function of drain source voltage; P-channel typical values. MGG353 −16 handbook, halfpage ID −12 handbook, halfpage (1) ID (A) (1) (A) (2) −12 (2) 20 (3) −8 (3) (4) 10 (4) −4 (5) (5) (6) (6) 0 0 0 4 Tamb = 25 °C; tp = 80 µs; δ = 0. (1) VGS = 10 V. (2) VGS = 5 V. (3) VGS = 4.5 V. 8 VDS (V) 12 0 Tamb = 25 °C; tp = 80 µs; δ = 0. (1) VGS = −10 V. (2) VGS = −5 V. (3) VGS = −4.5 V. (4) VGS = 4 V. (5) VGS = 3.5 V. (6) VGS = 3 V. Fig.10 Output characteristics; N-channel typical values. 1997 Oct 22 −4 −8 VDS (V) (4) VGS = −4 V. (5) VGS = −3.5 V. (6) VGS = −3 V. Fig.11 Output characteristics; P-channel typical values. 9 −12 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 MGG345 30 MGG354 −16 handbook, halfpage handbook, halfpage ID (A) ID (A) −12 20 −8 10 −4 0 0 0 2 4 VGS (V) 6 −2 0 −4 VGS (V) VDS = 10 V; Tamb = 25 °C; tp = 80 µs; δ = 0. VDS = −10 V; Tamb = 25 °C; tp = 80 µs; δ = 0. Fig.12 Transfer characteristic; N-channel typical values. Fig.13 Transfer characteristic; P-channel typical values. MGG346 16 MGG355 −16 handbook, halfpage −6 handbook, halfpage V (V) VDS, VGS (V) 12 −12 8 −8 (1) (1) (2) (2) −4 4 0 0 0 4 8 12 16 0 4 8 QG (nC) 12 16 QG (nC) VDD = 12.5 V; ID = 3.2 A; Tamb = 25 °C. VDD = −12.5 V; ID = −2 A; Tamb = 25 °C. (1) VDS. (2) VGS. (1) VDS. (2) VGS. Fig.14 Gate-source voltage and drain-source voltage as a function of total gate charge; N-channel typical values. Fig.15 Gate-source voltage and drain-source voltage as a function of total gate charge; P-channel typical values. 1997 Oct 22 10 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 MGG347 16 MGG356 −10 handbook, halfpage handbook, halfpage IS (A) IS (A) −8 12 (1) (2) −6 (3) (1) (2) (3) 8 −4 4 −2 0 0 0 0.4 0.8 VSD (V) 1.2 0 −0.4 −0.8 VSD (V) −1.2 VGD = 0. (1) Tamb = 150 °C; tp = 300 µs; δ = 0. (2) Tamb = 25 °C; tp = 300 µs; δ = 0. (3) Tamb = −65 °C; tp = 300 µs; δ = 0. VGD = 0. (1) Tamb = 150 °C; tp = 300 µs; δ = 0. (2) Tamb = 25 °C; tp = 300 µs; δ = 0. (3) Tamb = −65 °C; tp = 300 µs; δ = 0. Fig.16 Source current as a function of source-drain diode forward voltage; N-channel typical values. Fig.17 Source current as a function of source-drain diode forward voltage; P-channel typical values. 1997 Oct 22 11 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 MGG348 103 handbook, halfpage 103 handbook, halfpage RDSon RDSon (mΩ) (1) (2) (3) (4) (5) (mΩ) 102 10 MGG357 (1) (2) (3) (4) (5) (6) 102 0 2 4 6 8 10 10 VGS (V) 0 −2 −4 −6 −8 −10 VGS (V) VDS ≥ ID × RDSon; Tamb = 25 °C; tp = 300 µs; δ = 0. VDS ≥ ID × RDSon; Tamb = 25 °C; tp = 300 µs; δ = 0. ID = 0.1 A. ID = 0.5 A. ID = 1 A. ID = 2 A. (5) ID = 4 A. (6) ID = 8 A. (1) (2) (3) (4) (1) ID = 0.5 A. (2) ID = 1.6 A. (3) ID = 3.2 A. (4) ID = 6.4 A. (5) ID = 10 A. Fig.18 Drain-source on-state resistance as a function of gate-source voltage; N-channel typical values. 1997 Oct 22 Fig.19 Drain-source on-state resistance as a function of gate-source voltage; P-channel typical values. 12 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 MGG349 1.3 MGG358 1.3 handbook, halfpage handbook, halfpage k k 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 −100 −50 0 50 100 0.7 −100 150 Tj (°C) −50 0 50 100 150 Tj (°C) V GSth at T j k = ------------------------------------V GSth at 25°C V GSth at T j k = ------------------------------------V GSth at 25°C VGSth at VDS = VGS; ID = 1 mA. VGSth at VDS = VGS; ID = −1 mA. Fig.20 Temperature coefficient of gate-source threshold voltage as a function of junction temperature; N-channel typical values. Fig.21 Temperature coefficient of gate-source threshold voltage as function of junction temperature; P-channel typical values. 1997 Oct 22 13 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 MGG359 2 MGG359 2 handbook, halfpage handbook, halfpage k k (1) (1) 1.5 1.5 (2) (2) 1 1 0.5 0.5 0 −100 −50 0 50 100 0 −100 150 Tj (°C) −50 0 R DSon at T j k = ---------------------------------------R DSon at 25 °C R DSon at T j k = ---------------------------------------R DSon at 25 °C (1) RDSon at VGS = 10 V; ID = 3.2 A. (2) RDSon at VGS = 4.5 V; ID = 1.6 A. (1) RDSon at VGS = −10 V; ID = −2 A. (2) RDSon at VGS = −4.5 V; ID = −1 A. Fig.22 Temperature coefficient of drain-source on-resistance as a function of junction temperature; N-channel typical values. 1997 Oct 22 50 100 150 Tj (°C) Fig.23 Temperature coefficient of drain-source on-resistance as a function of junction temperature; P-channel typical values. 14 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 PACKAGE OUTLINE SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.244 0.039 0.028 0.050 0.041 0.228 0.016 0.024 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA 1997 Oct 22 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 15 o 8 0o Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Oct 22 16 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 NOTES 1997 Oct 22 17 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 NOTES 1997 Oct 22 18 Philips Semiconductors Product specification Complementary enhancement mode MOS transistors PHC20512 NOTES 1997 Oct 22 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 137107/00/03/pp20 Date of release: 1997 Oct 22 Document order number: 9397 750 02977