PHILIPS PHP222

DISCRETE SEMICONDUCTORS
DATA SHEET
M3D315
PHP222
Dual P-channel enhancement
mode MOS transistor
Preliminary specification
Supersedes data of 1998 Mar 24
File under Discrete Semiconductors, SC13
1998 Apr 01
Philips Semiconductors
Preliminary specification
Dual P-channel enhancement
mode MOS transistor
PHP222
FEATURES
PINNING - SOT96-1 (SO8)
• Very low on-state resistance
PIN
SYMBOL
DESCRIPTION
• High-speed switching
1
s1
source 1
• No secondary breakdown
2
g1
gate 1
• Low threshold.
3
s2
source 2
4
g2
gate 2
APPLICATIONS
5
d2
drain 2
• Power management
6
d2
drain 2
• DC-DC converters
7
d1
drain 1
• General purpose switch.
8
d1
drain 1
DESCRIPTION
Two P-channel enhancement mode MOS transistors in an
8-pin SOT96-1 (SO8) SMD plastic package.
d2 d2
d1 d1
handbook, halfpage
8
5
1
4
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
MAM119
s1
g
1
s2
g
2
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−
−30
V
IS = −1.25 A; VGD = 0
−
−1.3
V
gate-source voltage (DC)
open drain
−
±8
V
gate-source threshold voltage
ID = −1 mA; VDS = VGS
−0.4
−
V
ID
drain current (DC)
Ts = 80 °C
−
−3.2
A
RDSon
drain-source on-state resistance
ID = −1.6 A; VGS = −2.5 V
−
220
mΩ
Ptot
total power dissipation
Ts = 80 °C
−
3.5
W
VDS
drain-source voltage (DC)
VSD
source-drain diode forward voltage
VGSO
VGSth
1998 Apr 01
2
Philips Semiconductors
Preliminary specification
Dual P-channel enhancement
mode MOS transistor
PHP222
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per P-channel
VDS
drain-source voltage (DC)
VGSO
gate-source voltage (DC)
−
−30
V
open drain
−
±8
V
ID
drain current (DC)
Ts = 80 °C; note 1
−
−3.2
A
IDM
peak drain current
note 2
−
−12.8
A
Ptot
total power dissipation
Ts = 80 °C; note 3
−
3.5
W
Tamb = 25 °C; note 4
−
2.63
W
Tamb = 25 °C; note 5
−
1.14
W
Tamb = 25 °C; note 6
−
1.56
W
Tstg
storage temperature
−55
+150
°C
Tj
operating junction temperature
−55
+150
°C
Source-drain diode
IS
source current (DC)
Ts = 80 °C
−
−2.7
A
ISM
peak pulsed source current
note 2
−
−10.8
A
Notes
1. Ts is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Maximum permissible dissipation per MOS transistor. Both devices may be loaded up to 3.5 W at the same time.
4. Maximum permissible dissipation per MOS transistor. Device mounted on a printed-circuit board with an Rth a-tp
(ambient to tie-point) of 27.5 K/W.
5. Maximum permissible dissipation per MOS transistor. Device mounted on a printed-circuit board with an Rth a-tp
(ambient to tie-point) of 90 K/W.
6. Maximum permissible dissipation if only one MOS transistor dissipates. Device mounted on a printed-circuit board
with an Rth a-tp (ambient to tie-point) of 90 K/W.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-s
1998 Apr 01
PARAMETER
thermal resistance from junction to soldering point
3
VALUE
UNIT
20
K/W
Philips Semiconductors
Preliminary specification
Dual P-channel enhancement
mode MOS transistor
PHP222
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Per P-channel
V(BR)DSS
drain-source breakdown voltage
VGS = 0; ID = −10 µA
−30
−
−
V
VGSth
gate-source threshold voltage
VGS = VDS ; ID = −1 mA
−0.4
−
−
V
IDSS
drain-source leakage current
VGS = 0; VDS = −24 V
−
−
−100
nA
IGSS
gate leakage current
VGS = ±8 V; VDS = 0
−
−
±100
nA
RDSon
drain-source on-state resistance
VGS = −4.5 V; ID = −1.6 A
−
−
200
mΩ
VGS = −2.5 V; ID = −1.6 A
−
−
220
mΩ
VGS = −1.8 V; ID = −0.8 A
−
−
250
mΩ
Ciss
input capacitance
VGS = 0; VDS = −24 V; f = 1 MHz
−
696
−
pF
Coss
output capacitance
VGS = 0; VDS = −24 V; f = 1 MHz
−
163
−
pF
Crss
reverse transfer capacitance
VGS = 0; VDS = −24 V; f = 1 MHz
−
73
−
pF
QG
total gate charge
VGS = −4.5 V; VDD = −15 V;
ID = −1 A; Tamb = 25 °C
−
16
−
nC
QGS
gate-source charge
VDD = −15 V; ID = −1 A; Tamb = 25 °C −
0.7
−
nC
QGD
gate-drain charge
VDD = −15 V; ID = −1 A; Tamb = 25 °C −
4.1
−
nC
VGS = 0 to −8 V; VDD = −20 V;
ID = −1 A; Rgen = 6 Ω
−
3.5
−
ns
−
4
−
ns
−
7.5
−
ns
−
90
−
ns
−
35
−
ns
−
125
−
ns
Switching times
td(on)
turn-on delay time
tr
rise time
ton
turn-on switching time
td(off)
turn-off delay time
tf
fall time
toff
turn-off switching time
VGS = −8 to 0 V; VDD = −20 V;
ID = −1 A; Rgen = 6 Ω
Source-drain diode
VSD
source-drain diode forward
voltage
VGD = 0; IS = −1.25 A
−
−
−1.3
V
trr
reverse recovery time
IS = −1.25 A; di/dt = 100 A/µs
−
65
−
ns
1998 Apr 01
4
Philips Semiconductors
Preliminary specification
Dual P-channel enhancement
mode MOS transistor
PHP222
PACKAGE OUTLINE
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
0.16
0.15
0.244
0.039 0.028
0.050
0.041
0.228
0.016 0.024
inches
0.010 0.057
0.069
0.004 0.049
0.01
0.01
0.028
0.004
0.012
θ
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03S
MS-012AA
1998 Apr 01
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
5
o
8
0o
Philips Semiconductors
Preliminary specification
Dual P-channel enhancement
mode MOS transistor
PHP222
DEFINITIONS
Data Sheet Status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Apr 01
6
Philips Semiconductors
Preliminary specification
Dual P-channel enhancement
mode MOS transistor
PHP222
NOTES
1998 Apr 01
7
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© Philips Electronics N.V. 1998
SCA59
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Printed in The Netherlands
135108/00/03/pp8
Date of release: 1998 Apr 01
Document order number:
9397 750 03657