INTEGRATED CIRCUITS 74LV377 Octal D-type flip-flop with data enable; positive edge-trigger Product specification Supersedes data of 1997 Mar 04 IC24 Data Handbook 1998 Jun 10 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger FEATURES 74LV377 DESCRIPTION • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V • Typical VOLP (output ground bounce) 0.8V @ VCC = 3.3V, The 74LV377 is a low–voltage CMOS device and is pin and function compatible with 74HC/HCT377. The 74LV377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. Tamb = 25°C • Typical VOHV (output VOH undershoot) 2V @ VCC = 3.3V, Tamb = 25°C • Ideal for addressable register applications • Data enable for address and data synchronization applications • Eight positive-edge triggered D-type flip-flops • Output capability: standard • ICC category: MSI QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf 2.5 ns PARAMETER SYMBOL tPHL/tPLH Propagation delay CP to Qn fmax Maximum clock frequency CI Input capacitance CPD Power dissipation capacitance per flip-flop CONDITIONS CL = 15pF VCC = 3.3V 3 3V Notes 1 and 2 TYPICAL UNIT 13 ns 77 MHz 3.5 pF 20 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 fi (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL VCC2 fo) = sum of the outputs. 2. The condition is VI = GND to VCC ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL PACKAGES –40°C to +125°C 74LV377 N 74LV377 N SOT146-1 20-Pin Plastic SO –40°C to +125°C 74LV377 D 74LV377 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +125°C 74LV377 DB 74LV377 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +125°C 74LV377 PW 74LV377PW DH SOT360-1 PIN DESCRIPTION PIN NUMBER 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 FUNCTION TABLE SYMBOL E Q0 to Q7 FUNCTION OPERATING MODES Data enable input (active-LOW) flip-flop outputs D0 to D7 Data inputs 10 GND Ground (0V) 11 CP Clock input (LOW-to-HIGH, edge-triggered) 20 VCC Positive supply voltage H h L l ↑ X 1998 Jun 10 2 INPUTS OUTPUTS CP E Dn Qn Load ‘‘1’’ ↑ l h H Load ‘‘0’’ ↑ l l L Hold (do nothing) ↑ X h H X X No change No change = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW–to–HIGH CP transition = Don’t care 853–1935 19545 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 PIN CONFIGURATION LOGIC SYMBOL (IEEE/IEC) 11 1C2 1 E 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 3 D1 4 17 D6 4 5 Q1 5 16 Q6 7 6 Q2 6 15 Q5 8 9 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP G1 2 2D 13 12 14 15 17 16 18 19 SV00667 SV00669 LOGIC SYMBOL FUNCTIONAL DIAGRAM 11 3 3 4 7 8 13 14 D0 CP D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 17 D6 18 D7 Q0 Q5 2 4 5 7 6 8 9 13 12 14 15 Q6 16 Q7 19 17 18 E 1 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 FF1 to FF8 OUTPUTS Q4 D5 Q5 D6 Q6 D7 Q7 2 5 6 9 12 15 16 19 E CP 11 1 SV00668 1998 Jun 10 SV00670 3 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER DC supply voltage CONDITIONS MIN TYP MAX UNIT See Note 1 1.0 3.3 3.6 V VI Input voltage 0 – VCC V VO Output voltage 0 – VCC V +85 +125 °C 500 200 100 ns/V Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times See DC and AC characteristics VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V –40 –40 – – – – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V. ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL PARAMETER CONDITIONS RATING UNIT –0.5 to +4.6 V VCC DC supply voltage ±IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA ±IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA ±IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 mA 50 mA –65 to +150 °C ±IGND, ±ICC DC VCC or GND current for types with –standard outputs Tstg Storage temperature range Ptot t t Power dissipation per package –plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP) for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Jun 10 4 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 DC CHARACTERISTICS FOR THE LV FAMILY Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS MIN VIH VIL HIGH level l l Input I t voltage LOW level l l Input I t voltage VOH HIGH level output voltage; STANDARD outputs LOW level output voltage; all outputs VOL -40°C to +125°C MAX MIN VCC = 1.2V 0.9 0.9 VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 UNIT MAX V VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 VCC = 1.2V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage; all outputs TYP1 V 1.2 VCC = 2.0V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 3.0V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 V VCC = 1.2V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 0.25 0.40 0.50 V LOW level output voltage; STANDARD outputs VCC = 3.0V; VI = VIH or VIL; IO = 6mA Input leakage current VCC = 3.6V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; MSI VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 160 µA ∆ICC Additional quiescent supply current per input VCC = 2.7V to 3.6V; VI = VCC – 0.6V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. 1998 Jun 10 5 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL =1KW SYMBOL tPHL//tPLH tW tsu tsu th th fmax PARAMETER Propagation g delay y CP to Qn Cl k pulse l width idth Clock HIGH or LOW Set-up time Dn to CP Set-up time E to CP Hold time Dn to CP Hold time E to CP M i l k Maximum clock ulse frequency pulse WAVEFORM –40 to +85 °C VCC(V) MIN TYP1 1.2 – 2.0 – 2.7 –40 to +125 °C MAX MIN 80 – – – 27 51 – 61 – 20 38 – 45 3.0 to 3.6 – 152 30 – 36 2.0 34 9 – 41 – Figure 1 2.7 25 6 – 30 – 20 52 – 24 – 1.2 – 25 – – – 2.0 22 9 – 26 – 2.7 16 6 – 19 – 3.0 to 3.6 13 52 – 15 – 1.2 – 10 – – – 2.0 22 4 – 26 – 2.7 16 3 – 19 – 3.0 to 3.6 13 22 – 15 – 1.2 – –15 – – – 2.0 5 –5 – 5 – 2.7 5 –4 – 5 – 3.0 to 3.6 5 –32 – 5 – 1.2 – –5 – – – 2.0 5 –2 – 5 – 2.7 5 –2 – 5 – 3.0 to 3.6 5 –12 – 5 – 2.0 14 40 – 12 – 2.7 19 58 – 16 – 3.0 to 3.6 24 702 – 20 – Figure 2 Figure 2 Figure 2 Figure 2 Figure 1 6 UNIT MAX 3.0 to 3.6 Figure 2 NOTES: 1. Unless otherwise stated, all typical values are at Tamb = 25°C. 2. Typical value measured at VCC = 3.3V. 1998 Jun 10 LIMITS CONDITION ns ns ns ns ns ns MHz Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 AC WAVEFORMS TEST CIRCUIT VM = 1.5V at VCC 2.7V VM = 0.5V * VCC at VCC 2.7V VOL and VOH are the typical output voltage drop that occur with the output load. VCC CP INPUT VO VI 1/fmax VCC PULSE GENERATOR D.U.T. VM 50pF RT CL GND RL = 1k tW tPLH tPHL Test Circuit for switching times VOH Qn OUTPUT DEFINITIONS VM RL = Load resistor CL = Load capacitance includes jig and probe capacitance VOL RT = Termination resistance should be equal to ZOUT of pulse generators. SV00707 Figure 1. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. VCC E INPUT TEST ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ tPLH/tPHL VCC Dn INPUT GND VCC CP INPUT th tsu STABLE VM tsu th tW VM GND NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SV00671 Figure 2. Data set-up and hold times from the data input (Dn) and from the enable input (E) to the clock (CP). 1998 Jun 10 VI VCC 2.7V SV00901 Figure 3. GND th < 2.7V 2.7–3.6V VM tsu VCC 7 Load circuitry for switching times Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 DIP20: plastic dual in-line package; 20 leads (300 mil) 1998 Jun 10 8 SOT146-1 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 SO20: plastic small outline package; 20 leads; body width 7.5 mm 1998 Jun 10 9 SOT163-1 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1998 Jun 10 10 SOT339-1 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1998 Jun 10 11 SOT360-1 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive edge-trigger 74LV377 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Jun 10 12 Date of release: 05-96 9397-750-04449