PHILIPS TZA3017HW

INTEGRATED CIRCUITS
DATA SHEET
TZA3017HW
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
Product specification
Supersedes data of 2002 Jan 16
2003 May 14
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
FEATURES
• Single 3.3 V power supply
• I2C-bus and pin programmable fibre optic transmitter.
Synthesizer features
• Exchangeable pin designations of RF clock with data for
all I/Os for optimum connectivity
• Supports SDH/SONET bit rates at 155.52, 622.08,
2488.32 and 2666.06 Mbits/s (STM16/OC48 + FEC)
• Reversible pin designations of parallel data bus bits for
optimum connectivity
• Supports Gigabit Ethernet at 1250 and 3125 Mbits/s
• Supports Fibre Channel at 1062.5 and 2125 Mbits/s
• Four reference frequency ranges.
• Loss Of Lock (LOL) indicator
• ITU-T compliant jitter generation.
APPLICATIONS
• Any optical transmission system with bit rates between
30 Mbits/s and 3.2 Gbits/s
Multiplexer features
• 16:1, 10:1, 8:1 or 4:1 multiplexing ratio
• Physical interface IC in transmit channels
• Rail-to-rail parallel inputs compliant with LVPECL, CML
and LVDS
• Transponder applications
• Dense Wavelength Division Multiplexing (DWDM)
systems.
• 4-stage FIFO for wide tolerance to clock skew
• Supports co-directional and contra-directional clocking
• Programmable parity checking
GENERAL DESCRIPTION
• CML data and clock outputs, and loop mode inputs
The TZA3017HW is a fully integrated optical network
transmitter, containing a clock synthesizer and a
multiplexer with multiplexing ratios of 16:1, 10:1, 8:1
or 4:1.
• LVPECL outputs on parallel interface
• Line loop back input
• Diagnostic loop back output.
Additional features with the
The A-rate feature allows the IC to operate at any bit rate
between 30 Mbits/s and 3.2 Gbits/s using a single
reference frequency. The transmitter supports loop modes
with serial clock and data inputs and outputs. All clock
signals are generated using a fractional N synthesizer with
10 Hz resolution giving a true, continuous rate operation.
For full configuration flexibility, the transmitter is
programmable either by pin or via the I2C-bus.
I2C-bus
• A-rateTM(1) supports any bit rate from 30 Mbits/s to
3.2 Gbits/s with one reference frequency
• Programmable frequency resolution of 10 Hz
• Adjustable swings of data and clock outputs
• CML outputs on parallel interface
• Programmable polarity of all RF I/Os
(1) Koninklijke Philips Electronics N.V.
ORDERING INFORMATION
TYPE
NUMBER
TZA3017HW
2003 May 14
PACKAGE
NAME
HTQFP100
DESCRIPTION
plastic, heatsink thin quad flat package; 100 leads;
body 14 × 14 × 1.0 mm
2
VERSION
SOT638−1
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PARERRQ
PAREVEN
PARITY
PARITYQ
82
78
79
INTERRUPT
CONTROLLER
74
84
44
D
C
38
67
2
37
16
PARITY
CHECKER
AND
BUS SWAP
66
60
16
4 deep
16
16
FIFO
16
3
3, 5, 7, 9, 11, 14, 16,
18, 20, 22, 27, 29, 31,
94, 96, 98
W
MUX
4:1
8:1
10 : 1
16 : 1
2
2
59
D
2
89
2
R
88
92
2
91
34
85
TZA3017HW
86
52
POCLK
POCLKQ
2
POWER-ON
RESET
CLOCK
SYNTHESIZER
71
53
I2C-BUS
54
2
40
72
0° / 90°
PHASE SHIFT
39
1, 25, 33, 36, 41, 49,
58, 61, 64, 65, 68, 77,
80, 83, 87, 90, 93, 100
57
48
47
43
42
75
69
51
18
MD0
MD1
PRSCLO
LOL
CREF
VCCD VCCA VCCO
PRSCLOQ CREFQ
Fig.1 Simplified block diagram.
2, 13, 24,
26, 50,
70, 76
7
VDD
VEE
MGW559
DLOOP
DLOOPQ
CLOOP
CLOOPQ
ENLOUTQ
ENLINQ
SCL(DR2)
SDA(DR1)
CS(DR0)
UI
Product specification
63
COUTQ
TZA3017HW
62
COUT
C
35
2
DOUT
DOUTQ
16
D00Q to D15Q
CLKDIR
INT
73
4, 6, 8, 10, 12, 15, 17,
19, 21, 23, 28, 30, 32,
95, 97, 99
PICLKQ
81
56
D00 to D15
PICLK
DINQ
Philips Semiconductors
PARERR
45
DIN
CIN
CINQ
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
FIFORESET
46
55
BLOCK DIAGRAM
handbook, full pagewidth
2003 May 14
OVERFLOW
MUXR1
MUXR0
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
PINNING
SYMBOL
VEE
SYMBOL
PIN
DESCRIPTION
die pad common ground plane
PIN
DESCRIPTION
POCLK
40
parallel clock output
VCCD
41
supply voltage (digital part)
VCCD
1
supply voltage (digital part)
CREFQ
42
reference clock input inverted
VEE
2
ground
CREF
43
reference clock input
D12Q
3
parallel data input 12 inverted
PAREVEN
44
parity select (odd or even)
D12
4
parallel data input 12
MUXR1
45
multiplexing ratio select 1
D11Q
5
parallel data input 11 inverted
MUXR0
46
multiplexing ratio select 0
D11
6
parallel data input 11
PRSCLOQ
47
prescaler output signal inverted
D10Q
7
parallel data input 10 inverted
PRSCLO
48
prescaler output signal
D10
8
parallel data input 10
VCCD
49
supply voltage (digital part)
D09Q
9
parallel data input 09 inverted
VEE
50
ground
D09
10
parallel data input 09
VDD
51
supply voltage (digital part)
D08Q
11
parallel data input 08 inverted
SCL(DR2)
52
D08
12
parallel data input 08
I2C-bus serial clock (data rate
select 2)
VEE
13
ground
SDA(DR1)
53
D07Q
14
parallel data input 07 inverted
I2C-bus serial data (data rate
select 1)
D07
15
parallel data input 07
CS(DR0)
54
chip select (data rate select 0)
OVERFLOW
55
FIFO overflow alarm output
FIFORESET
56
FIFO reset input
LOL
57
loss of lock output
VCCD
58
supply voltage (digital part)
COUTQ
59
serial clock output inverted
COUT
60
serial clock output
VCCD
61
supply voltage (digital part)
MD0
62
parallel data input termination
mode select 0
MD1
63
parallel data input termination
mode select 1
D06Q
16
parallel data input 06 inverted
D06
17
parallel data input 06
D05Q
18
parallel data input 05 inverted
D05
19
parallel data input 05
D04Q
20
parallel data input 04 inverted
D04
21
parallel data input 04
D03Q
22
parallel data input 03 inverted
D03
23
parallel data input 03
VEE
24
ground
VCCD
25
supply voltage (digital part)
VEE
26
ground
VCCD
64
supply voltage (digital part)
D02Q
27
parallel data input 02 inverted
VCCD
65
supply voltage (digital part)
D02
28
parallel data input 02
DOUTQ
66
serial data output inverted
D01Q
29
parallel data input 01 inverted
DOUT
67
serial data output
D01
30
parallel data input 01
VCCD
68
supply voltage (digital part)
D00Q
31
parallel data input 00 inverted
VCCO
69
D00
32
parallel data input 00
supply voltage (clock
generator)
VCCD
33
supply voltage (digital part)
VEE
70
ground
PICLKQ
34
parallel clock input inverted
CLKDIR
71
PICLK
35
parallel clock input
selection between co- and
contra-directional clocking
VCCD
36
supply voltage (digital part)
UI
72
user interface select
73
parity error output inverted
PARITYQ
37
parity input inverted
PARERRQ
PARITY
38
parity input
PARERR
74
parity error output
POCLKQ
39
parallel clock output inverted
VCCA
75
supply voltage (analog part)
2003 May 14
4
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
SYMBOL
PIN
TZA3017HW
DESCRIPTION
SYMBOL
CLOOPQ
PIN
DESCRIPTION
91
loop mode clock output
inverted
VEE
76
ground
VCCD
77
supply voltage (digital part)
DINQ
78
loop mode data input inverted
CLOOP
92
loop mode clock output
93
supply voltage (digital part)
94
parallel data input 15 inverted
DIN
79
loop mode data input
VCCD
VCCD
80
supply voltage (digital part)
D15Q
CINQ
81
loop mode clock input inverted
D15
95
parallel data input 15
96
parallel data input 14 inverted
CIN
82
loop mode clock input
D14Q
VCCD
83
supply voltage (digital part)
D14
97
parallel data input 14
INT
84
interrupt output
D13Q
98
parallel data input 13 inverted
diagnostic loop back enable
input (active LOW)
D13
99
parallel data input 13
VCCD
100
supply voltage (digital part)
ENLOUTQ
ENLINQ
85
86
line loop back enable input
(active LOW)
VCCD
87
supply voltage (digital part)
DLOOPQ
88
loop mode data output inverted
DLOOP
89
loop mode data output
VCCD
90
supply voltage (digital part)
2003 May 14
5
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
77 VCCD
76 VEE
78 DINQ
81 CINQ
80 VCCD
79 DIN
83 VCCD
82 CIN
84 INT
85 ENLOUTQ
86 ENLINQ
87 VCCD
88 DLOOPQ
90 VCCD
89 DLOOP
93 VCCD
92 CLOOP
94 D15Q
95 D15
96 D14Q
97 D14
98 D13Q
100 VCCD
99 D13
handbook, full pagewidth
91 CLOOPQ
TZA3017HW
VCCD
1
VEE
2
75 VCCA
74 PARERR
D12Q
3
73 PARERRQ
D12
4
72 UI
D11Q
5
71 CLKDIR
D11
6
70 VEE
D10Q
7
69 VCCO
D10
8
D09Q
9
68 VCCD
67 DOUT
D09 10
66 DOUTQ
D08Q 11
65 VCCD
64 VCCD
D08 12
TZA3017HW
VEE 13
63 MD1
62 MD0
D07Q 14
61 VCCD
60 COUT
D07 15
D06Q 16
59 COUTQ
D06 17
D05Q 18
58 VCCD
57 LOL
D05 19
D04Q 20
56 FIFORESET
55 OVERFLOW
D04 21
54 CS(DR0)
D03Q 22
D03 23
53 SDA(DR1)
VEE 24
52 SCL(DR2)
51 VDD
Fig.2 Pin configuration.
2003 May 14
6
VEE 50
VCCD 49
PRSCLO 48
PRSCLOQ 47
MUXR0 46
MUXR1 45
PAREVEN 44
CREF 43
CREFQ 42
VCCD 41
POCLK 40
PARITY 38
POCLKQ 39
PARITYQ 37
VCCD 36
PICLK 35
PICLKQ 34
VCCD 33
D00 32
D00Q 31
D01 30
D02 28
D01Q 29
VEE 26
D02Q 27
VCCD 25
MGW560
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
FUNCTIONAL DESCRIPTION
Table 3
The TZA3017HW converts parallel input data into serial
output data having a bit rate from 30 Mbits/s up to
3.2 Gbits/s. An internal clock synthesizer synchronizes the
internal oscillator to an external reference frequency.
The parallel input data is multiplexed at ratios of 16:1,
10:1, 8:1 or 4:1.
Truth table for selecting bit rate in
pre-programmed mode (pin UI = VEE)
PROTOCOL
BIT RATE
(Mbits/s)
DR2
DR1
DR0
LOW
LOW
LOW
STM1/OC3
155.52
LOW
LOW
HIGH
STM4/OC12
622.08
LOW
HIGH
LOW
STM16/OC48
2488.32
Choice of user interface control
LOW
HIGH
HIGH
STM16 + FEC
2666.06
The TZA3017HW can be controlled either via the I2C-bus
or using programming pins DR0 to DR2. Pin UI selects the
user interface required. I2C-bus control and A-rate
functionality are enabled when pin UI is either open circuit
or connected to VCC. Pre-programmed mode is enabled
when pin UI is connected to VEE; see Table 1.
HIGH
LOW
LOW
GE
1250.00
HIGH
LOW
HIGH
10GE
3125.00
HIGH
HIGH
LOW
Fibre Channel
1062.50
HIGH
HIGH
HIGH
Fibre Channel
2125.00
Table 1
After power-up, the TZA3017HW initiates a Power-On
Reset (POR) sequence to restore the default settings of
the I2C-bus registers, irrespective of the level on pin UI.
The default settings are shown in Table 10.
Truth table for pin UI
UI
MODE
PIN 54
PIN 53
PIN 52
LOW
pre-programmed
DR0
DR1
DR2
HIGH
I2C-bus
CS
SDA
SCL
control
Clock synthesizer
Refer to Fig.3. The clock synthesizer is a fractional N-type
synthesizer which provides the A-rateTM functionality.
It consists of a Voltage Controlled Oscillator (VCO), octave
divider M, main divider N, fractional divider K, reference
divider R, Phase Frequency Detector (PFD), integrated
loop filter, Loss Of Lock (LOL) detection circuit, and a
prescaler output buffer. The internal VCO is phase-locked
to a reference clock signal of typically 19.44 MHz applied
to pins CREF and CREFQ.
In I2C-bus control mode, the chip is configured using
I2C-bus pins SDA and SCL. During I2C-bus read or write
actions, pin CS must be HIGH. When pin CS is LOW, the
programmed configuration remains active, but pins SDA
and SCL are ignored. This allows several TZA3017HWs in
the application with the same I2C-bus address to be
selected separately. The I2C-bus address of the
TZA3017HW is shown in Table 2.
Table 2
The clock synthesizer has a 22-bit fractional N capability
which allows any combination of bit rate and reference
frequency between 18 x R and 21 x R MHz, where R is
the reference division factor. The LSB (bit k[0]) of the
fractional divider, should be set to logic 1 to avoid limit
cycles. These are cycles of less than maximum length that
generate spurs in the frequency spectrum. This leaves
21 bits (k[21:1]) available for programming the fraction,
allowing a resolution frequency of approximately 10 Hz at
a fixed reference frequency.
I2C-bus address of the TZA3017HW
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
1
0
1
0
0
X
The function and content of the I2C-bus registers are
described in Section “I2C-bus registers”. Some functions in
the TZA3017HW can be controlled either by the I2C-bus or
a designated pin. The method required is specified by an
extra bit named I2C<pin name> in the corresponding
I2C-bus register, for example, bit I2CPARITY in
register MUXCNF2. The default is enable by pin.
The clock synthesizer does not require any external
components, allowing easier application use.
To comply with most transmission standards, the
reference frequency must be very accurate with minimum
phase noise in order to synthesize a pure RF clock signal
that complies with the strictest requirements for jitter
generation; see Section “Jitter performance”.
If the application has no I2C-bus control, the IC has to
operate with reduced functionality in pre-programmed
mode. In pre-programmed mode, pins DR0 to DR2 are
standard CMOS inputs that allow the selection of up to
eight pre-programmed bit rates using an external
reference clock frequency of 19.44 MHz; see Table 3.
2003 May 14
7
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
handbook, full pagewidth
REFERENCE
DIVIDER
TZA3017HW
LOL
OCTAVE
DIVIDER
up
CREF
CREFQ
R
PHASEFREQUENCY
DETECTOR
down
VCO
CHARGE-PUMP
AND
LOOP FILTER
M
to
MUX
MAIN
DIVIDER
PRSCLO
PRSCLOQ
N
9
FRACTION
CALCULATOR
9
22
N[8:0] K[21:0]
MGW561
Fig.3 Block diagram of the clock synthesizer.
Programming the reference clock
Table 4
Pre-programmed operation requires a reference clock
frequency of between 18 and 21 MHz connected to
pins CREF and CREFQ. However, to obtain the bit rates in
Table 3, the reference clock frequency must be
19.44 MHz. For SDH/SONET applications, a reference
clock frequency of 19.44 × R MHz is preferred.
I2C-bus control operation allows any one of four possible
reference clock frequency ranges to be selected by
programming reference divider R using bits REFDIV in
I2C-bus register SYNTHCNF (address B6H).
The REFDIV bit settings, reference clock frequency
ranges, and division factor are shown in Table 4.
The reference frequency is always divided internally to the
lowest range of 18 to 21 MHz.
2003 May 14
8
Truth table for bits REFDIV in I2C-bus register
SYNTHCNF
REFDIV
R
DIVISION
FACTOR
SDH/SONET
REFERENCE
FREQUENCY
(MHz)
REFERENCE
FREQUENCY
RANGE
(MHz)
00
1
19.44
18 to 21
01
2
38.88
36 to 42
10
4
77.76
72 to 84
11
8
155.52
144 to 168
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 6
Programming the clock synthesizer
The following dividers are used to program the clock
synthesizer: the main divider N, the fractional divider K
and the octave divider M.
4
28.125 56.25 112.5
3
225
2
450
1
900
0
1800
BIT RATE
(Mbits/s)
OCTAVE
10GE
3125.00
0
2xHDTV
2970.00
0
STM16/OC48 + FEC
2666.06
0
STM16/OC48
2488.32
0
DV-6000
2380.00
0
PROTOCOL
The division factor for M is obtained by first determining in
which octave the desired bit rate belongs as shown in
Figure 4 and Tables 5 and 6.
6
5
handbook, halfpage
Common optical transmission protocols and
corresponding octaves
3600
f (Mbits/s)
Fibre Channel
2125.00
0
HDTV
1485.00
1
D-1 Video
1380.00
1
DV-6010
1300.00
1
Gigabit Ethernet (GE)
1250.00
1
Fibre Channel
1062.50
1
OptiConnect
1062.50
1
ISC
1062.50
1
STM4/OC12
622.08
2
DV-6400
595.00
2
Fibre Channel
425.00
3
OptiConnect
265.63
3
Fibre Channel
212.50
4
ESCON/SBCON
200.00
4
STM1/OC3
155.52
4
FDDI
125.00
4
Fast Ethernet
125.00
4
Fibre Channel
106.25
5
OC1
51.84
6
MGT824
Fig.4 Allocation of octaves for common bit rates
shown on a logarithmic scale.
Table 5
Octave designation and M division factor
LOWEST
BIT RATE
(Mbits/s)
HIGHEST
BIT RATE
(Mbits/s)
OCTAVE
1800
3200
0
1
900
1800
1
2
450
900
2
4
M DIVISION
FACTOR
225
450
3
8
112.5
225
4
16
56.25
112.5
5
32
28.125
56.25
6
64
2003 May 14
Once the octave and M division factor are known, the
division factors for N and K can be calculated for a given
reference frequency using the Flowchart in Fig.5.
9
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
handbook, full pagewidth
TZA3017HW
CALCULATE
N and K
n, k =
bit rate × M × R
f ref
n is integer part
k is fractional part
yes
k=0?
no
NILFRAC = 1
NILFRAC = 0
0.25 < k < 0.75
no
yes
no
k ≤ 0.25 ?
yes
k ≥ 0.75 ?
no
yes
N=2×n
N=2×n
k = k + 0.5
k = k − 0.5
N=2×n−1
N=2×n+1
j = 21
k=k×2
k≥1?
no
yes
Kj = 1
Kj = 0
decimal to binary
conversion of
fractional part
k=k−1
j=j−1
j=0?
no
yes
Kj = 1
Write K j into registers B3H, B4H and B5H
Convert N to binary
and write into registers B1H and B2H
END
MGW570
Fig.5 Flowchart for calculating N and K for the required bit rate.
2003 May 14
10
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
The following examples refer to the flowchart in Fig.5.
Example 1: An SDH or SONET link has a bit rate of 2488.32 Mbits/s (STM16/OC48) that corresponds to octave 0 and
an M division factor of 1. If the reference frequency fref at pins CREF and CREFQ is 77.76 MHz, the division factor R is
required to be 4. The initial values for integer n and fractional part k are calculated using the equation:
2488.32 Mbits × 1 × 4
bit rate × M × R
n.k = ---------------------------------------- = --------------------------------------------------------- = 128
77.76 MHz
f ref
In this example, n = 128 and k = 0. Since k is 0, fractional functionality is not required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 1; see Table 19. N = n × 2 = 256 with no further correction required. The resulting
values of R = 4, M = 1 and N = 256 are set by I2C-bus registers SYNTHCNF (Table 22), DIVCNF (Table 16), MAINDIV1
(Table 17) and MAINDIV0 (Table 18).
Example 2: An SDH or SONET link has a bit rate of 2666.057143 Mbits/s (15/14 × 2488.32 Mbits/s) (STM16/OC48 link
with FEC) that corresponds to octave 0 and an M division factor of 1. If fref at pins CREF and CREFQ is 38.88 MHz,
the division factor R is required to be 2. The values for n and k are calculated as follows:
bit rate × M × R
2666.05714283 Mbits × 1 × 2
n.k = ---------------------------------------- = ----------------------------------------------------------------------------- = 137.1428571
f ref
38.88 MHz
In this example, n = 137 and k = 0.1428571. Fractional functionality is required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 0. Since k is less than 0.25, k is corrected to k = k + 0.5 = 0.6428571, and N is
corrected to N = n × 2 − 1 = 273. The resulting values of R = 2, M = 1, N = 273 and K = 10 1001 0010 0100 1001 0011
are set by I2C-bus registers SYNTHCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18),
FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21). The FEC bit rate is usually rounded up to
2666.06 Mbits/s, which actually gives a different value for k than in this example.
Example 3: A Fibre Channel link has a bit rate of 1062.50 Mbits/s that corresponds to octave 1 and an M division factor
of 2. If fref at pins CREF and CREFQ is 19.44 MHz, the division factor R is required to be 1. The values for n and k are
1062.50 Mbits × 2 × 1
bit rate × M × R
calculated as follows: n.k = ---------------------------------------- = --------------------------------------------------------- = 109.3106996
19.44 MHz
f ref
In this example, n = 109 and k = 0.3107. Fractional functionality is required, so bit NILFRAC in I2C-bus register FRACN2
should be set to logic 0. Since k is greater than 0.25 and less than 0.75, k does not need to be corrected. N is corrected
to N = n × 2 = 218. The resulting values of R = 1, M = 2, N = 218 and K = 01 0011 1110 0010 1000 0001 are set by
I2C-bus registers SYNTHCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18), FRACN2
(Table 19), FRACN1 (Table 20) and FRACN0 (Table 21).
Example 4: A non standard transmission link has a bit rate of 3012 Mbits/s that corresponds to octave 0 and an
M division factor of 1. If fref at pins CREF and CREFQ is 20.50 MHz, the division factor R is required to be 1. The values
bit rate × M × R
3012 Mbits × 1 × 1
for n and k are calculated as follows: n.k = ---------------------------------------- = ------------------------------------------------ = 146.9268293
f ref
20.50 MHz
In this example, n = 146 and k = 0.9268293. Fractional functionality is required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 0. Since k is greater than 0.75, k is corrected to k = k − 0.5 = 0.4268293, and N
is corrected to N = n × 2 + 1 = 293. The resulting values of R = 1, M = 1, N = 293 and K = 01 1011 0101 0001 0010 1011
are set by I2C-bus registers SYNTHCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18),
FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21).
If the I2C-bus is not used, the clock synthesizer can be set up for the eight pre-programmed bit rates shown in Table 3,
by pins DR0, DR1 and DR2 using an external reference clock frequency of 19.44 MHz.
2003 May 14
11
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
matches the source impedance Rsource; see Fig.6.
The PSRR can be improved by AC coupling the reference
frequency source to inputs CREF and CREFQ. Any low
frequency noise injected from the fref power supply will be
attenuated by the resulting high-pass filter. The low cut-off
frequency of the AC coupling must be lower than the
reference frequency, otherwise the reference signal will be
attenuated and the signal to noise ratio will be made
worse. The value of coupling capacitor C is calculated
1
using the formula: C > ----------------------------------2πR source f ref
Prescaler outputs
The frequency of prescaler outputs PRSCLO and
PRSCLOQ is the VCO frequency divided by a ratio of N.K.
If the synthesizer is in-lock, the frequency of the prescaler
output is equal to the reference frequency at CREF and
CREFQ divided by R. This provides an accurate reference
that can be used by other phase locked loops in the
application. If required, the polarity of the prescaler
outputs can be inverted by setting bit PRSCLOINV in
I2C-bus register IOCNF2. If no prescaler information is
required, its output can be disabled by setting
bit PRSCLOEN to logic 0 in the same register. In addition,
the prescaler output can be set for type of output,
termination mode and signal amplitude. These parameter
settings also apply to the parallel clock outputs POCLK
and POCLKQ and parity error outputs PARERR and
PARERRQ. For programming details; see Section
“Configuring the parallel interface”.
VCCD
handbook, halfpage
50 Ω
50 Ω
CREF
Loss of Lock (LOL)
C
CREFQ C
During normal operation, pin LOL should be LOW to
indicate that the clock synthesizer is in-lock and that the
output frequency corresponds to the programmed value.
If pin LOL goes HIGH, phase and/or frequency lock is lost,
and the output frequency may deviate from the
programmed value. The LOL function is also available
using I2C-bus registers INTERRUPT and STATUS; see
Sections “Interrupt register” and “Status register”.
If bit LOL in register INTERRUPT is not masked, a loss of
lock condition will generate an interrupt signal at pin INT.
Bit LOL is masked by default; see Section “Interrupt
generation”.
Rsource
Rsource
fref
on-chip
Fig.6
off-chip
MDB060
Reference input with single-ended clock
source.
Multiplexer
Jitter performance
The multiplexer comprises a high-speed input register, a
4-bit deep First In First Out (FIFO) elastic buffer, a parity
check circuit and a multiplexing tree.
The clock synthesizer is optimized for minimum jitter
generation. For all SDH/SONET bit rates, the generated
jitter complies with ITU-T standard G.958 using a pure
reference clock. To ensure negligible loss of performance,
the reference signal should have a single sideband phase
noise of better than −140 dBc/Hz, at frequencies of more
than 12 kHz from the carrier. If reference divider R is used,
this negative value is allowed to increase at approximately
20 × log (R).
Parallel data bus clocking schemes
The TZA3017HW supports both co-directional and
contra-directional clocking schemes for the parallel data
bus; see Figs 7 and 8. The clocking scheme is selected by
pin CLKDIR or I2C-bus bit CLKDIR in I2C-bus register
MUXCNF1 (address A1H). Co-directional clocking is the
default setting, and is selected when pin CLKDIR is HIGH
or when I2C-bus bit CLKDIR is set to logic 1.
With co-directional clocking selected, the incoming clock is
applied to pins PICLK and PICLKQ and the input data is
applied to pins D00 and D00Q to D15 and D15Q.
A parallel output clock is also available, if required, at
pins POCLK and POCLKQ, and can be disabled by
bit POCLKEN in I2C-bus register MUXCNF1.
Reference input
For optimum jitter performance and Power Supply
Rejection Ratio (PSRR), the sensitive reference input
should be driven differentially. If the reference frequency
source (fref) is single-ended, the unused CREF or CREFQ
input should be terminated with an impedance which
2003 May 14
VCC
12
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
When contra-directional clocking is selected, any incoming
clock at pins PICLK and PICLKQ is not used.
In contra-directional clocking mode, the incoming data on
the parallel data bus is sampled by the internally generated
parallel output clock. In this mode, the parallel data source
must be clocked using the parallel output clock signal at
pins POCLK and POCLKQ. To avoid timing problems, the
clock signal at pins POCLK and POCLKQ can be phase
shifted with respect to the internal clock in four 90 degree
steps, controlled by bits POCLKINV and POPHASE in
I2C-bus register MUXCNF1 (address A1H); see Table 7.
handbook, full pagewidth
Table 7
FRAMER
Truth table for bits POCLKINV and POPHASE
in I2C-bus register MUXCNF1
POCLKINV
POPHASE
0
0
0°
0
1
90°
1
0
180°
1
1
270°
TZA3017HW
PARITY
TX_PARITY
PARITYQ
16
TX_DATA
16
D00 to D15
D00Q to D15Q
PICLK
TX_CLK
PICLKQ
POCLK
TX_CLK_SRC
POCLKQ
FIFORESET CREF
MGW565
system
clock
Fig.7 Co-directional clocking.
2003 May 14
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PHASE SHIFT
Philips Semiconductors
Product specification
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A-rate fibre optic transmitter
handbook, full pagewidth
TZA3017HW
FRAMER
TZA3017HW
PARITY
TX_PARITY
PARITYQ
16
TX_DATA
16
D00 to D15
D00Q to D15Q
POCLK
TX_CLK_SRC
POCLKQ
FIFORESET CREF
MGW566
system
clock
Fig.8 Contra-directional clocking.
FIFO
whenever there has been a Loss Of Lock condition, or
whenever the bit rate is changed.
In the co-directional clocking scheme, the FIFO input
register samples the incoming parallel data on the rising
edge of the clock signal at pins PICLK and PICLKQ.
Data is retrieved from the FIFO by an internal clock,
derived from the multiplexing tree clock generator.
This provides a high tolerance to jitter, or clock skew,
at inputs on the parallel interface; the FIFO can
compensate for brief phase deviations, or clock skew,
of up to plus or minus 1 unit interval. Large phase
deviations will most likely cause the FIFO to either
overflow or underflow, and is indicated by bit OVERFLOW
in both I2C-bus registers INTERRUPT and STATUS; see
Sections “Interrupt register” and “Status register”. A FIFO
overflow is also indicated by a HIGH level at
pin OVERFLOW. If bit OVERFLOW in
register INTERRUPT is not masked, a FIFO overflow or
underflow condition will generate an interrupt signal at
pin INT; see Section “Interrupt generation”.
The FIFORESET signal is re-timed by the internal clock
generator signal. The FIFO will initialize two clock cycles
after FIFORESET goes HIGH and is operational two clock
cycles after FIFORESET goes LOW. The FIFO can be
initialized automatically when an overflow occurs by
connecting pin OVERFLOW to pin FIFORESET.
Adjustable multiplexing ratio
For optimum layout connectivity, the physical positions of
parallel data bus pins D00 and D00Q to D15 and D15Q on
the chip are located either side of pin VEE (pin 13).
The number of parallel data bus inputs that are used
depends on the multiplexing ratio selected by pins MUXR0
and MUXR1 or by bits MUXR in I2C-bus
register MUXCNF1 (address A1H). Any unused parallel
data bus inputs are disabled. The configuration settings
and active inputs for each multiplexing ratio are shown in
Table 8.
The overflow interrupt exists until the FIFO is reset by a
HIGH level on pin FIFORESET or by setting
bits FIFORESET and I2CFIFORESET in I2C-bus register
MUXCNF0 (address A2H). FIFORESET also initializes the
FIFO. For optimum performance, the FIFO should be reset
2003 May 14
In I2C-bus control mode, the default multiplexing ratio
is 16:1. For multiplexing ratios 16:1, 8:1 and 4:1, the MSB
is transmitted first. For multiplexing ratio 10:1, the LSB is
transmitted first.
14
Philips Semiconductors
Product specification
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TZA3017HW
To allow optimum layout connectivity, the pin designations of the parallel data bus bits can be reversed so that the default
designated pin for the MSB is exchanged with the default designated pin for the LSB. This is implemented by
bit BUSSWAP in I2C-bus register MUXCNF2 (address A0H).
The highest supported speed for the parallel data bus is 400 Mbits/s. Therefore a multiplexing ratio of 4:1 will support bit
rates of up to 1.6 Gbits/s.
Table 8
Setting multiplexing ratio
PIN MUXR1
PIN MUXR0
BITS MUX
(REG. MUXCNF1)
MULTIPLEXING
RATIO
ACTIVE INPUTS
LSB to MSB
LOW
LOW
00
4:1
D06 to D09
LOW
HIGH
01
8:1
D04 to D11
HIGH
LOW
10
10:1
D03 to D12
HIGH
HIGH
11
16:1
D00 to D15
Parity checking
The parity checking function verifies the integrity of the incoming data on the parallel data bus. The calculated parity is
compared to the parity expected at pins PARITY and PARITYQ. If these levels do not match, a parity error has occurred
and pin PARERR goes HIGH during the next parallel clock period at pins PICLK and PICLKQ; (see Fig.9).
The calculated parity can be configured to be either odd or even by pin PAREVEN or by bit PARITY in I2C-bus
register MUXCNF2 (address A0H). Odd parity is configured by either a LOW level at pin PAREVEN or setting
bit PARITY. The default setting for bit PARITY is even parity (logic 0).
handbook, full pagewidth
PICLK
D00-D15
PARITY
PARERR
PARITY
ERROR
MDB063
Fig.9 Parity timing.
2003 May 14
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TZA3017HW
In I2C-bus register MUXCNF2 (address A0H), setting
bit PDINV inverts the polarity of the parallel data.
Setting bit PICLKINV inverts the co-directional input clock
on pins PICLK and PICLKQ so that the clock edge is
shifted by half a clock cycle, changing the rising edge to a
falling edge. This function can be used to resolve a parallel
data bus timing problem.
Configuring the parallel interface
There are several options for configuring the parallel
interface which comprises the parallel data bus and
associated inputs and outputs. The options for parallel
clock outputs POCLK and POCLKQ, parity error outputs
PARERR and PARERRQ and prescaler outputs PRSCLO
and PRSCLOQ are: output driver type, termination mode
and output amplitude. I2C-bus register IOCNF2,
bit MFOUTMODE selects either the CML or LVPECL
output driver. The default is LVPECL. Bit MFOUTTERM
sets the output termination mode to either standard
LVPECL or floating termination, or in CML mode, to either
DC or AC-coupled. In all cases, bits MFS adjust the
amplitude. The default output amplitude is 850 mV (p-p),
single-ended.
Rail-to-rail parallel data and clock inputs
The differential parallel data, parity and clock inputs,
D00 to D15, D00Q to D15Q, PARITY, PARITYQ, PICLK,
and PICLKQ can handle input swings from 100 mV,
single-ended, to a maximum of 1000 mV. These rail-to-rail
inputs can also accept any absolute value between VEE
and VCC.
To keep the number of external components required to a
minimum, most of the common standards: LVPECL, CML
and LVDS are terminated internally; see Fig.10.
The signal polarity and selective enabling or disabling of
POCLK, POCLKQ, PRSCLO and PRSCLOQ can also be
configured. These options are set in I2C-bus
registers MUXCNF1 (address A1H) and IOCNF2
(address C8H).
VCCD
handbook, full pagewidth
VCCD
VCCD
2V
D
D
D
50 Ω
50 Ω
50 Ω
DQ
VEE
Floating and LVDS termination
50 Ω
50 Ω
50 Ω
DQ
DQ
VEE
VEE
CML termination
LVPECL termination
MDB062
Fig.10 Rail-to-rail input termination configurations.
2003 May 14
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
The default pin designations for RF output data and clock
are exchanged by setting bit CDOUTSWAP in I2C-bus
register IOCNF1 so that signals at pins COUT and
COUTQ are treated as data and signals at pins DOUT and
DOUTQ are treated as clock.
The termination mode is determined by pins MD0
and MD1; see Table 9.
Table 9
Input termination mode selection
INPUT
MODE
PIN MD1
PIN MD0
TERMINATION
0
0
floating
100 Ω differential
0
1
LVDS
100 Ω differential
(hysteresis on)
1
0
CML
50 Ω to VCC
1
1
LVPECL
50 Ω to VCC − 2 V
The default pin designations for Loop mode output data
and clock are exchanged by setting bit CDLOOPSWAP in
I2C-bus register IOCNF0 (address CBH) so that loop
mode output data is present at pins CLOOP and CLOOPQ
and loop mode clock output is present at pins DLOOP and
DLOOPQ.
Outputs DOUT and DOUTQ and COUT and COUTQ can
be independently disabled by bits DOUTENA and
COUTENA in I2C-bus register IOCNF1 (address CAH).
The LVDS mode has a differential hysteresis of 30 mV
implemented by default. Setting bit PIHYST in I2C-bus
register MUXCNF0 (address A2H) activates hysteresis for
all input modes.
The amplitude of the RF serial output signals in CML drive
mode, is adjustable (in 16 steps) between 70 mV (p-p) and
1100 mV (p-p), single-ended, controlled by bits RFS in
I2C-bus register IOCNF0 (address CBH). The default
amplitude is 280 mV (p-p), single-ended. The RF serial
outputs can be either DC or AC-coupled, terminated by
bit RFOUTTERM in I2C-bus register IOCNF0
(address CBH). The default termination is DC-coupled.
Loop mode I/Os
In line loopback mode, the internal data and clock routing
switch selects serial data and clock signals from
inputs DIN, DINQ, CIN, and CINQ instead of from the
output of the multiplexer. Line loopback mode is activated
by a LOW level on pin ENLINQ. Line loopback mode is
also selected by setting bit ENLIN in I2C-bus register
MUXCNF2 (address A0H).
CMOS control inputs
CMOS control inputs UI, MUXR0, MUXR1, PAREVEN,
CLKDIR, ENLOUTQ, ENLINQ, MD0, MD1, FIFORESET
and CS(DR0) have an internal pull-up resistor so that
these pins go HIGH when open circuit, and only go LOW
when deliberately forced. This is also true for pins DR1
and DR2 in pre-programmed mode (pin UI is LOW).
In I2C-bus control mode (pin UI is HIGH), pins SCL
and SDA comply with the I2C-bus interface standard.
In diagnostic loopback mode, the synthesized serial data
and clock signals are available at loop mode output
pins DLOOP and DLOOPQ, and CLOOP and CLOOPQ
and at output pins DOUT and DOUTQ and COUT and
COUTQ. Diagnostic loopback mode is activated by
making pin ENLOUTQ LOW. Diagnostic loopback mode is
also selected by setting bit ENLOUT in I2C-bus
register MUXCNF2 (address A0H).
Power supply connections
Four separate supply domains (VDD, VCCD, VCCO and
VCCA) provide isolation between the various functional
blocks. Each supply domain should be connected to a
common VCC using a separate filter. All supply pins,
including the exposed die pad, must be connected.
The die pad connection to ground must have the lowest
possible inductance. Since the die pad is also used as the
main ground return of the chip, this connection must also
have a low DC impedance. The voltage supply levels
should be in accordance with the values specified in
Chapters “Characteristics” and “Limiting values”.
Configuring the RF I/Os
The polarity of specific RF serial data and clock I/O signals
can be inverted using I2C-bus registers IOCNF0
(address CBH) and IOCNF1 (address CAH).
To allow easier connection to other ICs, the pin
designations for input data can be exchanged with the pin
designations for input clock. The pin designations for
output data and output clock can also be exchanged.
The default pin designations for loop mode input data and
clock are exchanged by setting bit CDINSWAP in I2C-bus
register IOCNF1 so that signals at pins CIN and CINQ are
treated as data and signals at pins DIN and DINQ are
treated as clock.
2003 May 14
All external components should be surface mounted, with
a preferable size of 0603 or smaller. The components
must be mounted as close to the IC as possible.
17
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
The active output level used is set by bit INTPOL in
I2C-bus register INTMASK. The default is an active
LOW level. Bit INTOUT sets the output mode at pin INT to
either open-drain or to standard CMOS. The default is
open-drain. An active LOW output in open-drain mode
allows several receivers to be connected together,
and requires only one 3.3 kΩ pull-up resistor.
Interrupt register
The following events are recorded by setting the
appropriate bit(s) in I2C-bus register INTERRUPT
(address 00H):
• Loss of lock
• High junction temperature
• FIFO overflow or underflow.
CHARACTERISTICS OF THE I2C-BUS
When register INTERRUPT is polled by an I2C-bus read
action, any set bits are reset. If a condition is still active,
the corresponding bit remains set.
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
Status register
The current status of the conditions that are recorded by
register INTERRUPT are indicated by setting the
appropriate bit(s) in I2C-bus register STATUS
(address 01H). A bit is set only for the period that the
condition is active and resets when the condition clears.
Register STATUS is polled by an I2C-bus read action.
Bit transfer
Refer to Fig.11. One data bit is transferred during each
clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse as changes in
the data line at this time will be interpreted as control
signals.
Interrupt generation
An interrupt is generated if an interrupt condition sets a bit
in I2C-bus register INTERRUPT (address 00H) and if the
bit is not masked by I2C-bus register INTMASK
(address CCH). Only the high junction temperature
interrupt bit is not masked by default. A generated interrupt
is indicated by an active logic level at pin INT.
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig.11 Bit transfer.
2003 May 14
18
MBC621
Philips Semiconductors
Product specification
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A-rate fibre optic transmitter
TZA3017HW
Start and stop conditions
Refer to Fig.12. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the stop condition (P).
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.12 Definition of start and stop conditions.
System configuration
Refer to Fig.13. A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’.
The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
MBA605
Fig.13 System configuration.
2003 May 14
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Philips Semiconductors
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30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Acknowledge
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end-of-data to the transmitter by not generating
an acknowledge on the last byte that has been clocked
out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition; see Fig.17.
Refer to Fig.14. Only one data byte is transferred between
the start and stop conditions during a write from the
transmitter to the receiver. Each byte of eight bits is
followed by an acknowledge bit. The acknowledge bit is a
HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed
must generate an acknowledge after the reception of each
byte. Also a master receiver must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter.
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.14 Acknowledgment on the I2C-bus.
2003 May 14
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Product specification
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A-rate fibre optic transmitter
TZA3017HW
I2C-BUS PROTOCOL
Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The address byte is
sent after the start condition.
The master transmitter/receiver either reads from the read-registers or writes to the write-registers. It is not possible to
read from and write to the same register. Figure 15 shows how the slave and register address bytes are defined.
handbook, full pagewidth
MSB
LSB
MSB
R/W
1
LSB
Slave address
Register address
MDB070
Fig.15 Slave and register addresses.
Read/Write protocols
The protocol for writing to a single register is shown in Fig.16. The transmitter sends the address of the slave device,
waits for an acknowledge from the slave, sends register address, waits for an acknowledge from the slave, sends data
byte, waits for an acknowledge from the slave, followed by a stop condition.
acknowledge
from slave
handbook, full pagewidth
acknowledge
from slave
R/W MSB
S
SLAVE
ADDRESS
0 A 1
acknowledge
from slave
MSB
REGISTER
ADDRESS
A
LSB
DATA
A
P
one byte transferred
MDB386
Fig.16 Write protocol.
2003 May 14
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Product specification
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A-rate fibre optic transmitter
TZA3017HW
The protocol for reading one or more registers is shown in Fig.17. The receiver sends the address of the slave device,
waits for an acknowledge from the slave, receives data byte(s) from slave (the TZA3017AHW starts sending data after
asserting an acknowledge), after receiving the data, the receiver sends an acknowledge or, if finished, a
not-acknowledge, followed by a stop condition.
handbook, full pagewidth
acknowledge
from master (1)
acknowledge
from slave
R/W
S
SLAVE
ADDRESS
1 A
MSB
acknowledge
from master (1)
LSB
DATA
acknowledge
from master (1)
MSB
A
first byte
A
LSB
DATA
A
P
last byte
MDB387
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave.
Fig.17 Read protocol.
I2C-bus registers
The I2C-bus registers are accessed in I2C-bus control mode by setting pin UI HIGH or leaving pin UI open circuit.
Address and read/write data are transferred serially via pin SDA and clocked via pin SCL when pin CS (chip select) is
HIGH. The I2C-bus registers are listed in Table 10.
2003 May 14
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Philips Semiconductors
Product specification
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A-rate fibre optic transmitter
TZA3017HW
Table 10 I2C-bus registers
ADDRESS
(HEX)(1)
NAME
DEFAULT
VALUE
FUNCTION
READ/
WRITE
00
INTERRUPT
Interrupt register; see Table 11
−
R
01
STATUS
Status register; see Table 12
−
R
A0
MUXCNF2
Multiplexer configuration register 2; see Table 13
0000 0000
W
A1
MUXCNF1
Multiplexer configuration register 1; see Table 14
0110 1001
W
A2
MUXCNF0
Multiplexer configuration register 0; see Table 15
0001 1000
W
B0
DIVCNF
Octave and loop mode configuration register; see Table 16
0000 0000
W
B1
MAINDIV1
Main divider division factor N; most significant byte; range
128 to 511; see Table 17
0000 0001
W
B2
MAINDIV0
Main divider division factor N; least significant byte; see Table 18 0000 0000
W
B3
FRACN2
Fractional divider division factor K; see Table 19
1000 0000
W
B4
FRACN1
Fractional divider division factor K; see Table 20
0000 0000
W
B5
FRACN0
Fractional divider division factor K; see Table 21
0000 0000
W
B6
SYNTHCNF
Clock synthesizer configuration register; see Table 22
0000 0000
W
C8
IOCNF2
Parallel interface output configuration register 2; see Table 23
0010 1100
W
CA
IOCNF1
RF serial I/O configuration register 1; see Table 24
1100 0000
W
CB
IOCNF0
RF serial output configuration register 0; see Table 25
0000 0011
W
CC
INTMASK
Interrupt masking register; see Table 26
0101 0000
W
FD
MUXTIMING
Multiplexer timing register; see Table 27
0000 1000
W
Note
1. Addresses not shown must not be accessed.
Table 11 Register INTERRUPT (address 00H)
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
clock synthesizer Loss of Lock (LOL)
X
X
X
1
out of lock (loss of lock condition)
0
in lock
0
0
0
0
2003 May 14
TALARM
junction temperature ≥ 130 °C
junction temperature < 130 °C
FIFO overflow or underflow
1
LOL
reserved
high junction temperature
1
NAME
overflow or underflow
normal operation
reserved
23
OVERFLOW
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 12 Register STATUS (address 01H)
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
clock synthesizer Loss of Lock (LOL)
X
X
X
1
out of lock (loss of lock condition)
0
in lock
1
junction temperature ≥ 130 °C
0
junction temperature < 130 °C
FIFO overflow or underflow
0
2003 May 14
LOL
reserved
high junction temperature
0
NAME
1
overflow or underflow
0
normal operation
reserved
24
TALARM
OVERFLOW
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 13 Register MUXCNF2 (address A0H); default value 00H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
parallel data bus bit designations
1
D00 = MSB, D15 = LSB (reversed)
0
D15 = MSB, D00 = LSB (normal)
parity checking
1
odd parity
0
even parity
parity programming
I2C-bus
1
via
0
via pin PAREVEN
inverted
0
normal
parallel data input polarity
1
inverted
0
normal
enable/disable loop mode inputs
1
enabled
0
disabled
enable/disable loop mode outputs
1
1
via
0
I2C-bus
interface
via pins ENLINQ and/or ENLOUTQ
2003 May 14
I2CPARITY
PICLKINV
PDINV
ENLIN
ENLOUT
disabled
loop mode control
0
PARITY
enabled
0
0
BUSSWAP
interface
parallel clock input polarity
1
NAME
0
0
0
0
0
0
default value
25
I2CLOOPMODE
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 14 Register MUXCNF1 (address A1H); default value 69H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
parallel clock output enable
1
enabled
0
disabled
parallel clock output phase
1
90° phase shift
0
0° phase shift
parallel clock output polarity
1
inverted
0
normal
parallel clock direction
1
co-directional
0
contra-directional
parallel clock direction programming
I2C-bus
1
via
0
via pin CLKDIR
1
16:1
1
0
10:1
0
1
8:1
0
0
4:1
multiplexing ratio programming
1
via I2C-bus interface
0
via pins MUXR0 and MUXR1
0
1
2003 May 14
1
0
1
0
0
1
default value
26
POCLKEN
POPHASE
POCLKINV
CLKDIR
I2CLKDIR
interface
multiplexing ratio
1
NAME
MUXR
I2CMUXR
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 15 Register MUXCNF0 (address A2H); default value 18H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
FIFO reset
FIFORESET
1
reset
0
normal mode
FIFO reset programming
I2C-bus
1
via
0
via pin FIFORESET
I2CFIFORESET
interface
parallel input hysteresis
0
0
0
1
1
0
0
0
1
1
NAME
1
all input modes
0
LVDS mode only
PIHYST
reserved
0
0
0
default value
Table 16 Register DIVCNF (address B0H); default value 00H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
octave divider division factor M, octave
selection
0
0
0
0
0
0
0
0
0
0
0
0
0
M = 1, octave number 0
0
0
1
M = 2, octave number 1
0
1
0
M = 4, octave number 2
0
1
1
M = 8, octave number 3
1
0
0
M = 16, octave number 4
1
0
1
M = 32, octave number 5
1
1
0
M = 64, octave number 6
0
0
0
NAME
DIV_M
reserved
default value
Table 17 Register MAINDIV1 (address B1H); default value 01H
BIT
PARAMETER
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
N8
0
0
0
0
0
0
0
1
DESCRIPTION
main divider division factor N; N8 = MSB
NAME
DIV_N
default value
Table 18 Register MAINDIV0 (address B2H); default value 00H
BIT
PARAMETER
7
6
5
4
3
2
1
0
N7
N6
N5
N4
N3
N2
N1
N0
0
0
0
0
0
0
0
0
2003 May 14
DESCRIPTION
main divider division factor N; N0 = LSB
default value
27
NAME
DIV_N
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 19 Register FRACN2 (address B3H); default value 80H
BIT
7
PARAMETER
6
5
4
3
2
1
X
K21
K20
K19
K18
K17
0
DESCRIPTION
K16 fractional divider division value K;
K21 = MSB
NILFRAC control bit
1
DIV_K
NILFRAC
no fractional N functionality
0
1
NAME
fractional N functionality
0
0
0
0
0
0
0
default value
Table 20 Register FRACN1 (address B4H); default value 00H
BIT
PARAMETER
7
6
5
4
3
2
1
0
K15
K14
K13
K12
K11
K10
K9
K8
0
0
0
0
0
0
0
0
DESCRIPTION
fractional divider division value K
NAME
DIV_K
default value
Table 21 Register FRACN0 (address B5H); default value 00H
BIT
PARAMETER
7
6
5
4
3
2
1
0
K7
K6
K5
K4
K3
K2
K1
K0
0
0
0
0
0
0
0
0
DESCRIPTION
fractional divider division value K;
K0 = LSB
NAME
DIV_K
default value
Table 22 Register SYNTHCNF (address B6H); default value 00H
BIT
7
6
5
PARAMETER
4
3
2
1
0
0
0
0
0
0
DESCRIPTION
reserved
clock synthesizer manual initialization
1
toggle to initialize synthesizer
0
normal operation; auto initialize
reference divider division factor R;
reference frequency
1
1
R = 8; 155.52 MHz
1
0
R = 4; 77.76 MHz
0
1
R = 2; 38.88 MHz
0
0
0
0
2003 May 14
R = 1; 19.44 MHz
0
0
0
0
0
0
NAME
default value
28
INITSYNTH
REFDIV
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 23 Register IOCNF2 (address C8H); default value 2CH
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
0
0
0
0
minimum: 60 mV (p-p)
1
1
0
0
default: 850 mV (p-p)
1
1
1
1
maximum: 1000 mV (p-p)
parallel output signal amplitude
prescaler output polarity
1
inverted
0
normal
prescaler output enable
1
enabled
0
disabled
parallel output termination
1
LVPECL mode: floating;
CML mode: AC-coupled
0
LVPECL mode: standard;
CML mode: DC-coupled
parallel output mode
1
Current Mode Logic (CML)
0
Low Voltage Positive Emitter Coupled
Logic (LVPECL)
0
0
2003 May 14
1
0
1
1
0
0
default value
29
NAME
MFS
PRSCLOINV
PRSCLOEN
MFOUTTERM
MFOUTMODE
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 24 Register IOCNF1 (address CAH); default value C0H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
loop mode clock input polarity
1
inverted
0
normal
loop mode data input polarity
1
inverted
0
normal
loop mode clock and data inputs swap
1
clock and data input pairs swapped
0
normal
clock output polarity
1
inverted
0
normal
data output polarity
1
inverted
0
normal
clock and data outputs swap
1
clock and data output pairs swapped
0
normal
serial clock output enable
1
1
enabled
0
disabled
2003 May 14
DININV
CDINSWAP
COUTINV
DOUTINV
CDOUTSWAP
COUTENA
disabled
serial data output enable
1
CININV
enabled
0
1
NAME
0
0
0
0
0
0
default value
30
DOUTENA
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 25 Register IOCNF0 (address CBH); default value 03H
BIT
7
6
5
4
PARAMETER
3
2
1
0
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
DESCRIPTION
RF serial output signal amplitude
minimum: 70 mV (p-p)
default: 280 mV (p-p)
maximum: 1100 mV (p-p)
loop mode clock output polarity
inverted
normal
loop mode data output polarity
inverted
normal
RF serial output termination
AC-coupled
DC-coupled
loop mode clock and data outputs swap
clock and data output pairs swapped
normal
default value
NAME
RFS
CLOOPINV
DLOOPINV
RFOUTTERM
CDLOOPSWAP
Table 26 Register INTMASK (address CCH); default value 50H
BIT
7
6
5
4
PARAMETER
3
2
1
0
1
0
0
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
0
0
DESCRIPTION
mask LOL interrupt bit
not masked
masked; note 1
reserved
mask high junction temperature interrupt
bit
not masked
masked; note 1
mask OVERFLOW interrupt bit
not masked
masked; note 1
pin INT output polarity
inverted; active LOW output
normal; active HIGH output
pin INT output mode
standard CMOS output
open-drain output
default value
Note
1. Signal is not processed by interrupt controller.
2003 May 14
31
NAME
MLOL
MTALARM
MOVERFLOW
INTPOL
INTOUT
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Table 27 Register MUXTIMING (address FDH); default value 80H
BIT
PARAMETER
7
6
5
4
3
2
1
0
DESCRIPTION
0
0
0
0
0
1
0
0
up to 3.2 Gbits/s
0
0
0
0
1
0
0
0
up to 2.7 Gbits/s
0
0
0
0
1
0
0
0
multiplexing ratio 10:1 maximum bit rate
MUX_TIMING
default value
• Co-directional or contra-directional clocking scheme:
pin CLKDIR
TZA3017HW FEATURES IN PRE-PROGRAMMED
MODE
• Loop mode serial input and output configuration:
pins ENLINQ and ENLOUTQ
Although the TZA3017HW is primarily intended to be
programmed via the I2C-bus, many of the TZA3017HW
functions can be accessed either via the I2C-bus in I2C-bus
control mode (pin UI HIGH), or via the external chip pins in
pre-programmed mode (pin UI LOW). The TZA3017HW
functions that are accessible in pre-programmed mode
and their control pins are as follows:
• Even/odd parity checking: pin PAREVEN
• LVPECL outputs on parallel interface with 800 mV (p-p),
single-ended signal, (DC-coupled termination to
VCC − 2 V)
• CML serial RF outputs with typical 280 mV (p-p),
single-ended signal, (DC-coupled load)
• Choice of four pre-programmed SDH/SONET bit rates:
STM1/OC3, STM4/OC12, STM16/OC48,
STM16/OC48 + FEC; pins DR0 to DR2
• Loss Of Lock indication (LOL)
• FIFO overflow indication
• Choice of four pre-programmed bit rates: Fibre Channel,
double Fibre Channel, Gigabit Ethernet, 10-Gigabit
Ethernet; pins DR0 to DR2
• FIFO reset
• High junction temperature indication (pin INT;
open-drain)
• Choice of four multiplexing ratios: 16:1, 10:1, 8:1 or 4:1:
pins MUXR1 and MUXR0
2003 May 14
NAME
• 18 to 21 MHz reference frequency supported.
32
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MIN.
In
UNIT
−0.5
+3.6
V
D00 to D15, D00Q to D15Q, PICLK, PICLKQ, PARITY, and
PARITYQ
VCC − 0.5
VCC + 0.5
V
POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO, and
PRSCLOQ
VCC − 2.5
VCC + 0.5
V
UI, CS, SDA, SCL, MUXR0, MUXR1, CLKDIR, PAREVEN,
FIFORESET, MD0, MD1, ENLOUTQ and ENLINQ
−0.5
VCC + 0.5
V
LOL and OVERFLOW
−0.5
VCC + 0.5
V
INT
−0.5
VCC + 0.5
V
D00 to D15, D00Q to D15Q, PICLK, PICLKQ, PARITY, and
PARITYQ
−25
+25
mA
CREF, CREFQ, CIN, CINQ, DIN and DINQ
−20
+20
mA
INT
−2
+2
mA
−40
+85
°C
+125
°C
+150
°C
VCCD, VCCA, supply voltages
VCCO,VDD
Vn
MAX.
DC voltage on pins
input current on pins
Tamb
ambient temperature
Tj
junction temperature
Tstg
storage temperature
−65
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
notes 1 and 2
VALUE
UNIT
16
K/W
Notes
1. In compliance with JEDEC standards JESD51-5 and JESD51-7.
2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and
fourth layer in the PCB.
2003 May 14
33
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
CHARACTERISTICS
VCC = 3.14 to 3.47 V; Tamb = −40 to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings
(note 1); all voltages are referenced to ground; positive currents flow into the device unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supplies
ICCA
analog supply current
ICCD
digital supply current
IDD
digital supply current
ICCO
oscillator supply current
ICC(tot)
total supply current
Ptot
total power dissipation
0.5
1.2
2.4
mA
notes 1 and 2
170
215
270
mA
notes 2 and 3
285
345
430
mA
0
2
4
mA
20
31
41
mA
notes 1 and 2
190
250
318
mA
notes 2 and 3
305
380
478
mA
notes 1 and 2
0.6
0.82
1.1
W
notes 2 and 3
0.96
1.25
1.66
W
CMOS input; pins UI, DR0, DR1, DR2, MUXR0, MUXR1, MD0, MD1, ENLINQ, ENLOUTQ, FIFORESET, PAREVEN
and CLKDIR
VIL
LOW-level input voltage
−
−
0.2VCC
V
VIH
HIGH-level input voltage
0.8VCC
−
−
V
IIL
LOW-level input current
VIL = 0 V
−200
−
−
µA
IIH
HIGH-level input current
VIH = VCC
−
−
10
µA
CMOS output; pins OVERFLOW, LOL and INT
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.2
V
VOH
HIGH-level output voltage
IOH = −0.5 mA
VCC − 0.2
−
VCC
V
Open-drain output; pin INT
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.2
V
IOH
HIGH-level output current
VOH = VCC
−
−
10
µA
Serial output; pins COUT, COUTQ, DOUT, DOUTQ, CLOOP, CLOOPQ, DLOOP, and DLOOPQ
Vo(p-p)
default output voltage swing single-ended with 50 Ω
(peak-to-peak value)
external load; note 4
220
280
340
mV
Zo
output impedance
single-ended to VCC
40
50
60
Ω
tr
rise time
20% to 80%
−
60
90
ps
tf
fall time
80% to 20%
−
60
90
ps
tD-C
data-to-clock delay
between differential
crossovers
−50
−
50
ps
δ
duty cycle COUT and
COUTQ
between differential
crossovers
40
50
60
%
fSBR
serial bit rate
MUX 16:1, 8:1, 4:1
30
−
3200
Mbits/s
MUX 10:1; note 5
30
−
3200
Mbits/s
50
−
1000
mV
VCC − 1
−
VCC + 0.25 V
Serial input; pins DIN, DINQ, CIN and CINQ
Vi(p-p)
input voltage
(peak-to-peak value)
Vi
input voltage range
2003 May 14
single-ended
34
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
SYMBOL
Zi
PARAMETER
input impedance
TZA3017HW
CONDITIONS
single-ended to VCC
MIN
40
TYP
50
MAX
60
UNIT
Ω
Parallel input (rail-to-rail); pins D00 to D15, D00Q to D15Q, PARITY, PARITYQ, PICLK, and PICLKQ
VEE − 0.25 −
VCC + 0.25 V
Vi
input voltage range
Vi(p-p)
input voltage swing
(peak-to-peak value)
single-ended
100
−
1000
mV
Vhys
input differential hysteresis
MD1 = LOW; MD0 = HIGH
−
30
−
mV
Zi(diff)
differential input impedance MD1 = LOW
80
100
120
Ω
Zi(se)
single-ended input
impedance
MD1 = HIGH
40
50
60
Ω
VT(CML)
input termination voltage in
CML mode
MD1 = HIGH; MD0 = LOW
−
VCC
−
V
VT(LVPECL)
input termination voltage in
LVPECL mode
MD1 = HIGH; MD0 = HIGH
VCC − 2.3
VCC − 2
VCC − 1.7
V
tsu(co)
set-up time
co-directional clocking
0
−
−
ps
th(co)
hold time
co-directional clocking
1000
−
−
ps
tsu(contra)
set-up time
contra-directional clocking
1300
−
−
ps
th(contra)
hold time
contra-directional clocking
−300
−
−
ps
δ
duty cycle PICLK and
PICLKQ
between differential
crossovers
40
50
60
%
fPBR
parallel bit rate
−
−
400
Mbits/s
CML mode output; pins POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO, and PRSCLOQ
Vo(p-p)
default output voltage swing single-ended with 50 Ω
(peak-to-peak value)
external load,
DC-coupled; note 6
600
850
1100
mV
Zo
output impedance
single-ended to VCC
80
95
110
Ω
tr
rise time
20% to 80%
200
250
350
ps
tf
fall time
80% to 20%
200
250
350
ps
LVPECL mode output; pins POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO, and PRSCLOQ
VOH
HIGH-level output voltage
50 Ω termination to
VCC − 2V
VCC − 1.2
VCC − 1.0 VCC − 0.9
V
VOL
LOW-level output voltage
50 Ω termination to
VCC − 2V
VCC − 2.0
VCC − 1.9 VCC − 1.7
V
Vo(p-p)
default output voltage swing LVPECL floating;
(peak-to-peak value)
single-ended with 50 Ω
external load
700
900
1150
mV
tr
rise time
20% to 80%
300
350
400
ps
tf
fall time
80% to 20%
300
350
400
ps
50
−
1000
mV
VCC − 1
−
VCC + 0.25 V
40
50
60
Reference frequency input; pins CREF, and CREFQ
Vi(p-p)
input voltage
(peak-to-peak value)
Vi
input voltage range
Zi
input impedance
2003 May 14
single-ended
single-ended to VCC
35
Ω
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
SYMBOL
PARAMETER
TZA3017HW
CONDITIONS
MIN
TYP
MAX
+20
UNIT
∆fCREF
reference clock frequency
accuracy
SDH/SONET requirement
−20
−
fCREF
reference clock frequency
see Table 4;
R = 1, 2, 4, or 8
18 × R
19.44 × R 21 × R
MHz
ppm
I2C-bus; pins SCL and SDA
VIL
LOW-level input voltage
−
−
0.2VCC
V
VIH
HIGH-level input voltage
0.8VCC
−
−
V
Vhys
hysteresis of Schmitt trigger
inputs
0.05VCC
−
−
V
VOL
SDA LOW-level output
voltage (open-drain)
0
−
0.4
V
IL
input leakage current
−10
−
+10
µA
Ci
input capacitance
−
−
10
pF
IOL = 3 mA
I2C-bus timing
fSCL
SCL clock frequency
−
−
100
kHz
tLOW
SCL LOW time
1.3
−
−
µs
tHIGH
SCL HIGH time
0.6
−
−
µs
tHD;STA
hold time START condition
0.6
−
−
µs
tSU;STA
set-up time START
condition
0.6
−
−
µs
tHD;DAT
data hold time
0
−
0.9
µs
tSU;DAT
data set-up time
100
−
−
ns
tSU;STO
set-up time STOP condition
0.6
−
−
µs
tr
SCL and SDA rise time
20
−
300
ns
tf
SCL and SDA fall time
20
−
300
ns
tBUF
bus free time between
STOP and START
1.3
−
−
µs
Cb
capacitive load on each bus
line
−
−
400
pF
tSP
pulse width of allowable
spikes
0
−
50
ns
VnL
noise margin at LOW-level
0.1VCC
−
−
V
VnH
noise margin at HIGH-level
0.2VCC
−
−
V
2003 May 14
36
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
SYMBOL
PARAMETER
TZA3017HW
CONDITIONS
MIN
TYP
MAX
UNIT
Jitter generation
Jgen(p-p)
jitter generation
(peak-to-peak value)
STM1/OC3 mode;
notes 7 and 8
f = 500 Hz to 1.3 MHz
−
−
16
mUI
f = 12 kHz to 1.3 MHz
−
−
4
mUI
f = 65 kHz to 1.3 MHz
−
−
4
mUI
f = 1 kHz to 5 MHz
−
−
63
mUI
f = 12 kHz to 5 MHz
−
−
13
mUI
f = 250 kHz to 5 MHz
−
−
13
mUI
f = 5 kHz to 20 MHz
−
35
250
mUI
f = 12 kHz to 20 MHz
−
32
50
mUI
f = 1 MHz to 20 MHz
−
7
50
mUI
STM4/OC12 mode;
notes 7 and 8
STM16/OC48 mode;
notes 7 and 8
Notes
1. Default settings: UI = LOW (pre-programmed mode; see Table 1); DR0 = LOW, DR1 = HIGH, DR2 = LOW
(STM16/OC48); PAREVEN = HIGH (even parity); MUXR0 = HIGH, MUXR1 = HIGH (multiplexing ratio is 16:1);
FIFORESET = LOW; MD0 = LOW, MD1 = LOW (100Ω differential); CLKDIR = HIGH (co-directional clocking);
ENLOUTQ = HIGH (DLOOP, DLOOPQ, CLOOP and CLOOPQ disabled); ENLINQ = HIGH (DIN, DINQ, CIN and
CINQ disabled); CREF and CREFQ = 19.44MHz; COUT, COUTQ, DOUT, DOUTQ, POCLK, POCLKQ, PARERR,
PARERRQ, PRSCLO and PRSCLOQ are not connected.
2. The total supply current and power dissipation is dependent on the I2C settings such as output swing, loop modes,
multiplexing ratio and input and output termination conditions. For dependency on output termination and output
swing; see Figs 18 and 20.
3. ENLOUTQ = LOW (DLOOP, CLOOP enabled); ENLINQ = LOW (DIN, CIN enabled) and maximum output swing;
COUT, COUTQ, DOUT, DOUTQ, POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO, PRSCLOQ, DLOOP,
DLOOPQ, CLOOP and CLOOPQ are not connected.
4. The output swing is adjustable in 16 steps controlled by bits RFS in the I2C-bus register IOCNF0 (address CBH).
5. For multiplexing ratio 10:1, the I2C-bus register MUXTIMING (address FDH) should be programmed with 0000.0100
(04H) for supporting 3.2 Gbits/s. The highest supported bit rate for multiplexing ratio 10:1 in a pin programmed
application is 2.7 Gbits/s.
6. The output swing is adjustable in 16 steps controlled by bits MFS in the I2C-bus register IOCNF2 (address C8H).
7. Reference frequency of 19.44 MHz, with a phase-noise of less than −140 dBc for frequencies of more than 12 kHz
from the carrier. Measured for 60 seconds within the appropriate bandwidth.
8. For bit rates lower than 1.8 Gbits/s, the jitter decreases with the octave division ratio.
2003 May 14
37
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
MBL556
handbook, full pagewidth
50
ICCD
(mA)
40
LVPECL standard
30
CML AC
LVPECL floating
20
10
CML DC
0
0
5
10
15
value of address C8H, bit 3 to bit 0
Fig.18 Supply current per parallel output.
MDB064
handbook, full pagewidth
DEFAULT
1000
Vo(p-p)
(mV)
800
LVPECL
CML
600
400
200
0
0
5
10
15
value of address C8H, bit 3 to bit 0
Fig.19 Output voltage swing of parallel output.
2003 May 14
38
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
MDB065
60
handbook, full pagewidth
50
ICCD
(mA)
40
CML AC
30
CML DC
20
10
0
0
5
10
15
value of address CBH, bit 3 to bit 0
Fig.20 Supply current per serial output.
handbook, full pagewidth
MDB066
1100
1000
Vo(p-p)
(mV)
800
600
400
DEFAULT
200
0
0
5
10
15
value of address CBH, bit 3 to bit 0
Fig.21 Output voltage swing of serial output.
2003 May 14
39
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
handbook, full pagewidth
SWING CONTROL
VCC
Vterm
OUT
2V
optional
AC coupling
transmission
lines
to highimpedance
input
50 Ω
50 Ω
OUTQ
Iswing
50 Ω
50 Ω
in
on-chip
off-chip
MBL562
Fig.22 Parallel output standard LVPECL mode.
handbook, full pagewidth
SWING CONTROL
VCC
OUT
transmission lines
50 Ω
50 Ω
OUTQ
Iswing
100 Ω
to highimpedance
input
in
on-chip
off-chip
Fig.23 Parallel output floating LVPECL mode (DC-coupled).
2003 May 14
40
MBL560
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
handbook, full pagewidth
SWING CONTROL
VCC
Vbias
AC coupling
OUT
50 Ω
transmission
lines
50 Ω
to highimpedance
input
50 Ω
50 Ω
OUTQ
Iswing
in
on-chip
off-chip
MBL561
Fig.24 Parallel output floating LVPECL mode (AC-coupled).
handbook, full pagewidth
SWING CONTROL
VCC
100 Ω
Vbias
100 Ω
50 Ω
transmission
lines
OUT
50 Ω
to highimpedance
input
50 Ω
OUTQ
Iswing
in
on-chip
off-chip
MDB067
Fig.25 Parallel output CML mode (AC-coupled).
2003 May 14
41
50 Ω
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
handbook, full pagewidth
SWING CONTROL
VCC
100 Ω
100 Ω
OUT
50 Ω
transmission
lines
50 Ω
to highimpedance
input
50 Ω
OUTQ
Iswing
50 Ω
in
on-chip
off-chip
MBL564
Fig.26 Parallel output CML mode (DC-coupled).
handbook, full pagewidth
SWING CONTROL
VCC
50 Ω
Vbias
50 Ω
50 Ω
transmission
lines
OUT
50 Ω
to highimpedance
input
50 Ω
OUTQ
Iswing
in
on-chip
off-chip
Fig.27 Serial output CML mode (AC-coupled).
2003 May 14
42
50 Ω
MDB068
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
handbook, full pagewidth
SWING CONTROL
VCC
50 Ω
50 Ω
50 Ω
transmission
lines
OUT
50 Ω
to highimpedance
input
50 Ω
OUTQ
Iswing
50 Ω
in
on-chip
off-chip
MDB069
Fig.28 Serial output CML mode (DC-coupled).
handbook, full pagewidth
PICLK
t h(co)
t su(co)
D00 to D15,
PARITY
valid data
POCLK
MBL581
The timing is measured from the crossover point of the reference signal to the crossover point of the input.
Fig.29 Parallel bus co-directional timing.
2003 May 14
43
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
handbook, full pagewidth
D00 to D15,
PARITY
valid data
t su(contra)
t h(contra)
POCLK
MBL582
The timing is measured from the crossover point of the reference signal to the crossover point of the input.
Fig.30 Parallel bus contra-directional timing.
handbook, full pagewidth
COUT, CLOOP
t D-C
DOUT, DLOOP
MBL583
The timing is measured from the crossover point of the reference signal to the crossover point of the output.
Fig.31 RF output timing.
2003 May 14
44
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
PACKAGE OUTLINE
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads;
body 14 x 14 x 1 mm; exposed die pad
SOT638-1
c
y
exposed die pad side
X
Dh
A
75
51
76
50
ZE
e
E HE
Eh
A
A2
(A3)
A1
w M
θ
bp
Lp
pin 1 index
L
detail X
26
100
1
25
bp
e
w M
ZD
v M A
D
B
HD
v M B
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max.
mm
1.2
A1
A2
A3
bp
c
D(1)
Dh
E(1)
Eh
e
0.15
0.05
1.05
0.95
0.25
0.27
0.17
0.20
0.09
14.1
13.9
7.1
6.1
14.1
13.9
7.1
6.1
0.5
HD
HE
16.15 16.15
15.85 15.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.08
ZD(1) ZE(1)
θ
1.15
0.85
7°
0°
1.15
0.85
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
01-03-30
03-04-07
SOT638-1
2003 May 14
EUROPEAN
PROJECTION
45
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 May 14
46
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 May 14
47
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 May 14
48
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 May 14
49
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
NOTES
2003 May 14
50
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic transmitter
TZA3017HW
NOTES
2003 May 14
51
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403510/02/pp52
Date of release: 2003
May 14
Document order number:
9397 750 10574