PHILIPS PCD4440T

INTEGRATED CIRCUITS
DATA SHEET
PCD4440T
Analog voice
scrambler/descrambler
Product specification
Supersedes data of October 1992
File under Integrated Circuits, IC03
1996 Dec 20
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
6
PINNING INFORMATION
6.1
6.2
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Pinning
Pin description
Scrambling
Power supply (VDD, VSS)
Oscillator (OSCI)
Splitting frequency and mode selection
Serial clock input (SCL), Serial data input (SDA)
Address input (A0)
I2C-bus data configuration
Signal input (IN), Signal output (OUT)
8
I2C BUS INTERFACE
8.1
8.2
8.3
8.4
8.5
Bit transfer
Start and stop conditions
System configuration
Acknowledge
Timing specifications
9
APPLICATIONS
10
HANDLING
11
LIMITING VALUES
12
CHARACTERISTICS
14.1
14.2
14.3
14.4
Introduction
Reflow soldering
Wave soldering
Repairing soldered joints
15
DEFINITIONS+
16
LIFE SUPPORT APPLICATIONS
17
PURCHASE OF PHILIPS I2C COMPONENTS
1996 Dec 20
2
PCD4440T
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
1
PCD4440T
2
FEATURES
APPLICATIONS
• Scrambler or descrambler function
• Cordless telephones
• Scrambling in frequency domain
• Security telephones
• Selectable split frequency (up to 10 selections per
second)
• Portable phones
• Private Mobile Radio (PMR).
• Telephony-band filtering included
• No increase in bandwidth
3
• No external components required
GENERAL DESCRIPTION
The PCD4440T is a silicon gate CMOS integrated circuit
intended to be used in cordless telephony, radio, and line
telecommunications products utilizing a microcontroller for
the control functions. The purpose of the device is to
prevent unauthorized ‘listening-in’ on conversations.
A major application is protection of the vulnerable radio link
between a CT0 type cordless handset and its base unit.
Analog scrambling/descrambling is based on the split
frequency method realized in a sophisticated
switched-capacitor technology. The PCD4440T is
compatible with most microcontrollers and communicates
via a two line bidirectional I2C-bus.
• Small signal delay
• Insensitive to distortion and group delay of transmission
channel
• Control via serial I2C-bus
• Low transfer loss of speech
• Mute option
• Transparent mode
• High signal input impedance
• Low signal output impedance
• Low power consumption.
4
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
PCD4440T
SO8
1996 Dec 20
DESCRIPTION
plastic small outline package; 8 leads; body width 7.5 mm
3
VERSION
SOT176-1
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
5
PCD4440T
BLOCK DIAGRAM
handbook, full pagewidth
clocks
LPF
IN
4
LPF
PCD4440T
LPF
LPF
I2C-bus INTERFACE
mute
1
2
SCL
SDA
CONTROL LOGIC
8
A0
Fig.1 Block diagram.
1996 Dec 20
OUT
LPF
transparent
BIAS GEN
5
LPF
4
7
6
3
OSCI
VDD
VSS
MGG729
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
6
PCD4440T
PINNING INFORMATION
6.1
7.1
The PCD4440Taccomplishes this task by first filtering the
incoming signal, limiting the bandwidth to 3500 Hz. Then
the signal is split into a high (> fs) and a low (< fs) frequency
band. Both frequency bands are inverted and added again
to provide a single output signal. Values for 9 split
frequencies fS can be controlled by a scramble code table
in the microcontroller. Control of these split frequencies is
accomplished via the serial two-wire I2C-bus. In addition to
the split frequencies (fs), a transparent mode and mute
instruction can be selected (see Table 1).
Pinning
handbook, halfpage
SCL 1
8 A0
SDA 2
7
OSCI
PCD4440T
VSS
3
6
VDD
IN
4
5
OUT
Scrambling
MGG728
Figure 3 shows the signal path for both bands. The lower
band path (on the left side of the diagram) operates on
frequencies f ≤ fs (Split Frequency), the upper band path
(on the right side) on frequencies f ≥ fs.
Fig.2 Pin configuration.
6.2
SYMBOL
PIN
TYPE
SCL
1
I
serial clock line (I2C-bus)
SDA
2
I
serial data line (I2C-bus)
VSS
3
P
negative Supply
IN
4
I
signal input
OUT
5
O
signal output
VDD
6
P
positive supply
OSCI
7
I
oscillator input
A0
8
I
slave address input (I2C-bus)
7
The input signal contains frequencies from f1 up to f2.
In scrambling mode, the output signal is band limited from
fl (300 Hz) to fh (3500 Hz). In the left path, the input signal
is first limited to fs. The following modulator inverts the
lower band. fl is folded up to fs, fs down to fl. In general, an
input frequency fin is folded to fout = fs + fl − fin. Finally the
folded signal is band limited to fs again.
Pin description
DESCRIPTION
In the right path, the input signal is first limited to fh.
The following modulator inverts the upper band. fs is folded
up to fh, fh down to fs. In general, an input frequency fin is
folded to fout = fs + fh − fin. Finally, the folded signal is band
limited to fh again. In the last step, the bands are added
and buffered.
Because of the symmetry of the scrambling process,
descrambling is achieved by passing the signal through
another PCD4440T.
FUNCTIONAL DESCRIPTION
To provide privacy for the end user of a cordless telephone
set, the radio-link audio signal must be scrambled. In the
microphone of the handset and the incoming telephone
line audio path of the base unit a scrambler circuit has to
be implemented. Consequently the audio signal to the
telephone line and to the earpiece must be descrambled.
Both functions can be fulfilled by the PCD4440T by simply
inserting it in the audio path.
1996 Dec 20
In the transparent mode, the input signal is band limited to
3500 Hz. Frequencies from 0 to 300 Hz are not filtered
out.
5
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
A
handbook, full pagewidth
a b
0 f1 fl
c d
fs
e
f
fh
f2
f
LPF
1a
LPF
2a
A
A
a b
0 f1 fl
c
a b
fs
0 f1 fl
f
fm1 = fl + fs
A
c
0 f1 fl
c d
ab
c
fs
fs
fh
f2
f
e
d c
ba
ab
fh
f2
fm2 = fh + fs
A
ba
e
0 f1 fl
f
fs
LPF
1b
A
c
0 f1 fl
b
e
fs
f
0 f1 fl
fs
d
fh
A
c
0 f1 fl
b e
fs
d
fh
f2
f
MGG730
Fig.3 Scrambler signal path.
1996 Dec 20
6
f2
e
f
LPF
2b
A
cd
f
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
7.2
PCD4440T
Power supply (VDD, VSS)
7.4
Table 1 shows the input codes required to select the
various splitting frequencies, and the mute, transparent
and scramble/descramble modes. The codes form part of
the serial I2C-bus message input on the SDA line from the
microcontroller.
The positive supply of the circuit (VDD) must meet the
voltage requirement as indicated in the characteristics.
To avoid undefined states of the device at power-on, an
internal reset circuit clears the logic. The power-on reset
has the highest priority; it blocks and resets the complete
circuit.
7.3
Splitting frequency and mode selection
Oscillator (OSCI)
The time base for the PCD4440T is a 3.58 MHz input
signal which can be derived from the oscillator output
(OSCO) of Philips microcontroller families PCD33xxA or
PCF84CxxxA. Figure 4 shows the OSCI connection.
handbook, full pagewidth
27 pF
PCD33xxA
PCF84CxxxA
OSCO
MICROCONTROLLER
OSCI
PCD4440T
MGG731
3.58 MHz
Fig.4 OSCI (oscillator input) connection.
Table 1
Input data codes for splitting frequency and mode selection; note 1
D3
D2
D1
D0
HEX
fs(2) (Hz)
APPLICATION
0
0
0
1
01
Mute mode
−
0
0
1
0
02
Select fs
2641
0
0
1
1
03
Select fs
1853
0
1
0
0
04
Select fs
1507
0
1
0
1
05
Select fs
1279
0
1
1
0
06
Select fs
1117
0
1
1
1
07
Select fs
1018
1
0
0
0
08
Select fs
899
1
0
0
1
09
Select fs
837
1
0
1
0
0A
Select fs
767
1
0
1
1
0B
Transparent mode
−
1
1
1
1
0F
Start scramble/descramble mode
−
Notes
1. Input codes other than shown in the table are not allowed.
2. Oscillator frequency = 3.58 MHz.
1996 Dec 20
7
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
7.5
PCD4440T
Serial clock input (SCL), Serial data input
(SDA)
I2C-bus data configuration
7.7
SCL and SDA are serial clock and data lines which
conform to the I2C-bus specification. Both inputs must be
pulled up externally to VDD through resistors of
approximately 10 kΩ.
The PCD4440T is always a slave receiver in the I2C-bus
configuration (the R/W bit = 0). The slave address consists
of 7 bits, where the least significant is set by the input on
A0. The more significant bits are fixed internally, as shown
in Fig.5. For definition of D0-D4, see Table 1.
7.6
7.8
Address input (A0)
A0 is the slave address input and is used to set one bit of
the slave address, so as to identify one of two PCD4440T
devices connected to the same I2C-bus. Whether another
PCD4440T is connected to the bus or not, A0 must be
connected to VDD or VSS. The remaining bits of the slave
address are fixed internally.
Signal input (IN), Signal output (OUT)
Signal input for the scrambler/descrambler is coupled into
a ‘Sallen and Key’ anti-aliasing filter configuration. A DC
bias voltage of 1⁄2VDD is built-in.
The analog signal output is buffered to achieve a relatively
low output impedance of roughly 1 kΩ which is sufficient to
drive the earpiece amplifier or similar applications.
acknowledge
handbook, full pagewidth
MSB
S
1
acknowledge
R/W
1
0
1
1
1
A0
0
A
0
0
0
slave address
D3
D2
D1
D0
A
P
data
internal STROBE
MGG732
Fig.5 I2C-bus data format.
1996 Dec 20
0
8
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
8
PCD4440T
I2C BUS INTERFACE
The I2C-bus is for two-way communication between different ICs or modules. It uses only two lines, a serial data line
(SDA) and a serial clock line (SCL), both of which are bi-directional. Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus
is not busy.
8.1
Bit transfer (see Fig.6)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as control signals.
SDA
SCL
change
of data
allowed
data line
stable;
data valid
MBC621
Fig.6 Bit transfer.
8.2
Start and stop conditions (see Fig.7)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is
defined as the stop condition (P).
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Fig.7 Start and stop conditions.
1996 Dec 20
9
MBC622
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
8.3
PCD4440T
System configuration (see Fig.8)
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
message transfer is the ‘master’ and the devices that are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER /
RECEIVER
MASTER
TRANSMITTER
MBA605
Fig.8 System configuration.
8.4
Acknowledge (see Fig.9)
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited.
Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra acknowledge after the reception of each byte. Also a master must
generate an acknowledge after reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the acknowledge-related clock pulse. Set-up and hold times must
be taken into account to ensure that the SDA line is stable LOW during the whole high period of the acknowledge-related
clock pulse. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate the stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
START
CONDITION
MBC602
Fig.9 Acknowledgment on the I2C-bus.
1996 Dec 20
10
clock pulse for
acknowledgement
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
8.5
PCD4440T
Timing specifications
The PCD4440T accepts data input from a microcontroller and operates as a ‘slave receiver’ via the I2C-bus. It supports
the ‘standard’ mode of the I2C-bus, but not the ‘fast’ mode detailed in “The I2C-bus and how to use it” document order
no. 9398 393 40011. The timing requirement are as follows:
Masters generate a bus clock with a maximum frequency of 100 kHz. Detailed timing is shown in Fig. 10, where the two
signal levels are LOW = VIL and HIGH = VIH, see Chapter 12. The time symbols are explained in Table 2. Figure 11
shows a complete data transfer.
handbook, full pagewidth
SDA
t LOW
t BUF
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA
MBC764
t SU;STA
t SU;STO
Fig.10 Standard mode timing.
handbook, full pagewidth
SDA
SCL
1-7
8
START ADDRESS
CONDITION
R/W
9
ACK
1-7
8
DATA
9
ACK
1-7
START ADDRESS
CONDITION
Clock LOW minimum = 4.7 µs; clock HIGH minimum = 4 µs.
The dashed line is the acknowledgment of the receiver.
Mark-to-space ratio = 1 : 1 (LOW-to-HIGH).
Maximum number of bytes is unrestricted.
Premature termination of transfer is allowed by generation of STOP condition.
Acknowledge clock bit must be provided by master.
Fig.11 Complete data transfer in standard mode.
1996 Dec 20
11
8
9
R/W
ACK
STOP
MBC765
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
Table 2
PCD4440T
Explanation of time symbols used in Fig.10
SYMBOL
PARAMETER
DESCRIPTION
MIN.
MAX.
UNITS
fSCL
SCL clock frequency
0
100
kHz
tSW
tolerable pulse spike width
−
100
ns
tBUF
bus free time
The time that the bus is free (SDA is HIGH)
before a new transmission is initiated by
SDA going LOW.
4.7
−
µs
tSU;STA
set-up time repeated START
Only valid for repeated start code.
4.7
−
µs
tHD;STA
hold time START condition
The time between SDA going LOW and the
first valid negative-going transition of SCL.
4.0
−
µs
tLOW
SCL LOW time
The LOW period of the SCL clock.
4.7
−
µs
tHIGH
SCL HIGH time
The HIGH period of the SCL clock.
4.0
−
µs
tr
rise time SDA and SCL
−
1.0
µs
tf
fall time SDA and SCL
−
0.3
µs
tSU;DAT
data set-up time
250
−
ns
tHD;DAT
data hold time
0
−
ns
tSU;STO
set-up time STOP condition
4.0
−
µs
1996 Dec 20
12
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
9
PCD4440T
APPLICATIONS
handbook, full pagewidth
LCD DISPLAY
LCD DRIVER
antenna
I2C-bus
mod
data out
power down RX
KEYPAD
power down TX
RSSI
RF
SECTION
MICROCONTROLLER
PCD33xxA
A/D CONVERTER
RX
DETECTOR
data in
TX
VREF
DESCRAMBLER
PCD4440T
EXPANDOR
1/2 NE577
SCRAMBLER
PCD4440T
COMPRESSOR
1/2 NE577
MGG733
Fig.12 CT0 handset with direct (Manchester code) data system.
1996 Dec 20
13
1
2
3
4
5
6
7
8
9
*
0
#
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
antenna
handbook,
full pagewidth
I2C-bus
mod
data out
power down RX
power down TX
RSSI
RF
SECTION
A/D CONVERTER
RX
MICROCONTROLLER
PCD33xxA
DETECTOR
data in
CHARGING
CIRCUIT
TX
DTMF
VREF
DESCRAMBLER
PCD4440T
EXPANDOR
1/2 NE577
SCRAMBLER
PCD4440T
COMPRESSOR
1/2 NE577
LINE INTERFACE
TEA106x
telephone
line
MGG734
Fig.13 CT0 base unit with direct (Manchester code) data system.
10 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handbook IC03, Section General, Handling MOS
devices”).
1996 Dec 20
14
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.3
+7.0
V
VI
all input voltages
−0.8
VDD + 0.8
V
II
DC input current
−10
+10
mA
IO
DC output current
−20
+20
mA
Ptot
total power dissipation
−
300
mW
PO
power dissipation per output
−
50
mW
Tstg
storage temperature
−65
+150
°C
Tamb
operating ambient temperature
−25
+70
°C
12 CHARACTERISTICS
VDD = 5.0 V; VSS = 0 V; Tamb = 25 °C; all voltages with respect to VSS; fxtal = 3.579 MHz unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
operating supply voltage
IDD
supply current
2.8
−
6.0
V
mute mode
VDD = 3 V
−
2.2
−
mA
operating mode
VDD = 3 V
−
13
−
mA
−
Inputs/Outputs: AO, SDA, SCL
VIL
LOW level input voltage
0
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD −
VDD
V
Ci
input capacitance
−
−
7
pF
IOL
SDA output current LOW
3.0
−
−
mA
−
0.5VDD −
VOL = 0.4 V
Signal input: IN
VDC
DC voltage level
Vi(P-P)
allowed amplitude
|Zi|
input impedance
V
−
1.25
VDD − 1 V
frequency = 1 kHz
−
120
−
kΩ
Signal output: OUT
VDC
DC voltage level
−
0.5VDD −
V
|Zo|
output impedance
frequency = 1 kHz
−
−
1
kΩ
UFS
unwanted frequency
suppression
Vi(P-P) = 1.25 V; fS = 767 or 2461 Hz;
fin = 1 kHz; VDD = 3 V or 5 V
35
40
−
dB
Vo/Vi
transfer loss
transparent mode
−
3.5
−
dB
operating mode
−
0
−
dB
Oscillator frequency input: OSCI
VDC
DC voltage level
−
0.5VDD −
V
VIL
LOW level input voltage
0
−
0.3VDD
V
VIH
HIGH level input voltage
0.7VDD −
VDD
V
1996 Dec 20
15
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
13 PACKAGE OUTLINE
SO8: plastic small outline package; 8 leads; body width 7.5 mm
SOT176-1
D
E
A
X
c
y
HE
v M A
Z
8
5
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
7.65
7.45
7.6
7.4
1.27
10.65
10.00
1.45
1.1
0.45
1.1
1.0
0.25
0.25
0.1
2.0
1.8
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.30
0.29
0.30
0.29
0.050
0.42
0.39
0.057
0.043
0.018
0.043
0.039
0.01
0.01
0.004
0.079
0.071
inches
0.10
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
91-08-13
95-02-25
SOT176-1
1996 Dec 20
EUROPEAN
PROJECTION
16
o
8
0o
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
14 SOLDERING
14.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
14.2
14.4
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
14.3
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
1996 Dec 20
Repairing soldered joints
17
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
15 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
16 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Dec 20
18
Philips Semiconductors
Product specification
Analog voice scrambler/descrambler
PCD4440T
NOTES
1996 Dec 20
19
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© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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Printed in The Netherlands
417021/1200/02/pp20
Date of release: 1996 Dec 20
Document order number:
9397 750 01604