PHILIPS TZA3012AHW

INTEGRATED CIRCUITS
DATA SHEET
TZA3012AHW
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
Product specification
Supersedes data of 2002 Sep 10
2003 May 21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
FEATURES
• Single 3.3 V power supply
• I2C-bus and pin programmable fibre optic receiver.
Dual limiter features
• Exchangeable pin designations of RF clock with data for
all I/Os for optimum connectivity
• Dual limiting input with 12 mV sensitivity
• Received Signal Strength Indicator (RSSI)
• Reversible pin designations of parallel data bus bits for
optimum connectivity
• Loss Of Signal (LOS) indicator with threshold adjust
• Differential overvoltage protection.
• Slice level adjustment to improve Bit Error Rate (BER)
Data and clock recovery features
• Mute function for a forced logic 0 output state
• Supports SHD/SONET bit rates at 155.52, 622.08,
2488.32 and 2666.06 Mbits/s (STM16/OC48 + FEC)
• Programmable parity
• Programmable 32-bit frame detection.
• Supports Gigabit Ethernet at 1250 and 3125 Mbits/s
• Supports Fibre Channel at 1062.5 and 2125 Mbits/s
APPLICATIONS
• ITU-T compliant jitter tolerance
• Frequency lock indicator
• Any optical transmission system with bit rates between
30 Mbits/s and 3.2 Gbits/s
• Stable clock signal when input data absent
• Physical interface IC in receive channels
• Outputs for recovered data and clock loop mode.
• Transponder applications
Demultiplexer features
• Dense Wavelength Division Multiplexing (DWDM)
systems.
• 1:16, 1:10, 1:8 or 1:4 demultiplexing ratio
• LVPECL or CML demultiplexer outputs
GENERAL DESCRIPTION
• Frame detection for SDH/SONET and GE frames
The TZA3012AHW is a fully integrated optical network
receiver containing a dual limiter, Data and Clock
Recovery (DCR) and a demultiplexer with demultiplexing
ratios 1:16, 1:10, 1:8 or 1:4.
• Parity bit generation
• Loop mode inputs to demultiplexer.
The A-rate feature allows the IC to operate at any bit rate
between 30 Mbits/s and 3.2 Gbits/s using a single
reference frequency. The receiver supports loop modes
with serial clock and data inputs and outputs. All clock
signals are generated using a fractional N synthesizer with
10 Hz resolution giving a true, continuous rate operation.
For full configuration flexibility, the receiver is
programmable by pin or via the I2C-bus.
Additional features with the I2C-bus
• A-rateTM(1) supports any bit rate from 30 Mbits/s to
3.2 Gbits/s with one reference frequency
• Programmable frequency resolution of 10 Hz
• Four reference frequency ranges
• Adjustable swing of data, clock and parallel outputs
• Programmable polarity of all RF I/Os
(1) A-rate is a Trademark of Koninklijke Philips Electronics N.V.
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
TZA3012AHW
HTQFP100
2003 May 21
DESCRIPTION
plastic thermal enhanced thin quad flat package; 100 leads;
body 14 × 14 × 1 mm; exposed die pad
2
VERSION
SOT638−1
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LOSTH1
5
6
7
DLOOP
87
DMXR1
ENLINQ
88 84 85
91
52 30 31
38
39
PARITY
PARITYQ
LOS
RSSI
INSEL
IN1
IN1Q
12
TZA3012AHW
9
c
d
LIM
10
DMX
1 : 4 16
1:8
1 : 10
1 : 16
SWITCH
PHASE
2
DETECTOR
16
d
PARITY
GENERATOR
AND
BUS SWAP
c
IN2
LIM
17
16
16
44, 46, 48, 53
55, 57, 59, 61,
64, 66, 68, 70
72, 77, 79, 81
45, 47, 49, 54
56, 58, 60, 62,
65, 67, 69, 71
73, 78, 80, 82
2
IN2Q
41
42
2
LPF
2
RSSI
36
37
LOS
3
SCL(DR2)
SDA(DR1)
CS(DR0)
UI
i.c.
FREQUENCY
WINDOW DETECTOR
19
LOSTH2
2
RREF
94
95
24
23
97
98
I2C-BUS
22
4
INTERRUPT
CONTROLLER
28, 29
14
8, 11,
15, 18
4
VCCA
20
RSSI2
21
13 33 34 27 2
LOS2
CREFQ
CREF
90
PRSCLOQ
INWINDOW
26, 50, 63,
74, 100
POCLK
POCLKQ
FP
FPQ
COUT
COUTQ
DOUT
DOUTQ
INT
MGU314
13
VDD
VCCD
PRSCLO
25
D00Q
to D15Q
ENLOUTQ
Fig.1 Simplified block diagram.
VEE
Product specification
LIM = Limiting amplifier.
RSSI = Receiving Signal Strength Indicator.
LOS = Loss Of Signal detector.
LPF = Low-Pass Filter.
DMX = Demultiplexer.
VCCO
TZA3012AHW
WINSIZE
3
1, 35, 40, 43, 51
75, 76, 83, 86,
89, 93, 96, 99
32
92
D00
to D15
Philips Semiconductors
LOS1
RSSI1
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
DMXR0
ENBA
BLOCK DIAGRAM
pagewidth
2003 May 21
CLOOP
DLOOPQ CLOOPQ
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
PINNING
SYMBOL
VEE
SYMBOL
PIN
DESCRIPTION
die pad common ground plane
PIN
DESCRIPTION
VCCO
32
supply voltage (clock generator)
CREF
33
reference clock input
VCCD
1
supply voltage (digital part)
CREFQ
34
reference clock inverted input
PRSCLO
2
prescaler output
VCCD
35
supply voltage (digital part)
PRSCLOQ
3
prescaler inverted output
FP
36
frame pulse output
UI
4
user interface select
FPQ
37
frame pulse inverted output
LOS1
5
first input channel loss of signal
output
PARITY
38
parity output
PARITYQ
39
parity inverted output
RSSI1
6
first input channel received
signal strength indicator output
VCCD
40
supply voltage (digital part)
POCLK
41
parallel clock output
POCLKQ
42
parallel clock inverted output
VCCD
43
supply voltage (digital part)
D00
44
parallel data 00 output
D00Q
45
parallel data 00 inverted output
D01
46
parallel data 01 output
D01Q
47
parallel data 01 inverted output
D02
48
parallel data 02 output
D02Q
49
parallel data 02 inverted output
50
ground
LOSTH1
7
first input channel loss of signal
threshold input
VCCA
8
supply voltage (analog part)
IN1
9
first channel input
IN1Q
10
first channel inverted input
VCCA
11
supply voltage (analog part)
INSEL
12
input selector
WINSIZE
13
wide and narrow frequency
detect window select
RREF
14
reference resistor input
VEE
VCCA
15
supply voltage (analog part)
VCCD
51
supply voltage (digital part)
IN2
16
second channel input
ENBA
52
byte alignment enable input
53
parallel data 03 output
IN2Q
17
second channel inverted input
D03
VCCA
18
supply voltage (analog part)
D03Q
54
parallel data 03 inverted output
LOSTH2
19
second input channel loss of
signal threshold input
D04
55
parallel data 04 output
D04Q
56
parallel data 04 inverted output
RSSI2
20
second input channel received
signal strength indicator output
D05
57
parallel data 05 output
D05Q
58
parallel data 05 inverted output
LOS2
21
LOS output of second input
channel
D06
59
parallel data 06 output
D06Q
60
parallel data 06 inverted output
D07
61
parallel data 07 output
D07Q
62
parallel data 07 inverted output
I2C-bus serial clock (data rate
select 2)
VEE
63
ground
D08
64
parallel data 08 output
supply voltage (digital part)
D08Q
65
parallel data 08 inverted output
66
parallel data 09 output
CS(DR0)
22
chip select (data rate select 0)
SDA(DR1)
23
I2C-bus serial data (data rate
select 1)
SCL(DR2)
VDD
24
25
VEE
26
ground
D09
INWINDOW
27
frequency window detector
output
D09Q
67
parallel data 09 inverted output
D10
68
parallel data 10 output
i.c.
28
internally connected
D10Q
69
parallel data 10 inverted output
i.c.
29
internally connected
D11
70
parallel data 11 output
DMXR0
30
demultiplexing ratio select 0
D11Q
71
parallel data 11 inverted output
DMXR1
31
demultiplexing ratio select 1
D12
72
parallel data 12 output
2003 May 21
4
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
PIN
DESCRIPTION
SYMBOL
PIN
D12Q
73
parallel data 12 inverted output
ENLOUTQ
90
VEE
74
ground
line loop back enable input
(active LOW)
VCCD
75
supply voltage (digital part)
ENLINQ
91
VCCD
76
supply voltage (digital part)
diagnostic loop back enable
input (active LOW)
D13
77
parallel data 13 output
INT
92
interrupt output
D13Q
78
parallel data 13 inverted output
VCCD
93
supply voltage (digital part)
D14
79
parallel data 14 output
COUT
94
recovered clock output
COUTQ
95
recovered clock inverted output
VCCD
96
supply voltage (digital part)
DOUT
97
recovered data output
DOUTQ
98
recovered data inverted output
SYMBOL
D14Q
80
parallel data 14 inverted output
D15
81
parallel data 15 output
D15Q
82
parallel data 15 inverted output
DESCRIPTION
VCCD
83
supply voltage (digital part)
CLOOP
84
loop mode clock input
VCCD
99
supply voltage (digital part)
CLOOPQ
85
loop mode clock inverted input
VEE
100
ground
VCCD
86
supply voltage (digital part)
DLOOP
87
loop mode data input
DLOOPQ
88
loop mode data inverted input
VCCD
89
supply voltage (digital part)
2003 May 21
5
Philips Semiconductors
Product specification
76 VCCD
77 D13
78 D13Q
79 D14
81 D15
80 D14Q
82 D15Q
83 VCCD
84 CLOOP
86 VCCD
85 CLOOPQ
87 DLOOP
88 DLOOPQ
89 VCCD
90 ENLOUTQ
91 ENLINQ
TZA3012AHW
93 VCCD
92 INT
94 COUT
95 COUTQ
96 VCCD
97 DOUT
handbook, full pagewidth
98 DOUTQ
100 VEE
99 VCCD
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
VCCD
PRSCLO
1
75 VCCD
2
PRSCLOQ
3
74 VEE
73 D12Q
UI
4
72 D12
LOS1
5
71 D11Q
RSSI1
6
70 D11
LOSTH1
7
69 D10Q
VCCA
8
68 D10
IN1
9
67 D09Q
IN1Q 10
66 D09
VCCA 11
65 D08Q
INSEL 12
64 D08
TZA3012AHW
WINSIZE 13
63 VEE
RREF 14
62 D07Q
VCCA 15
61 D07
IN2 16
60 D06Q
IN2Q 17
59 D06
VCCA 18
LOSTH2 19
58 D05Q
RSSI2 20
56 D04Q
57 D05
LOS2 21
55 D04
54 D03Q
CS(DR0) 22
Fig.2 Pin configuration.
2003 May 21
6
VEE 50
D02Q 49
D02 48
D01Q 47
D01 46
D00Q 45
D00 44
VCCD 43
POCLKQ 42
POCLK 41
VCCD 40
PARITYQ 39
PARITY 38
FP 36
FPQ 37
VCCD 35
CREFQ 34
CREF 33
VCCO 32
DMXR1 31
51 VCCD
DMXR0 30
VDD 25
i.c. 29
52 ENBA
i.c. 28
53 D03
SCL(DR2) 24
VEE 26
INWINDOW 27
SDA(DR1) 23
MGU315
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
FUNCTIONAL DESCRIPTION
Table 3
The TZA3012AHW receives data from an incoming bit
stream having a bit rate from 30 Mbits/s up to 3.2 Gbits/s.
Two line inputs with limiting amplifiers are available.
An internal DCR synchronizes the internal clock generator
to the incoming data. The recovered serial data and clock
are demultiplexed at ratios of 1:16, 1:10, 1:8 or 1:4.
Truth table for selecting bit rate in
pre-programmed mode (pin UI = VEE)
PROTOCOL
BIT RATE
(Mbits/s)
DR2
DR1
DR0
LOW
LOW
LOW
STM1/OC3
155.52
LOW
LOW
HIGH
STM4/OC12
622.08
LOW
HIGH
LOW
STM16/OC48
2488.32
Choice of user interface
LOW
HIGH
HIGH
STM16 + FEC
2666.06
The TZA3012AHW can be controlled either via the I2C-bus
or using programming pins DR0 to DR2. Pin UI selects the
user interface required. I2C-bus control and A-rate
functionality are enabled when pin UI is either open circuit
or connected to VCC. Pre-programmed mode is enabled
when pin UI is connected to VEE; see Table 1.
HIGH
LOW
LOW
GE
1250.00
HIGH
LOW
HIGH
10GE
3125.00
HIGH
HIGH
LOW
Fibre Channel
1062.50
HIGH
HIGH
HIGH
Fibre Channel
2125.00
Table 1
After power-up, the TZA3012AHW initiates a Power-On
Reset (POR) sequence to restore the default settings of
the I2C-bus registers, irrespective of the level on pin UI.
The default settings are shown in Table 12.
Truth table for pin UI
UI
MODE
PIN 22
PIN 23
PIN 24
LOW
pre-programmed
DR0
DR1
DR2
HIGH
I2C-bus
CS
SDA
SCL
control
Limiting amplifiers
The TZA3012AHW has two switchable RF line inputs.
Each input has a limiting amplifier (limiter) which provides
optimum receiver sensitivity at any bit rate. The bandwidth
of each limiter is automatically adjusted in accordance with
the input bit rate. This ensures that wideband noise
present in the optical front-end (photo-detector and
transimpedance amplifier) is reduced at low input bit rates.
The maximum bandwidth is selected by default at
power-up. The bandwidth can be set independently of
input bit rate using bits AMPOCT in I2C-bus register
LIMCNF (address C2H).
In I2C-bus control mode, the chip is configured using the
I2C-bus pins SDA and SCL. During I2C-bus read or write
actions, pin CS must be HIGH. When pin CS is LOW, the
programmed configuration remains active but signals SDA
and SCL are ignored. This allows several TZA3012AHWs
in the application with the same I2C-bus address to be
selected separately. The I2C-bus address of the
TZA3012AHW is shown in Table 2.
Table 2
I2C-bus address of the TZA3012AHW
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
1
0
0
0
0
X
Normally, only one limiter is activated at any one time so
that only the RF signal applied to the active channel is
routed to the DCR. The unused limiter automatically enters
a sleep mode to reduce power dissipation. A limiter is
selected by pin INSEL as shown in Table 4.
The function and content of the I2C-bus registers are
described in Section “I2C-bus registers”. Some functions in
the TZA3012AHW can be controlled either by the I2C-bus
or a designated pin. The method required is specified by
an extra bit named I2C<pin name> in the corresponding
I2C-bus register, for example, bit I2CDMXR in
register DMXCNF. The default is enable by pin.
Table 4
PIN
INSEL
If the application has no I2C-bus control, the IC must
operate with reduced functionality in pre-programmed
mode. In pre-programmed mode, pins DR0 to DR2 are
standard CMOS inputs that allow the selection of up to
eight pre-programmed bit rates using an external
reference clock frequency of typically 19.44 MHz;
see Table 3.
2003 May 21
Truth table for pin INSEL
SELECTED CHANNEL
SELECTED
INPUTS
HIGH
channel 1; limiter 1 active
IN1 and IN1Q
LOW
channel 2; limiter 2 active
IN2 and IN2Q
A limiter can also be selected by setting bit I2CINSEL in
I2C-bus register LIMCNF, and specifying bit INSEL as
shown in Table 5.
7
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
Table 5
TZA3012AHW
Received Signal Strength Indicator (RSSI)
Channel selection
The strength of signal present at each RF input is
measured by a logarithmic detector and represented by an
analog voltage at pins RSSI1 and RSSI2 for channels 1
and 2, respectively. The RSSI has a sensitivity of
17 mV/dB typical for an input voltage swing Vi(p-p) range of
5 mV to 500 mV; see Fig.4. RSSI output voltage VRSSI can
be calculated using the following formula:
I2C BIT
PIN
INSEL
INSEL
I2CINSEL
SELECTED CHANNEL
0
X
LOW
channel 2; limiter 2 active
0
X
HIGH
channel 1; limiter 1 active
1
0
X
channel 2; limiter 2 active
1
1
X
channel 1; limiter 1 active
V i(p-p)
V RSSI = V RSSI(32 mV) + S RSSI × 20log ----------------32 mV
Both limiters can be made active by setting bit BOTHON in
I2C-bus register LIMCNF. This allows ‘hot switching’,
where the second channel can be selected quickly if the
first channel loses its signal. Note that even when both
limiters are active, only one channel is selected at any
time; see Table 6.
Both logarithmic detectors are always active to allow the
input with the strongest signal to be selected.
Loss Of Signal (LOS) indicator
In addition to the analog RSSI output, the TZA3012AHW
also provides a digital LOS indication output on pins LOS1
and LOS2. The RSSI level is internally compared with a
LOS threshold voltage level, which can be set either by an
external resistor connected to pins LOSTH1 and LOSTH2,
or by using an internal D/A converter. The method used is
determined by bit I2CREFLVL1 in I2C-bus
register LIMLOS1CNF (address BDH) for channel 1, or
bit I2CREFLVL2 in I2C-bus register LIMLOS2CNF
(address BFH) for channel 2. Using the internal
D/A converter requires a value representing the threshold
voltage to be programmed into I2C-bus registers
LIMLOS1TH (address BCH) or LIMLOS2TH
(address BEH). This allows separate LOS threshold levels
to be specified per channel.
When only one limiter is active, the time taken to
deactivate its limiter and activate the limiter in the other
channel takes 4 µs typical.
Table 6
Channel and limiter selection with bit BOTHON
I2C BIT
PIN
BOTHON INSEL
SELECTED
CHANNEL
SELECTED
INPUTS
0
HIGH
channel 1;
limiter 1 active
IN1 and IN1Q
1
HIGH
channel 1;
limiters 1 and 2
active
IN1 and IN1Q
0
LOW
channel 2;
limiter 2 active
IN2 and IN2Q
1
LOW
channel 2;
limiters 1 and 2
active
IN2 and IN2Q
handbook, halfpage
If the received signal strength is below the default
hysteresis value of 3 dB, the corresponding LOS pin will
be HIGH. Alternative hysteresis values from 0 to 7 dB in
steps of 1 dB can be specified using bits HYS1 and HYS2
in I2C-bus registers LIMLOS1CNF and LIMLOS2CNF
respectively. If required, the polarity of the LOS indicator
outputs can be inverted by setting bits LOS1POL
and LOS2POL in the same registers. The LOS function
can be disabled by setting bit LOS1 or LOS2 to logic 0 for
channel 1 or channel 2 respectively.
VCCA
IN
50 Ω
The LOS function is also available using I2C-bus registers
INTERRUPT and STATUS; see Sections “Interrupt
register” and “Status register”. If bit LOS1 or LOS2 in
register INTERRUPT is not masked, a loss of signal
condition will generate an interrupt signal at pin LOS1 or
pin LOS2. Bits LOS1 and LOS2 are masked by default;
see Section “Interrupt generation”.
50 Ω
INQ
VEE
MDB385
Fig.3
Limiter input termination configuration.
2003 May 21
8
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
MBL555
handbook, full pagewidth
1.2
VRSSI
(V)
SRSSI
0.9
0.6
0.3
0
5
10
32
300
102
500
103
Vi(p-p) (mV)
Fig.4 VRSSI as a function of Vi(p-p).
Setting LOSTH reference level by external resistor
If the internal D/A converter is not used, the reference
voltage level on pin LOSTH1 (or LOSTH2) can be set by
connecting an external resistor (R2) from the relevant pin
to ground. The voltage on the pin is determined by the ratio
between R2 and R1; see Fig.5. For resistor R1 a value of
10 to 20 kΩ is recommended, giving a current of
120 to 60 µA.
VCCA
RSSI
R2
The LOSTH voltage equals -------- × V ref
R1
LOS
Voltage Vref represents a temperature stabilized and
accurate reference voltage of 1.2 V. The minimum
threshold level corresponds to 0 V and the maximum to
1.2 V. Hence, the value of R2 may not be higher than R1.
The accuracy of the LOSTH voltage depends mainly on
carefully choosing the values of the two external resistors.
1.2 V
Vref
RREF
I
R1
10 kΩ
LOSTH1
LOSTH2
R2
GND
MGU318
Instead of using resistors (R1 and R2) to set the LOS
threshold, an accurate external voltage source can also be
used.
If no resistor is connected to LOSTH1 (or LOSTH2), or an
external voltage higher than 2⁄3 × VCC is applied to the pin,
the LOS detection circuit (including the RSSI reading for
that channel) is automatically switched off to reduce power
dissipation. This ‘auto power off’ only works if UI = VEE, i.e.
manual control of the TZA3012AHW. In I2C-bus mode,
several I2C-bus bits allow flexible configuration.
2003 May 21
LOS
compare
Fig.5
9
Setting the LOSTH reference level by
external resistors.
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
The FWD is a conventional frequency locked PLL, which,
at power-up, initially applies a coarse adjustment to the
free running VCO frequency. The FWD checks the VCO
frequency, which has to be within a 1000 ppm (parts per
million) window around the desired frequency. The FWD
then compares the divided VCO frequency (also available
on pins PRSCLO and PRSCLOQ) with the reference
frequency, usually 19.44 MHz, on pins CREF and
CREFQ. If the VCO frequency is found to be outside this
window, the FWD disables the Data Phase Detector
(DPD) and forces the VCO to a frequency within the
window. As soon as the ‘in window’ condition occurs,
which is visible on pin INWINDOW, the DPD starts
acquiring lock on the incoming bit stream. Since the VCO
frequency is very close to the expected bit rate, the phase
acquisition will be almost instantaneous, resulting in quick
phase lock to the incoming data stream.
Slice level adjustment
The TZA3012AHW uses a slice level circuit to counter the
affects of asymmetrical noise that can occur in some
optical transmission systems. The slice level circuit
improves pre-detection signal-to-noise ratio by adding a
DC offset to the input signal. The offset required will
depend on the characteristics of the photo detector in the
optical front-end and the amplitude of the received signal.
The slice level is adjustable between −50 mV and +50 mV
in 512 steps of 0.2 mV.
The slice level function is enabled by setting bits SL1
and SL2 in I2C-bus registers LIMLOS1CNF
(address BDH) and LIMLOS2CNF (address BFH) for
channel 1 and channel 2 respectively. The slice level is set
by sign and magnitude convention. The sign, either
positive or negative (polarity), is set by I2C-bus
bits SL1SGN and SL2SGN. The magnitude, 0 to 50 mV in
256 steps, is set by an 8-bit D/A converter via I2C-bus
register LIMSLICE1 (address C0H) and
LIMSLICE2 (C1H) for channel 1 and channel 2
respectively.
Although the VCO is now locked to the incoming bit
stream, the FWD is still supervising the VCO frequency
and takes over control if the VCO drifts outside the
predefined frequency window. This might occur during a
‘loss of signal’ situation. Due to the FWD, the VCO
frequency is always close to the required bit rate, enabling
rapid phase acquisition if the lost input signal returns.
The introduced offset is not present at inputs IN and INQ
to prevent the logarithmic RSSI detector from detecting the
offset as a valid input signal.
The default frequency window of 1000 ppm means that
the reference frequency does not need to be highly
accurate or stable. Any crystal-based oscillator that
generates a reasonably accurate frequency, such
as 100 ppm, is suitable.
Data and Clock Recovery (DCR)
The TZA3012AHW recovers the clock and data contents
from the incoming bit stream; see Fig.6. The DCR uses a
combined frequency and phase locking scheme, providing
reliable and quick data acquisition at any bit rate between
30 Mbits/s and 3.2 Gbits/s. The DCR contains a Voltage
Controlled Oscillator (VCO), Frequency Window Detector
(FWD), octave divider M, main divider N, fractional
divider K, reference divider R, and a phase detector.
The internal VCO is phase-locked to a reference clock
signal of typically 19.44 MHz applied to pins CREF and
CREFQ.
2003 May 21
10
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
handbook, full pagewidth
TZA3012AHW
LIMITING
AMPLIFIER
DATA IN
DATA PHASE
DETECTOR
N [8:0]
K [21:0]
9
FRACTION
CALCULATOR
VOLTAGE
CONTROLLED
OSCILLATOR
(VCO)
÷R
to
DEMULTIPLEXER
CHARGE PUMP
LOOP FILTER
+
÷N
REFERENCE
DIVIDER
CREF(Q)
COUT(Q)
÷M
22
MAIN
DIVIDER
DOUT(Q)
up
down
OCTAVE
DIVIDER
RECOVERED DATA
RECOVERED CLOCK
up
FREQUENCY
WINDOW
DETECTOR
down
CHARGE PUMP
REFERENCE
INPUT
PRESCALER
OUTPUT
PRSCLO(Q)
MGU346
Fig.6 Block diagram of data and clock recovery.
I2C-bus control operation allows any one of four possible
reference clock frequency ranges to be selected by
programming reference divider R using bits REFDIV in
I2C-bus register DCRCNF (address B6 H).
The REFDIV bit settings, reference clock frequency
ranges, and division factor are shown in Table 7.
The reference frequency is always divided internally to the
lowest range of 18 to 21 MHz.
Fractional N synthesizer
The DCR uses a fractional N-type synthesizer to provide
the A-rate functionality that allows the DCR to synchronize
to incoming data, regardless of its bit rate.
The DCR has a 22-bit fractional N capability which allows
any combination of bit rate and reference frequency
between 18 × R and 21 × R MHz, where R is the reference
division factor. The LSB (bit k[0]) of the fractional divider,
should be set to logic 1 to avoid limit cycles. These are
cycles of less than maximum length that generate spurs in
the frequency spectrum. This leaves 21 bits (k[21:1])
available for programming the fraction, allowing a
resolution frequency of approximately 10 Hz at a fixed
reference frequency.
Table 7
Truth table for bits REFDIV in I2C-bus register
DCRCNF
REFDIV
R
DIVISION
FACTOR
SDH/SONET
REFERENCE
FREQUENCY
(MHz)
REFERENCE
FREQUENCY
RANGE
(MHz)
Programming the reference clock
00
1
19.44
18 to 21
Pre-programmed operation requires a reference clock
frequency of between 18 and 21 MHz connected to
pins CREF and CREFQ. However, to obtain the bit rates in
Table 3, the reference clock frequency must be
19.44 MHz. For SDH/SONET applications, a reference
clock frequency of 19.44 × R MHz is preferred.
01
2
38.88
36 to 42
10
4
77.76
72 to 84
11
8
155.52
144 to 168
2003 May 21
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Programming the DCR
Table 9
The following dividers are used to program the clock
synthesizer: the main divider N, the fractional divider K
and the octave divider M.
28.125 56.25
4
112.5
3
225
2
450
1
900
0
1800
3200
Mbits/s
MGU316
Fig.7
Table 8
Allocation of octaves for common bit rates
shown on a logarithmic scale.
Octave designation and M division factor
LOWEST
BIT RATE
(Mbits/s)
HIGHEST
BIT RATE
(Mbits/s)
OCTAVE
BIT RATE
(Mbits/s)
OCTAVE
10GE
3125.00
0
2xHDTV
2970.00
0
STM16/OC48 + FEC
2666.06
0
STM16/OC48
2488.32
0
DV-6000
2380.00
0
PROTOCOL
The division factor for M is obtained by first determining in
which octave the desired bit rate belongs as shown in
Figure 7 and Tables 8 and 9.
handbook, 6halfpage 5
Common optical transmission protocols and
corresponding octaves
M DIVISION
FACTOR
Fibre Channel
2125.00
0
HDTV
1485.00
1
D-1 Video
1380.00
1
DV-6010
1300.00
1
Gigabit Ethernet (GE)
1250.00
1
Fibre Channel
1062.50
1
OptiConnect
1062.50
1
ISC
1062.50
1
STM4/OC12
622.08
2
DV-6400
595.00
2
Fibre Channel
425.00
3
OptiConnect
265.63
3
Fibre Channel
212.50
4
ESCON/SBCON
200.00
4
STM1/OC3
155.52
4
FDDI
125.00
4
Fast Ethernet
125.00
4
106.25
5
51.84
6
1800
3200
0
1
Fibre Channel
900
1800
1
2
OC1
450
900
2
4
225
450
3
8
112.5
225
4
16
56.25
112.5
5
32
28.125
56.25
6
64
2003 May 21
Once the octave and M division factor are known, the
division factors for N and K can be calculated for a given
reference frequency using the Flowchart in Fig.8.
12
Philips Semiconductors
Product specification
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A-rate fibre optic receiver
handbook, full pagewidth
TZA3012AHW
CALCULATE
N and K
n, k =
bit rate × M × R
f ref
n is integer part
k is fractional part
yes
k=0?
no
NILFRAC = 1
NILFRAC = 0
0.25 < k < 0.75
no
yes
no
k ≤ 0.25 ?
yes
k ≥ 0.75 ?
no
yes
N=2×n
N=2×n
k = k + 0.5
k = k − 0.5
N=2×n−1
N=2×n+1
j = 21
k=k×2
k≥1?
no
yes
Kj = 1
Kj = 0
decimal to binary
conversion of
fractional part
k=k−1
j=j−1
j=0?
no
yes
Kj = 1
Write K j into registers B3H, B4H and B5H
Convert N to binary
and write into registers B1H and B2H
END
MGW570
Fig.8 Flowchart for calculating N and K for the required bit rate.
2003 May 21
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Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
The following examples refer to the flowchart in Fig.8.
Example 1: An SDH or SONET link has a bit rate of 2488.32 Mbits/s (STM16/OC48) that corresponds to octave 0 and
an M division factor of 1. If the reference frequency fref at pins CREF and CREFQ is 77.76 MHz, the division factor R is
required to be 4. The initial values for integer n and fractional part k are calculated using the equation:
2488.32 Mbits × 1 × 4
bit rate × M × R
n.k = ---------------------------------------- = --------------------------------------------------------- = 128
77.76 MHz
f ref
In this example, n = 128 and k = 0. Since k is 0, fractional functionality is not required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 1; see Table 19. N = n × 2 = 256 with no further correction required. The resulting
values of R = 4, M = 1 and N = 256 are set by I2C-bus registers DCRCNF (Table 22), DIVCNF (Table 16), MAINDIV1
(Table 17) and MAINDIV0 (Table 18).
Example 2: An SDH or SONET link has a bit rate of 2666.057143 Mbits/s (15/14 × 2488.32 Mbits/s) (STM16/OC48 link
with FEC) that corresponds to octave 0 and an M division factor of 1. If fref at pins CREF and CREFQ is 38.88 MHz, the
division factor R is required to be 2. The values for n and k are calculated as follows:
bit rate × M × R
2666.05714283 Mbits × 1 × 2
n.k = ---------------------------------------- = ----------------------------------------------------------------------------- = 137.1428571
f ref
38.88 MHz
In this example, n = 137 and k = 0.1428571. Fractional functionality is required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 0. Since k is less than 0.25, k is corrected to k = k + 0.5 = 0.6428571, and N is
corrected to N = n × 2 − 1 = 273. The resulting values of R = 2, M = 1, N = 273 and K = 10 1001 0010 0100 1001 0011
are set by I2C-bus registers DCRCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18),
FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21). The FEC bit rate is usually rounded up to
2666.06 Mbits/s, which actually gives a different value for k than in this example.
Example 3: A Fibre Channel link has a bit rate of 1062.50 Mbits/s that corresponds to octave 1 and an M division factor
of 2. If fref at pins CREF and CREFQ is 19.44 MHz, the division factor R is required to be 1. The values for n and k are
1062.50 Mbits × 2 × 1
bit rate × M × R
calculated as follows: n.k = ---------------------------------------- = --------------------------------------------------------- = 109.3106996
19.44 MHz
f ref
In this example, n = 109 and k = 0.3107. Fractional functionality is required, so bit NILFRAC in I2C-bus register FRACN2
should be set to logic 0. Since k is greater than 0.25 and less than 0.75, k does not need to be corrected. N is corrected
to N = n × 2 = 218. The resulting values of R = 1, M = 2, N = 218 and K = 01 0011 1110 0010 1000 0001 are set by
I2C-bus registers DCRCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18), FRACN2
(Table 19), FRACN1 (Table 20) and FRACN0 (Table 21).
Example 4: A non standard transmission link has a bit rate of 3012 Mbits/s that corresponds to octave 0 and an
M division factor of 1. If fref at pins CREF and CREFQ is 20.50 MHz, the division factor R is required to be 1. The values
bit rate × M × R
3012 Mbits × 1 × 1
for n and k are calculated as follows: n.k = ---------------------------------------- = ------------------------------------------------ = 146.9268293
f ref
20.50 MHz
In this example, n = 146 and k = 0.9268293. Fractional functionality is required, so bit NILFRAC in I2C-bus
register FRACN2 should be set to logic 0. Since k is greater than 0.75, k is corrected to k = k − 0.5 = 0.4268293, and N
is corrected to N = n × 2 + 1 = 293. The resulting values of R = 1, M = 1, N = 293 and K = 01 1011 0101 0001 0010 1011
are set by I2C-bus registers DCRCNF (Table 22), DIVCNF (Table 16), MAINDIV1 (Table 17), MAINDIV0 (Table 18),
FRACN2 (Table 19), FRACN1 (Table 20) and FRACN0 (Table 21).
If the I2C-bus is not used, the clock synthesizer can be set up for the eight pre-programmed bit rates shown in Table 3,
by pins DR0, DR1 and DR2 using an external reference clock frequency of 19.44 MHz.
2003 May 21
14
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Prescaler outputs
Accurate clock generation during loss of signal
The frequency of prescaler outputs PRSCLO and
PRSCLOQ is the VCO frequency divided by a ratio of N.K.
If the synthesizer is in-lock, the frequency of the prescaler
output is equal to the reference frequency at CREF and
CREFQ divided by R which also corresponds to the
recovered data rate. This provides an accurate reference
that can be used by other phase locked loops in the
application. If required, the polarity of the prescaler outputs
can be inverted by setting bit PRSCLOINV in I2C-bus
register IOCNF0 (address CBH) to logic 1. If no prescaler
information is required, its output can be disabled by
setting bit PRSCLOEN in the same register to logic 0.
In addition, the prescaler output can be set for type of
output, termination mode and signal amplitude. These
parameter settings also apply to the parallel output
clock POCLK and POCLKQ and parity error
output PARERR and PARERRQ. For programming
details, These parameter settings also apply to the parallel
demultiplexer outputs. For programming details;
see Section “Configuring the parallel interface”.
During a loss of signal, there is no data present for clock
recovery to use. A frequency acquisition window size of
zero will make the recovered clock frequency equal to the
reference frequency, including its tolerance.
Setting bit AUTOWIN in I2C-bus register DCRCNF makes
the window size dependent on the LOS status of the active
limiter channel. If the optical input signal is lost, the FWD
automatically selects the 0 ppm window size, so that the
VCO is directly phase-locked to the reference signal.
This ensures that the output clock signal remains stable
during loss of signal, and automatically reverts to normal
DCR operation when the input signal returns.
Note that the accuracy of the reference frequency must be
better than 20 ppm for the application to comply with ITU-T
recommendations.
INWINDOW signal
The status of the FWD circuit is indicated by the level on
pin INWINDOW. A HIGH level indicates that the VCO is
within the defined frequency acquisition window size, and
a LOW level indicates that the VCO is outside the defined
window size. The status of the FWD circuit is also
indicated by bit INWINDOW in I2C-bus
registers INTERRUPT and STATUS.
Programming the FWD
The default window for frequency acquisition is 1000 ppm
around the desired bit rate. The size of window determines
the amount of variation in the frequency of the applied
reference clock, and VCO, that is tolerated by the FWD.
The window size can be set to other predefined values
between 250 and 2000 ppm by bits WINDOWSIZE in
I2C-bus register DCRCNF (address B6H).
Jitter performance
The clock synthesizer is optimized for minimum jitter
generation. For all SDH/SONET bit rates, the generated
jitter complies with ITU-T standard G.958 using a pure
reference clock. To ensure negligible loss of performance
when a reference clock is used, the reference signal
should have a single sideband phase noise of better than
−140 dBc/Hz, at frequencies of more than 12 kHz from the
carrier. If reference divider R is used, this negative value is
allowed to increase at approximately 20 × log (R).
An additional feature allows the size of the frequency
acquisition window to be set to 0 ppm, which effectively
removes the ‘dead zone’ from the FWD, converting it to a
classical PLL. The VCO will then be directly phase-locked
to the reference signal instead of the incoming bit stream.
This is implemented by either applying a LOW level to
pin WINSIZE, or by setting bit WINSIZE to logic 0 and
bit I2CWINSIZE to logic 1 in I2C-bus register DCRCNF;
see Table 10.
Demultiplexer
The demultiplexer converts the serial input bit stream to
parallel formats of 1:16, 1:10, 1:8, and 1:4. The output data
is available on a scalable bus, of which the output driver
type can be either LVPECL or CML. In addition to the
deserializing function, the demultiplexer comprises a parity
calculator and a frame header detection circuit.
A calculated parity of EVEN is output at pins PARITY and
PARITYQ. A detected frame header pattern in the data
stream results in a 1 clock cycle wide pulse on outputs FP
and FPQ.
Table 10 Truth table for pin WINSIZE
WINSIZE
WINDOW SIZE (ppm)
LOW
0
HIGH
1000
2003 May 21
15
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
depends on the demultiplexing ratio selected by
pins DMXR0 and DMXR1 or by bits DMXR in I2C-bus
register DMXCNF (address A8 H). Any unused parallel
data bus outputs are disabled. The configuration settings
and active outputs for each demultiplexing ratio are shown
in Table 11.
Making pin ENBA HIGH automatically aligns the parallel
output into logical bytes or words. The same function is
implemented by setting bit ENBA in I2C-bus
register DMXCNF (address A8H).
To support most commonly used transmission systems
and protocols, the demultiplexing ratio can be set to 1:16,
1:10, 1:8, and 1:4, and the frame header pattern
programmed to any 32 or 10-bit pattern; see Section
“Frame detection”.
In I2C-bus control mode, the default demultiplexing ratio
is 16:1.
To allow optimum layout connectivity, the pin designations
of the parallel data bus bits can be reversed so that the
default designated pin for D15 (MSB) is exchanged with
the default designated pin for D0 (LSB). This is
implemented by bit BUSSWAP in I2C-bus
register DMXCNF (address A8H).
If required, the demultiplexer output can be forced into a
fixed logic 0 state by bit DMXMUTE in I2C-bus
register DMXCNF.
Adjustable demultiplexing ratio
For optimum layout connectivity, the physical positions of
parallel data bus pins D00 to D15 and D00Q to D15Q on
the chip are located either side of pin VEE (pin 63).
The number of parallel data bus outputs that are used
The highest supported speed for the parallel data bus is
400 Mbits/s. Therefore a demultiplexing ratio of 4:1 will
support bit rates of up to 1.6 Gbits/s.
Table 11 Setting demultiplexing ratio
PIN DMXR1
PIN DMXR0
BITS DMXR
(REG DMXCNF)
DEMULTIPLEXING
RATIO
ACTIVE OUTPUTS
LSB to MSB
LOW
LOW
00
1:4
D06 to D09
LOW
HIGH
01
1:8
D04 to D11
HIGH
LOW
10
1:10
D03 to D12
HIGH
HIGH
11
1:16
D00 to D15
Frame detection
Any bit position can be programmed with a ‘don’t care’ to
give a frame header pattern that is either much shorter
than 32 or 10 bits, or has gaps. The “don’t care” bits are
produced by programming a pattern into I2C-bus registers
HEADERX0 to HEADERX3 which is used to mask the
programmed frame header pattern as shown in the
example Fig.9.
Byte alignment is enabled if the Enable Byte Alignment
input (pin ENBA) is HIGH, or if bit I2CENBA and bit ENBA
are both logic 1 in I2C-bus register DMXCNF
(address A8H). Whenever the incoming data has a 32-bit
or 10-bit sequence that matches the programmed frame
header pattern, the data is formatted into logical bytes or
words, and a frame pulse is generated on differential
outputs FP and FPQ. Any frame header pattern can be
programmed in I2C-bus registers HEADER0
to HEADER3.
2003 May 21
The default frame header pattern is F6F62828H,
corresponding to the middle section of the standard
SDH/SONET frame header (the last two A1 bytes plus the
first two A2 bytes).
16
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
MSB HEADER
handbook, full pagewidth
LSB HEADER
BIT1
BIT32
HEADER3
0
0
0
1
0
1
1
1
0
1
1
0
0
0
1
0
HEADER0
HEADERX3
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
HEADERX0
X
0
0
1
0
X
1
1
0
1
1
0
0
0
X
X
received
data
data stream
MGU548
‘X’ = “don’t care”
‘MSB’ = Most Significant Byte.
Fig.9 Example of programming the frame header pattern.
If ENBA is LOW, no active alignment takes place.
However, if the frame header pattern occurs in the
formatted data, a frame pulse will still be output on pins FP
and FPQ.
Receiver framing in SDH/SONET applications
Figure 10 shows a typical SDH/SONET reframe sequence
involving byte alignment. Frame and byte boundary
detection is enabled on the rising edge of ENBA and
remains enabled while ENBA is HIGH. Boundaries are
recognized on receipt of the second A2 byte and FP goes
HIGH for one POCLK cycle.
For 10-bit oriented protocols, such as Gigabit Ethernet,
the frame header detection operates on a 10-bit pattern
sequence. These 10 bits should be programmed into
I2C-bus registers HEADER3 and the two MSBs of
HEADER2; the remaining 22 bits are ignored. A ‘don’t
care’ pattern overlay can be programmed in I2C-bus
register HEADERX3 and the two MSBs of HEADERX2.
In 1:16 mode, the first two A2 bytes in the frame header
are the first data word to be reported with the correct
alignment on the outgoing data bus (D00 to D15). In 1:8
mode the first A2 byte is the first aligned data byte (D04 to
D11), while in 1:4 mode the most significant nibble of the
first A2 byte is the first aligned data (D06 to D09).
Since some 10-bit oriented protocols use a DC balancing
code, the detection pattern could appear in
complementary form in the data stream. By setting
bit CMPL in I2C-bus register DMXCNF (address A8H), the
header detection scans the data stream for both the
programmed pattern and its complement simultaneously.
Either occurrence produces a ‘byte’ alignment and a
corresponding frame pulse on pins FP and FPQ.
When interfacing with a section terminating device, ENBA
must remain HIGH for a full frame after the initial frame
pulse. This is to allow the section terminating device to
verify internally that frame and byte alignment are correct;
see Fig.11. Byte boundary detection is disabled on the first
FP pulse after ENBA has gone LOW.
The default pattern (after power-up) is ‘0011111010’ or
K28.5 character plus alternating 010. This is the only
pattern containing five consecutive bits of the same sign.
2003 May 21
Figure 12 shows frame and byte boundary detection
activated on the rising edge of ENBA, and deactivated by
the first FP pulse after ENBA has gone LOW.
17
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
handbook, full pagewidth
TZA3012AHW
serial clock
ENBA
32 bits
serial data
A1
A1
A1
A2
A2
invalid data
valid data
1 : 16
A2
D00 to D15
(1:16)
A2
28 28
POCLK
(1:16)
FP
(1:16)
1:4
D06 to D09
(1:4)
A2
2
A2
8
2
8
POCLK
(1:4)
FP
(1:4)
MGU550
Fig.10 Frame and byte detection in SDH/SONET application.
handbook, halfpage
boundary detection enabled
handbook, halfpage
ENBA
boundary detection
enabled
ENBA
FP
FP
MGU340
MGU341
Fig.11 ENBA timing with section terminating
device.
2003 May 21
Fig.12 Alternate ENBA timing.
18
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Parity generation
Loop mode I/Os
Outputs PARITY and PARITYQ provide the even parity of
the byte/word that is currently available on the parallel bus.
Odd parity can be output by setting bit PARINV to logic 1
in I2C-bus register IOCNF2 (address C9H). If no parity
output is required, and/or to reduce output power, set
bit PAREN, in the same register, to logic 0.
In line loopback mode, the internal data and clock routing
switch routes the received serial data and recovered clock
to outputs DOUT, DOUTQ COUT and COUTQ instead of
to the demultiplexer. Line loopback mode is activated by a
LOW level on pin ENLOUTQ. Line loopback mode is also
selected by setting bit ENLOOPOUT and
bit I2CLOOPMODE in I2C-bus register DIVCNF
(address B0H).
Configuring the parallel interface
There are several options for configuring the parallel
interface which comprises the parallel data bus and
associated outputs. The options for parallel data
output D00 to D15 and D00Q to D15Q, parallel clock
output POCLK and POCLKQ, parity output PARITY and
PARITYQ, frame pulse output FP and FPQ, and prescaler
output PRSCLO and PRSCLOQ are: output driver type,
termination mode, output amplitude, signal polarity, and
selective enabling or disabling. The parallel data bus pin
designations can also be reversed and/or muted. These
options are set in I2C-bus registers IOCNF3
(address C8H) and IOCNF2 (address C9H), IOCNF0
(address CBH) and DMXCNF (address A8H).
In diagnostic loopback mode, the demultiplexer selects the
serial data and clock signals at loop mode input
pins DLOOP, DLOOPQ and CLOOP, CLOOPQ instead of
from the DCR. Diagnostic loopback mode is activated by a
LOW level on pin ENLINQ. Diagnostic loopback mode is
also selected by setting bit ENLOOPIN and
bit I2CLOOPMODE in I2C-bus register DIVCNF
(address B0H).
Configuring the RF I/Os
The polarity of specific RF serial data and clock I/O signals
can be inverted using I2C-bus register IOCNF1
(address CAH).
I2C-bus register IOCNF3, bit MFOUTMODE selects either
the CML or LVPECL output driver. The default is LVPECL.
Bit MFOUTTERM sets the output termination mode to
either standard LVPECL or floating termination, or in CML
mode, to either DC or AC-coupled. In all cases, bits MFS
adjust the amplitude. The default output amplitude is
800 mV (p-p) single-ended.
To allow easier connection to other ICs, the pin
designations for input data can be exchanged with the pin
designations for input clock. The pin designations for
output data and output clock can also be exchanged.
The default pin designations for Loop mode input data and
clock are exchanged by setting bit CDINSWAP in I2C-bus
register IOCNF1 so that signals at pins CLOOP and
CLOOPQ are treated as data and signals at pins DLOOP
and DLOOPQ are treated as clock.
In I2C-bus register IOCNF2, setting bit PDEN to logic 0
disables the parallel interface output driver. This is not the
same effect as setting bit DMXMUTE in I2C-bus
register DMXCNF (address A8H), which forces the
outputs to a logic 0 state. Setting bit PDINV to logic 1 in
I2C-bus register IOCNF2 (address C9H) inverts the
polarity of the parallel data. Setting bit POCLKINV to
logic 1 in the same register inverts the clock output so that
the clock edge is shifted by half a clock cycle, changing the
rising edge to a falling edge. This function can be used to
resolve a parallel data bus timing problem. The parallel
bus clock is disabled by setting bit POCLKEN to logic 0 in
the same register. Control bits in the same register and in
register IOCNF0 (address CBH) also apply the same
options to the parity, frame pulse and prescaler outputs.
2003 May 21
The default pin designations for Loop mode output data
and clock are exchanged by setting bit CDOUTSWAP in
I2C-bus register IOCNF1 so that signals at pins COUT and
COUTQ are treated as data and signals at pins DOUT and
DOUTQ are treated as clock.
The amplitude of the RF serial output signals in CML drive
mode, is adjustable (in 16 steps) between 60 mV (p-p) and
1000 mV (p-p), single-ended, controlled by bits RFS
and RFSWING in I2C-bus register IOCNF0
(address CBH). The default amplitude is 80 mV (p-p),
single-ended. The RF serial outputs are AC-coupled.
19
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
CMOS control inputs
Status register
CMOS control inputs UI, INSEL, WINSIZE, DMXR0,
DMXR1, ENBA, ENLOUTQ, ENLINQ and CS(DR0) have
an internal pull-up resistor so that these pins go HIGH
when open circuit, and only go LOW when deliberately
forced. This is also true for pins DR1 and DR2 in
pre-programmed mode (pin UI is LOW). In I2C-bus control
mode (pin UI is HIGH), pins SCL and SDA comply with the
I2C-bus interface standard.
The current status of the conditions that are recorded by
register INTERRUPT are indicated by setting the
appropriate bit(s) in I2C-bus register STATUS
(address 01H). A bit is set only for the period that the
condition is active and resets when the condition clears.
Register STATUS is polled by an I2C-bus read action.
Interrupt generation
An interrupt is generated if an interrupt condition sets a bit
in I2C-bus register INTERRUPT (address 00H) and if the
bit is not masked by I2C-bus register INTMASK
(address CCH). Only the high junction temperature
interrupt bit is not masked by default. A generated interrupt
is indicated by an active logic level at pin INT. The active
output level used is set by bit INTPOL in I2C-bus
register INTMASK. The default is an active LOW level.
Bit INTOUT sets the output mode at pin INT to either
open-drain or to standard CMOS. The default is
open-drain. An active LOW output in open-drain mode
allows several receivers to be connected together, and
requires only one 3.3 kΩ pull-up resistor.
Power supply connections
Four separate supply domains (VDD, VCCD, VCCO and
VCCA) provide isolation between the various functional
blocks. Each supply domain should be connected to a
common VCC using a separate filter. All supply pins,
including the exposed die pad, must be connected.
The die pad connection to ground must have the lowest
possible inductance. Since the die pad is also used as the
main ground return of the chip, this connection must also
have a low DC impedance. The voltage supply levels
should be in accordance with the values specified in
Chapters “Characteristics” and “Limiting values”.
All external components should be surface mounted, with
a preferable size of 0603 or smaller. The components
must be mounted as close to the IC as possible.
Interrupt register
The following events are recorded by setting the
appropriate bit(s) in I2C-bus register INTERRUPT
(address 00 H):
• Loss of signal on channel 1
• Loss of signal on channel 2
• DCR frequency locked or unlocked
• Limiter channel switching enabled or disabled
• High junction temperature.
When register INTERRUPT is polled by an I2C-bus read
action, any set bits are reset. If a condition is still active, the
corresponding bit remains set.
2003 May 21
20
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line
(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
Bit transfer
Refer to Fig.13. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during
the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.13 Bit transfer.
Start and stop conditions
Refer to Fig.14. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data
line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the
clock is HIGH is defined as the stop condition (P).
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
Fig.14 Definition of start and stop conditions.
2003 May 21
21
MBC622
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
System configuration
Refer to Fig.15. A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’.
The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER
TRANSMITTER /
RECEIVER
SLAVE
TRANSMITTER /
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER /
RECEIVER
MBA605
Fig.15 System configuration.
Acknowledge
Refer to Fig.16. Only one data byte is transferred between the start and stop conditions during a write from the transmitter
to the receiver. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put
on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave
receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into
consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable
the master to generate a stop condition; see Fig.19.
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.16 Acknowledgment on the I2C-bus.
2003 May 21
22
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
I2C-BUS PROTOCOL
Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The address byte is
sent after the start condition.
The master transmitter/receiver either reads from the read-registers or writes to the write-registers. It is not possible to
read from and write to the same register. Figure 17 shows how the slave and register address bytes are defined.
handbook, full pagewidth
MSB
LSB
MSB
R/W
1
LSB
Slave address
Register address
MDB070
Fig.17 Slave and register addresses.
Read/Write protocols
The protocol for writing to a single register is shown in Fig.18. The transmitter sends the address of the slave device,
waits for an acknowledge from the slave, sends register address, waits for an acknowledge from the slave, sends data
byte, waits for an acknowledge from the slave, followed by a stop condition.
acknowledge
from slave
handbook, full pagewidth
acknowledge
from slave
R/W MSB
S
SLAVE
ADDRESS
0 A 1
acknowledge
from slave
MSB
REGISTER
ADDRESS
A
LSB
DATA
A
P
one byte transferred
MDB386
Fig.18 Write protocol.
The protocol for reading one or more registers is shown in Fig.19. The receiver sends the address of the slave device,
waits for an acknowledge from the slave, receives data byte(s) from the slave (the TZA3012AHW starts sending data
after asserting an acknowledge), after receiving the data, the receiver sends an acknowledge or, if finished, a
not-acknowledge, followed by a stop condition.
2003 May 21
23
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
handbook, full pagewidth
TZA3012AHW
acknowledge
from master (1)
acknowledge
from slave
R/W
S
SLAVE
ADDRESS
1 A
MSB
acknowledge
from master (1)
LSB
DATA
acknowledge
from master (1)
MSB
A
first byte
A
LSB
DATA
A
P
last byte
MDB387
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave.
Fig.19 Read protocol.
I2C-bus registers
The I2C-bus registers are accessed in I2C-bus control mode by setting pin UI HIGH or leaving pin UI open circuit.
Address and read/write data are transferred serially via pin SDA and clocked via pin SCL when pin CS (chip select) is
HIGH. The I2C-bus registers are listed in Table 12.
2003 May 21
24
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 12 I2C-bus registers
ADDRESS
(HEX)(1)
NAME
FUNCTION
DEFAULT
VALUE
READ/
WRITE
00
INTERRUPT
Interrupt register; see Table 13
−
R
01
STATUS
Status register; see Table 14
−
R
A0
HEADER3
Programmable header, most significant byte
1111 0110
W
1:10 ratio
0011 1110
Programmable header
1111 0110
1:10 ratio
10X XXXX
A1
HEADER2
W
A2
HEADER1
Programmable header
0010 1000
W
A3
HEADER0
Programmable header, least significant byte
0010 1000
W
A4
HEADERX3
Programmable header, don’t care, most significant byte
0000 0000
W
1:10 ratio
0000 0000
Programmable header, don’t care
0000 0000
1:10 ratio
00XX XXXX
A5
HEADERX2
W
A6
HEADERX1
Programmable header, don’t care
0000 0000
W
A7
HEADERX0
Programmable header, don’t care, least significant byte
0000 0000
W
A8
DMXCNF
Demultiplexer configuration register; see Table 15
0000 1011
W
B0
DIVCNF
Octave and loop mode configuration register; see Table 16
0000 0000
W
B1
MAINDIV1
Main divider division factor N; most significant byte; range
128 to 511; see Table 17
0000 0001
W
B2
MAINDIV0
Main divider division factor N; least significant byte; see Table 18 0000 0000
W
B3
FRACN2
Fractional divider division factor K; see Table 19
1000 0000
W
B4
FRACN1
Fractional divider division factor K; see Table 20
0000 0000
W
B5
FRACN0
Fractional divider division factor K; see Table 21
0000 0000
W
B6
DCRCNF
DCR configuration register; see Table 22
0000 1100
W
BC
LIMLOS1TH
Limiter 1 loss of signal threshold register; range 0 to 255
0000 0000
W
BD
LIMLOS1CNF Limiter 1 loss of signal configuration register; see Table 23
0000 1101
W
BE
LIMLOS2TH
0000 0000
W
Limiter 2 loss of signal threshold register; range 0 to 255
BF
LIMLOS2CNF Limiter 2 loss of signal configuration register; see Table 24
0000 1101
W
C0
LIMSLICE1
Limiter 1 slice level register; range 0 to 255
0000 0000
W
C1
LIMSLICE2
Limiter 2 slice level register; range 0 to 255
0000 0000
W
C2
LIMCNF
Limiter configuration register; see Table 25
0000 1000
W
C8
IOCNF3
Parallel interface output configuration register 3; see Table 26
0000 1100
W
C9
IOCNF2
Parallel interface output configuration register 2; see Table 27
1010 1010
W
CA
IOCNF1
RF serial I/O configuration register 1; see Table 28
0000 0000
W
CB
IOCNF0
RF serial output configuration register 0; see Table 29
0010 0011
W
CC
INTMASK
Interrupt masking register; see Table 30
0101 0000
W
Notes
1. Addresses not shown must not be accessed.
2. X = don’t care.
2003 May 21
25
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 13 Register INTERRUPT (address 00H)
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
loss of signal on channel 1
1
no signal present (loss of signal condition)
0
signal present
loss of signal on channel 2
1
no signal present (loss of signal condition)
0
signal present
DCR frequency indication
1
frequency outside predefined window
(unlocked)
0
frequency inside predefined window (locked)
auto-switching between channels
1
enabled (active limiter indicated in Status
register)
0
disabled (no auto-switching between
channels)
high junction temperature
0
0
2003 May 21
0
1
junction temperature ≥130 °C
0
junction temperature <130 °C
reserved
26
NAME
LOS1
LOS2
INWINDOW
LIMSW
TALARM
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 14 Register STATUS (address 01H)
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
loss of signal on channel 1
1
no signal present (loss of signal condition)
0
signal present
loss of signal on channel 2
1
no signal present (loss of signal condition)
0
signal present
DCR frequency indication
1
frequency inside predefined window
(locked)
0
frequency outside predefined window
(unlocked)
active limiter indication
1
limiter 1 active
0
limiter 2 active
high junction temperature
0
0
2003 May 21
0
1
junction temperature ≥130 °C
0
junction temperature <130 °C
reserved
27
NAME
LOS1
LOS2
INWINDOW
LIMSEL
TALARM
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 15 Register DMXCNF (address A8H); default value 0BH
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
1
1
1:16
1
0
1:10
0
1
1:8
0
0
demultiplexing ratio
via
0
DMXR
1:4
demultiplexing ratio programming
1
NAME
I2C-bus
I2CDMXR
interface
via pins DMXR0 and DMXR1
frame header detection in 1:10 Gigabit
Ethernet mode
1
CMPL
simultaneously check for complementary
header
0
check programmed header only
parallel data bus bit designations
1
BUSSWAP
D00 = MSB, D15 = LSB (reversed)
0
D15 = MSB, D00 = LSB (normal)
demultiplexer mute parallel interface outputs DMXMUTE
1
mute; parallel interface outputs forced to
logic 0
0
no mute
enable/disable byte alignment
1
enabled
0
disabled
ENBA control
1
via
0
0
I2C-bus
I2CENBA
interface
via pin ENBA
0
2003 May 21
ENBA
0
0
1
0
1
1
default value
28
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 16 Register DIVCNF (address B0H); default value 00H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
octave divider division factor M, octave
selection
0
0
0
0
M = 1, octave number 0
0
0
1
M = 2, octave number 1
0
1
0
M = 4, octave number 2
0
1
1
M = 8, octave number 3
1
0
0
M = 16, octave number 4
1
0
1
M = 32, octave number 5
1
1
0
0
M = 64, octave number 6
1
enabled
0
disabled
enable/disable loop mode outputs
1
enabled
0
disabled
loop mode control
I2C-bus
1
via
via pin ENLINQ and/or pin ENLOUTQ
0
0
0
0
0
0
ENLOOPIN
ENLOOPOUT
I2CLOOPMODE
0
0
DIV_M
reserved
enable/disable loop mode inputs
0
NAME
interface
default value
Table 17 Register MAINDIV1 (address B1H); default value 01H
BIT
7
6
5
4
PARAMETER
3
2
1
0
−
−
−
−
−
−
−
N8
0
0
0
0
0
0
0
1
DESCRIPTION
main divider division factor N; N8 = MSB
NAME
DIV_N
default value
Table 18 Register MAINDIV0 (address B2H); default value 00H
BIT
PARAMETER
7
6
5
4
3
2
1
0
N7
N6
N5
N4
N3
N2
N1
N0
0
0
0
0
0
0
0
0
2003 May 21
DESCRIPTION
main divider division factor N; N0 = LSB
default value
29
NAME
DIV_N
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 19 Register FRACN2 (address B3H); default value 80H
BIT
PARAMETER
7
6
5
4
3
2
1
NF
X
K21
K20
K19
K18
K17
0
DESCRIPTION
K16 fractional divider division value K;
K21 = MSB
NILFRAC control bit
1
DIV_K
NILFRAC
no fractional N functionality
0
1
NAME
fractional N functionality
0
0
0
0
0
0
0
default value
Note
1. X = don’t care.
Table 20 Register FRACN1 (address B4H); default value 00H
BIT
PARAMETER
7
6
5
4
3
2
1
0
K15
K14
K13
K12
K11
K10
K9
K8
0
0
0
0
0
0
0
0
DESCRIPTION
fractional divider division value K
NAME
DIV_K
default value
Table 21 Register FRACN0 (address B5H); default value 00H
BIT
PARAMETER
7
6
5
4
3
2
1
0
DESCRIPTION
K7
K6
K5
K4
K3
K2
K1
K0
fractional divider division value K; K0 = LSB
0
0
0
0
0
0
0
0
2003 May 21
default value
30
NAME
DIV_K
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 22 Register DCRCNF (address B6H); default value 0CH
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
0
1
1
2000 ppm
1
0
0
1000 ppm
1
0
1
500 ppm
1
1
0
FWD window size; relative to bit rate
NAME
WINDOWSIZE
250 ppm
FWD window size select; WINDOWSIZE
value or zero
1
window size specified by ‘WINDOWSIZE’;
PLL frequency allowed to vary around the
reference frequency
0
window size = 0 ppm; PLL frequency
directly synthesized from reference
frequency
WINSIZE control bit
I2C-bus
1
via
0
via pin WINSIZE
enabled
0
disabled
I2CWINSIZE
interface
automatic window size select
1
WINSIZE
AUTOWIN
reference divider division factor R; reference REFDIV
frequency
1
1
R = 8; 155.52 MHz
1
0
R = 4; 77.76 MHz
0
1
R = 2; 38.88 MHz
0
0
R = 1; 19.44 MHz
0
0
2003 May 21
0
0
1
1
0
0
default value
31
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 23 Register LIMLOS1CNF (address BDH); default value 0DH
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
loss of signal detection on channel 1
1
enabled
0
disabled
loss of signal threshold level control bit on
channel 1
1
via I2C-bus interface by internal DAC;
register LIMLOS1TH
0
via analog voltage on pin LOSTH1
loss of signal detection hysteresis on
channel 1
0
0
0
0 dB
0
0
1
1 dB
0
1
0
2 dB
0
1
1
3 dB
1
0
0
4 dB
1
0
1
5 dB
1
1
0
6 dB
1
1
1
7 dB
slice level on channel 1
1
enabled
0
disabled
slice level sign on channel 1
1
positive
0
negative
polarity of LOS on channel 1
1
inverted
0
normal
0
0
2003 May 21
0
0
1
1
0
1
default value
32
NAME
LOS1
I2CREFLVL1
HYS1
SL1
SL1SGN
LOS1POL
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 24 Register LIMLOS2CNF (address BFH); default value 0DH
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
loss of signal detection on channel 2
1
enabled
0
disabled
loss of signal threshold level control bit on
channel 2
1
via I2C-bus interface by internal DAC;
register LIMLOS2TH
0
via analog voltage on pin LOSTH2
loss of signal detection hysteresis on
channel 2
0
0
0
0 dB
0
0
1
1 dB
0
1
0
2 dB
0
1
1
3 dB
1
0
0
4 dB
1
0
1
5 dB
1
1
0
6 dB
1
1
1
7 dB
slice level on channel 2
1
enabled
0
disabled
slice level sign on channel 2
1
positive
0
negative
polarity of LOS on channel 2
1
inverted
0
normal
0
0
2003 May 21
0
0
1
1
0
1
default value
33
NAME
LOS2
I2CREFLVL2
HYS2
SL2
SL2SGN
LOS2POL
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 25 Register LIMCNF (address C2H); default value 08H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
0
0
0
octave number 0; 1800 to 3200 Mbits/s
0
0
1
octave number 1; 900 to 1800 Mbits/s
0
1
0
octave number 2; 450 to 900 Mbits/s
amplifier octave selection
0
1
1
octave number 3; 225 to 450 Mbits/s
1
X
X
octave number 4; 30 to 225 Mbits/s
channel selection
1
channel 1 selected; limiter 1 active
0
channel 2 selected; limiter 2 active
channel selection control bit
I2C-bus
1
via
0
via pin INSEL
0
0
0
1
both limiters active
0
single limiter active, specified by bit INSEL
reserved
0
0
1
0
0
0
default value
Note
1. X = don’t care.
2003 May 21
34
AMPOCT
INSEL
I2CINSEL
interface; bit INSEL
single/dual limiter selection
0
NAME
BOTHON
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 26 Register IOCNF3 (address C8H); default value 0CH
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
0
0
0
0
60 mV (p-p)
0
0
0
1
minimum; 120 mV (p-p)
1
1
0
0
default; 800 mV (p-p)
1
1
1
1
parallel output signal amplitude
0
0
maximum; 1000 mV (p-p)
1
LVPECL mode: floating; CML mode:
AC-coupled
0
LVPECL mode: standard; CML mode:
DC-coupled
parallel output mode
1
Current Mode Logic (CML)
0
Low Voltage Positive Emitter Coupled
Logic (LVPECL)
0
2003 May 21
0
0
MFS
reserved
parallel output termination
0
NAME
1
1
0
0
default value
35
MFOUTTERM
MFOUTMODE
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 27 Register IOCNF2 (address C9H); default value AAH
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
parallel data output polarity
1
inverted
0
normal
parallel data output enable
1
enabled
0
disabled
parallel clock output polarity
1
inverted
0
normal
parallel clock output enable
1
enabled
0
disabled
parity output polarity
1
inverted
0
normal
parity output enable
1
enabled
0
disabled
frame pulse output polarity
1
1
enabled
0
disabled
2003 May 21
PDEN
POCLKINV
POCLKEN
PARINV
PAREN
FPINV
normal
frame pulse output enable
0
PDINV
inverted
0
1
NAME
1
0
1
0
1
0
default value
36
FPEN
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 28 Register IOCNF1 (address CAH); default value 00H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
loop mode clock input polarity
1
inverted
0
normal
loop mode data input polarity
1
inverted
0
normal
loop mode clock and data inputs swap
1
clock and data input pairs swapped
0
normal
loop mode clock output polarity
1
inverted
0
normal
loop mode data output polarity
1
inverted
0
normal
loop mode clock and data outputs swap
0
0
0
0
2003 May 21
1
clock and data output pairs swapped
0
normal
reserved
0
0
0
0
0
0
default value
37
NAME
CININV
DININV
CDINSWAP
COUTINV
DOUTINV
CDOUTSWAP
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 29 Register IOCNF0 (address CBH); default value 23H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
0
0
0
0
minimum: 20mV (p-p); 60 mV (p-p) high
swing
0
0
1
1
default: 80mV (p-p); 250 mV (p-p) high
swing
1
1
1
1
maximum: 300mV (p-p); 1000 mV (p-p)
high swing
RF serial output signal amplitude
prescaler output polarity
1
1
enabled
0
disabled
RF serial output swing
1
high swing
0
low swing
0
reserved
2003 May 21
1
0
PRSCLOINV
normal
prescaler output enable
0
RFS
inverted
0
0
NAME
0
0
1
1
default value
38
PRSCLOEN
RFSWING
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Table 30 Register INTMASK (address CCH); default value A0H
BIT
7
6
5
4
PARAMETER
3
2
1
0
DESCRIPTION
mask LOS1 signal
1
not masked
0
masked; note 1
mask LOS2 signal
1
not masked
0
masked; note 1
mask INWINDOW signal
1
not masked
0
masked; note 1
mask LIMSEL signal
1
not masked
0
masked; note 1
mask high junction temperature
1
not masked
0
masked; note 1
0
1
inverted; active LOW output
0
normal; active HIGH output
pin INT output mode
1
standard CMOS output
0
open-drain output
1
0
1
0
0
0
0
default value
Note
1. Signal is not processed by the interrupt controller.
2003 May 21
MLOS1
MLOS2
MINWINDOW
MLIMSEL
MTALARM
reserved
pin INT polarity mode
0
NAME
39
INTPOL
INTOUT
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
• Loop mode serial input and output configuration:
pins ENLINQ and ENLOUTQ
TZA3012AHW FEATURES IN PRE-PROGRAMMED
MODE
• Automatic byte alignment for SDH/SONET or Gigabit
Ethernet (ENBA)
Although the TZA3012AHW is primarily intended to be
programmed via the I2C-bus (pin UI HIGH), many of the
TZA3012AHW functions can be accessed via the external
chip pins in pre-programmed mode (pin UI LOW) as
follows:
• Frame detection for SDH/SONET (pattern is
A1A1A2A2) or Gigabit Ethernet
• EVEN parity generation
• Choice of four pre-programmed SDH/SONET bit rates:
STM1/OC3, STM4/OC12, STM16/OC48,
STM16/OC48 + FEC; pins DR0 to DR2
• LVPECL outputs on parallel interface with 800 mV (p-p),
single-ended signal, (DC-coupled termination to
VCC − 2 V)
• Choice of four pre-programmed bit rates; Fibre Channel,
double Fibre Channel, Gigabit Ethernet, 10-Gigabit
Ethernet; pins DR0 to DR2
• CML serial RF outputs with typical 80 mV (p-p),
single-ended signal, (AC-coupled load)
• In window detection (INWINDOW)
• Choice of four demultiplexing ratios; 1:16, 1:10, 1:8 or
1:4 pins DMUXR1 and DMUXR0
• FWD window size select, WINDOWSIZE value ppm or
0 ppm (WINSIZE)
• Input channel selection (INSEL)
• High junction temperature indication (pin INT;
open-drain)
• Received signal strength indicator, independently for
channels 1 and 2
• 18 to 21 MHz reference frequency supported.
• Loss of signal detection threshold for each input channel
individually (LOSTH1 and LOSTH2)
• Automatic disable of unused logarithmic detector
(LOSTH1 and LOSTH2)
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MAX.
UNIT
−0.5
+3.6
V
D00 to D15, D00Q to D15Q, POCLK, POCLKQ, FP, FPQ,
PARITY, PARITYQ, PRSCLO and PRSCLOQ
VCC − 2.5
VCC + 0.5
V
LOSTH1, LOSTH2 and RREF
−0.5
VCC + 0.5
V
RSSI1 and RSSI2
−0.5
VCC + 0.5
V
UI, INSEL, WINSIZE, CS, SDA, SCL, DMXR0, DMXR1, ENBA,
ENLOUTQ and ENLINQ
−0.5
VCC + 0.5
V
LOS1, LOS2 and INWINDOW
−0.5
VCC + 0.5
V
INT
−0.5
VCC + 0.5
V
VCCA, VCCD,
VCCO, VDD
supply voltages
Vn
DC voltage on pins
In
MIN.
input current on pins
IN1, IN1Q, IN2 and IN2Q
−30
+30
mA
CREF, CREFQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ
−20
+20
mA
INT
−2
+2
mA
Tamb
ambient temperature
−40
+85
°C
Tj
junction temperature
−
+125
°C
Tstg
storage temperature
−65
+150
°C
2003 May 21
40
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
16
K/W
notes 1 and 2
Notes
1. In compliance with JEDEC standards JESD51-5 and JESD51-7.
2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and
fourth layer in the PCB.
CHARACTERISTICS
VCC = 3.14 to 3.47 V; Tamb = −40 to +85 °C; Rth(j-a) ≤ 16 K/W; all characteristics are specified for the default settings
(note 1); all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supplies
ICCA
analog supply current
15
ICCD
digital supply current
270
350
450
mA
ICCO
oscillator supply current
20
25
33
mA
IDD
digital supply current
0
0
1
mA
ICC(tot)
total supply current
note 2
305
395
511
mA
Ptot
total power dissipation
note 2
0.96
1.3
1.77
W
see Figs 20 and 22
20
27
mA
CMOS input: pins UI, DR0, DR1, DR2, INSEL, WINSIZE, DMXR0, DMXR1, ENBA, ENLOUTQ and ENLINQ
VIL
LOW-level input voltage
−
−
0.2VCC
V
VIH
HIGH-level input voltage
0.8VCC
−
−
V
IIL
LOW-level input current
VIL = 0 V
−200
−
−
µA
IIH
HIGH-level input current
VIH = VCC
−
−
10
µA
CMOS output: pins LOS1, LOS2, INWINDOW and INT
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.2
V
VOH
HIGH-level output voltage
IOH = −0.5 mA
VCC − 0.2
−
VCC
V
Open-drain output: pin INT
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.2
V
IOH
HIGH-level output current
VOH = VCC
−
−
10
µA
Serial output: pins COUT, COUTQ, DOUT and DOUTQ
Vo(p-p)
default output voltage swing single-ended with 50 Ω
(peak-to-peak value)
external load;
ENLOUTQ = LOW;
see Figs 23 and 27; note 3
50
80
110
mV
Zo
output impedance
single-ended to VCC
80
100
120
Ω
tr
rise time
20% to 80%
−
100
−
ps
tf
fall time
80% to 20%
−
100
−
ps
2003 May 21
41
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
SYMBOL
PARAMETER
TZA3012AHW
CONDITIONS
MIN
TYP
MAX
UNIT
tD-C
data-to-clock delay
(COUT, COUTQ and DOUT, 80
DOUTQ) between
differential crossovers;
see Fig.29
140
200
ps
δ
duty cycle COUT and
COUTQ
between differential
crossovers
40
50
60
%
50
−
1000
mV
VCC − 1
−
VCC + 0.25 V
40
50
60
Serial input: pins CLOOP, CLOOPQ, DLOOP and DLOOPQ
Vi(p-p)
input voltage
(peak-to-peak value)
Vi
DC input voltage
Zi
input impedance
td
clock delay
see Fig.30
260
340
400
ps
tsu
set-up time
see Fig.30
15
30
60
ps
th
hold time
see Fig.30
15
30
60
ps
δ
duty cycle signals CLOOP
and CLOOPQ
between differential
crossovers
40
50
60
%
single-ended
single-ended to VCC
Ω
CML mode parallel output: pins D00 to D15, D00Q to D15Q, FP, FPQ, PARITY, PARITYQ, POCLK, POCLKQ,
PRSCLO and PRSCLOQ
Vo(p-p)
default output voltage swing single-ended with 50 Ω
(peak-to-peak value)
external load to VCC;
AC-coupled; see Fig.27 or
DC-coupled; see Fig.28;
note 4
650
800
1000
mV
Zo
output impedance
single-ended to VCC
70
95
110
Ω
tr
rise time
20% to 80%
200
250
350
ps
tf
fall time
80% to 20%
fPBR
parallel bit rate
200
250
350
ps
−
−
400
Mbits/s
LVPECL mode parallel output: pins D00 to D15, D00Q to D15Q, FP, FPQ, PARITY, PARITYQ, POCLK, POCLKQ,
PRSCLO and PRSCLOQ
VOH
HIGH-level output voltage
50 Ω termination to
VCC − 2V; see Fig.24
VCC − 1.2
VCC − 1.0 VCC − 0.9
V
VOL
LOW-level output voltage
50 Ω termination to
VCC − 2V; see Fig.24
VCC − 2.0
VCC − 1.9 VCC − 1.7
V
Vo(p-p)
default output voltage swing LVPECL floating; Fig.21;
(peak-to-peak value)
single-ended with 50 Ω
external load to VCC;
AC-coupled; see Fig.26 or
DC-coupled; see Fig.25;
note 4
700
900
1150
mV
tr
rise time
20% to 80%
300
350
400
ps
tf
fall time
80% to 20%
300
350
400
ps
fpar
parallel bit rate
−
−
400
Mbits/s
2003 May 21
42
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
SYMBOL
PARAMETER
TZA3012AHW
CONDITIONS
MIN
TYP
MAX
UNIT
Parallel timing output: pins D00 to D15, D00Q to D15Q, FP, FPQ, PARITY, PARITYQ, POCLK, POCLKQ,
PRSCLO and PRSCLOQ
−100
tD-C
data-to-clock delay
D00 to D15/POCLK
DMX 1:16, 1:10, 1:8;
see Fig.31; note 5
tD-C
data-to-clock delay
D06 to D09/POCLK
DMX 1:4; see Fig.31; note 5 150
δ
duty cycle POCLK
50
60
%
skew
channel to channel skew
D00 and Dn (between
channels)
DMX 1:16, 1:10, 1:8; note 5 −
−
200
ps
skew
channel to channel skew
D06 and D09 (between
channels)
DMX 1:4; note 5
−
−
50
ps
10 to 20 kΩ resistor to VEE
1.17
1.21
1.26
V
40
100
250
ps
180
250
ps
Reference: pin RREF
Vref
reference voltage
I2C-bus pins SCL and SDA
VIL
LOW-level input voltage
−
−
0.2VCC
V
VIH
HIGH-level input voltage
0.8VCC
−
−
V
Vhys
hysteresis of Schmitt trigger
inputs
0.05VCC
−
−
V
VOL
SDA LOW-level output
voltage (open-drain)
0
−
0.4
V
IL
leakage current
−10
−
+10
µA
Ci
input capacitance
−
−
10
pF
IOL = 3 mA
I2C-bus timing
fSCL
SCL clock frequency
−
−
100
kHz
tLOW
SCL LOW time
1.3
−
−
µs
tHD;STA
hold time START condition
0.6
−
−
µs
tHIGH
SCL HIGH time
0.6
−
−
µs
tSU;STA
set-up time START
condition
0.6
−
−
µs
tHD;DAT
data hold time
0
−
0.9
µs
tSU;DAT
data set-up time
100
−
−
ns
tSU;STO
set-up time STOP condition
0.6
−
−
µs
tr
SCL and SDA rise time
20
−
300
ns
tf
SCL and SDA fall time
20
−
300
ns
tBUF
bus free time between
STOP and START
1.3
−
−
µs
Cb
capacitive load on each bus
line
−
−
400
pF
tSP
pulse width of allowable
spikes
0
−
50
ns
2003 May 21
43
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
SYMBOL
TZA3012AHW
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
VnL
noise margin at LOW-level
0.1VCC
−
−
V
VnH
noise margin at HIGH-level
0.2VCC
−
−
V
mV
RF input: pins IN1, INQ1, IN2 and IN2Q
Vi(p-p)
input voltage swing
(peak-to-peak value)
single-ended; note 6
12
−
500
Vsl
typical slice level range
note 7
−50
−
+50
mV
Zi
input impedance
differential
80
100
120
Ω
αiso
between channel isolation
−
60
−
dB
5
−
500
mV
Received Signal Strength Indicator (RSSI)
Vi(p-p)
input voltage swing
(peak-to-peak value)
single-ended
SRSSI
RSSI sensitivity
see Fig.4
15
17
20
mV/dB
VRSSI
output voltage
Vi(p-p) = 32 mV (p-p);
PRBS (231−1)
580
680
780
mV
∆Vo(RSSI)
output voltage variation
input 30 to 3200 Mbits/s;
PRBS (231−1);
VCC = 3.14 to 3.47 V;
∆T = 120 °C
−50
−
+50
mV
Output: pins RSSI1 and RSSI2
Zo
output impedance
−
1
10
Ω
IO(source)
output source current
−
−
1
mA
IO(sink)
output sink current
−
−
0.4
mA
LOS detector
hys
hysteresis
note 8
−
3
−
dB
ta
assert time
∆Vi(p-p) = 3 dB
−
−
5
µs
td
de-assert time
∆Vi(p-p) = 3 dB
−
−
5
µs
single-ended
50
−
1000
mV
Reference frequency input: pins CREF and CREFQ
Vi(p-p)
input voltage
(peak-to-peak value)
Vi
DC input voltage
VCC − 1
−
VCC + 0.25 V
Zi
input impedance
single-ended to VCC
40
50
60
Ω
∆fCREF
reference clock frequency
accuracy
SDH/SONET requirement
−20
−
+20
ppm
fCREF
reference clock frequency
see Table 7; R = 1, 2, 4 or 8 18 × R
19.44 × R 21 × R
MHz
PLL characteristics
tacq
acquisition time
30 Mbits/s
−
−
200
µs
tacq(pc)
acquisition time at power
cycle
30 Mbits/s
−
−
10
ms
tacq(o)
acquisition time octave
change
30 Mbits/s
−
−
10
µs
TDR
transitionless data run
30 Mbits/s
−
1000
−
bits
2003 May 21
44
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
SYMBOL
TZA3012AHW
PARAMETER
CONDITIONS
jitter tolerance
(peak-to-peak value)
STM1/OC3 mode
(ITU-T G.958);
PRBS (231−1); note 9
MIN
TYP
MAX
UNIT
Jitter tolerance
Jtol(p-p)
f = 6.5 kHz
3
10
−
UI
f = 65 kHz
0.3
1
−
UI
f = 1 MHz
0.3
0.5
−
UI
STM4/OC12 mode
(ITU-T G.958);
PRBS (231−1); note 10
f = 25 kHz
3
10
−
UI
f = 250 kHz
0.3
1
−
UI
f = 5 MHz
0.3
0.5
−
UI
f = 100 kHz
3
10
−
UI
f = 1 MHz
0.3
1
−
UI
f = 20 MHz
0.3
0.5
−
UI
STM16/OC48 mode
(ITU-T G.958);
PRBS (231−1); note 11
Notes
1. Default settings: UI = LOW (pre-programmed mode; see Table 1); DR0 = LOW, DR1 = HIGH, DR2 = LOW
(STM16/OC48); INSEL = HIGH (limiter 1 active); WINSIZE = HIGH (1000 ppm); ENBA = HIGH (automatic byte
alignment); ENLOUTQ = HIGH (DOUT, COUT disabled); ENLINQ = HIGH (DLOOP, CLOOP disabled);
DMXR0 = HIGH, DMXR1 = HIGH (DMX ratio 1:16); CREF and CREFQ = 19.44 MHz; LOSTH2 not connected
(LOS2 switched off); D00 to D15 and D00Q to D15Q, FP, FPQ, PARITY, PARITYQ, POCLK, POCLKQ, PRSCLO
and PRSCLOQ not connected.
2. The total supply current and power dissipation is dependent on the IC setups such as swing and loop modes and
termination conditions.
3. The output swing is adjustable in 16 steps controlled by bits RFS in I2C-bus register CBH.
4. The output swing is adjustable in 16 steps controlled by bits MFS in I2C-bus register IOCNF3 (address C8H). In
standard LVPECL mode only swing = 12 (default) should be used.
5. With 50% duty cycle.
6. The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. It is assumed that
both inputs carry a complementary signal of the specified peak-to-peak value.
7. The slice level is adjustable in 256 steps controlled by I2C-bus registers LIMSLICE1 (address C0H) and LIMSLICE2
(address C1H).
8. The hysteresis is adjustable in 8 steps controlled by bits HYS1 and HYS2 in I2C-bus registers LIMLOS1CNF
(address BDH) and LIMLOS2CNF (address BFH).
9. The Jtol(p-p) min. value is 0.25UI for Tamb = −40 °C to 0 °C at f = 65 kHz and 1 MHz.
10. The Jtol(p-p) min. value is 0.25UI for Tamb = −40 °C to 0 °C at f = 250 kHz and 5 MHz.
11. The Jtol(p-p) min. value is 0.25UI for Tamb = −40 °C to 0 °C at f = 1 MHz and 20 MHz.
2003 May 21
45
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
MBL556
handbook, full pagewidth
50
ICCD
(mA)
40
LVPECL standard
30
CML AC
LVPECL floating
20
10
CML DC
0
0
5
10
15
value of address C8H, bit 3 to bit 0
Fig.20 Supply current per parallel output.
MBL557
handbook, full pagewidth
1000
Vo(p-p)
(mV)
800
DEFAULT
LVPECL standard
600
CML AC/DC
LVPECL floating
400
200
0
0
5
10
15
value of address C8H, bit 3 to bit 0
Fig.21 Output voltage swing of parallel output.
2003 May 21
46
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
MBL558
handbook, full pagewidth
50
ICCD
(mA)
40
CML AC
30
20
low swing
10
0
0
5
10
15
value of address CBH, bit 3 to bit 0
Serial outputs are off (default).
Fig.22 Supply current per serial output.
MBL559
handbook, full pagewidth
1000
Vo(p-p)
(mV)
800
600
CML AC
(clock 2.4 GHz)
400
low swing
200
(ENLOUTQ = LOW)
0
0
5
10
15
value of address CBH, bit 3 to bit 0
Fig.23 Output voltage swing of serial output.
2003 May 21
47
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
handbook, full pagewidth
SWING CONTROL
VCC
Vterm
OUT
2V
optional
AC coupling
transmission
lines
to highimpedance
input
50 Ω
50 Ω
OUTQ
Iswing
50 Ω
50 Ω
in
on-chip
off-chip
MBL562
Fig.24 Standard PECL mode.
handbook, full pagewidth
SWING CONTROL
VCC
OUT
transmission lines
50 Ω
50 Ω
OUTQ
Iswing
100 Ω
to highimpedance
input
in
on-chip
off-chip
Fig.25 Floating PECL mode (DC-coupled).
2003 May 21
48
MBL560
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
handbook, full pagewidth
SWING CONTROL
VCC
Vbias
AC coupling
OUT
50 Ω
transmission
lines
to highimpedance
input
50 Ω
50 Ω
OUTQ
Iswing
50 Ω
in
on-chip
off-chip
MBL561
Fig.26 Floating LVPECL mode (AC-coupled).
recommended for
serial outputs
handbook, full pagewidth
SWING CONTROL
VCC
100 Ω
Vbias
120
Ω
100 Ω
OUT
100 Ω
100 Ω
50 Ω
transmission
lines
50 Ω
50 Ω
OUTQ
Iswing
in
on-chip
off-chip
Fig.27 CML mode (AC-coupled).
2003 May 21
49
50 Ω
MBL563
to highimpedance
input
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
handbook, full pagewidth
SWING CONTROL
VCC
100 Ω
100 Ω
OUT
50 Ω
transmission
lines
50 Ω
to highimpedance
input
50 Ω
OUTQ
Iswing
50 Ω
in
on-chip
off-chip
MBL564
Fig.28 CML mode (DC-coupled).
handbook, full pagewidth
COUT
t D-C
DOUT
MGU345
The timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signals are differential).
Fig.29 Loop mode output timing.
2003 May 21
50
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
handbook, halfpage
CLOOP
td
tsu
th
DLOOP
MBL554
The timing is measured from the crossover point of the clock input signal to the crossover point of the data input.
Fig.30 Loop mode input timing.
handbook, full pagewidth
POCLK
t D-C
D00 to D15,
FP, PARITY
MGU343
The timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signals are differential).
Fig.31 Parallel bus output timing.
2003 May 21
51
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
PACKAGE OUTLINE
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads;
body 14 x 14 x 1 mm; exposed die pad
SOT638-1
c
y
exposed die pad side
X
Dh
A
75
51
76
50
ZE
e
E HE
Eh
A
A2
(A3)
A1
w M
θ
bp
Lp
pin 1 index
L
detail X
26
100
1
25
bp
e
w M
ZD
v M A
D
B
HD
v M B
0
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max.
mm
1.2
A1
A2
A3
bp
c
D(1)
Dh
E(1)
Eh
e
0.15
0.05
1.05
0.95
0.25
0.27
0.17
0.20
0.09
14.1
13.9
7.1
6.1
14.1
13.9
7.1
6.1
0.5
HD
HE
16.15 16.15
15.85 15.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.08
ZD(1) ZE(1)
θ
1.15
0.85
7°
0°
1.15
0.85
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
01-03-30
03-04-07
SOT638-1
2003 May 21
EUROPEAN
PROJECTION
52
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
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TZA3012AHW
To overcome these problems the double-wave soldering
method was specifically developed.
SOLDERING
Introduction to soldering surface mount packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material.
The top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 220 °C (SnPb process) or below 245 °C
(Pb-free process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all the BGA packages
– for packages with a thickness ≥ 2.5 mm
Manual soldering
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the
lead. Contact time must be limited to 10 seconds at up to
300 °C.
• below 235 °C (SnPb process) or below 260 °C
(Pb-free process) for packages with a thickness
< 2.5 mm and a volume < 350 mm3 so called small/thin
packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2003 May 21
53
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO, VSSOP
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 May 21
54
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
DEFINITIONS
DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 May 21
55
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 May 21
56
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
NOTES
2003 May 21
57
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
NOTES
2003 May 21
58
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate fibre optic receiver
TZA3012AHW
NOTES
2003 May 21
59
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected]
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403510/02/pp60
Date of release: 2003
May 21
Document order number:
9397 750 10905