PHILIPS BUK582-100A

Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK582-100A
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode
logic level field-effect power
transistor in a plastic envelope
suitable for surface mount
applications.
The device is intended for use in
automotive and general purpose
switching applications.
PINNING - SOT223
PIN
SYMBOL
PARAMETER
MAX.
UNIT
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance;
VGS = 5 V
100
1.7
1.8
150
0.31
V
A
W
˚C
Ω
PIN CONFIGURATION
DESCRIPTION
1
gate
2
drain
3
source
4
drain (tab)
SYMBOL
d
4
g
2
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg
Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage temperature
Junction Temperature
RGS = 20 kΩ
Tamb = 25 ˚C
Tamb = 100 ˚C
Tamb = 25 ˚C
Tamb = 25 ˚C
-
- 55
-
100
100
15
1.7
1.1
6.8
1.8
150
150
V
V
V
A
A
A
W
˚C
˚C
THERMAL RESISTANCES
SYMBOL
Rth j-b
Rth j-amb
PARAMETER
CONDITIONS
1
From junction to board
From junction to ambient
Mounted on any PCB
Mounted on PCB of Fig.17
MIN.
TYP.
MAX.
UNIT
-
40
-
70
K/W
K/W
1 Temperature measured 1-3 mm from tab.
January 1998
1
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK582-100A
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Zero gate voltage drain current
Gate source leakage current
Drain-source on-state
resistance
VGS = 0 V; ID = 0.25 mA
100
-
-
V
VDS = VGS; ID = 1 mA
VDS = 100 V; VGS = 0 V;
VDS = 100 V; VGS = 0 V; Tj = 125 ˚C
VGS = ±15 V; VDS = 0 V
VGS = 5 V; ID = 1.7 A
1.0
-
1.5
1
0.1
10
0.23
2.0
10
1.0
100
0.31
V
µA
mA
nA
Ω
MIN.
TYP.
MAX.
UNIT
VGS(TO)
IDSS
IDSS
IGSS
RDS(ON)
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 1.7 A
2
3
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
400
90
35
600
120
50
pF
pF
pF
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 3 A;
VGS = 5 V; RGS = 50 Ω;
Rgen = 50 Ω
-
12
45
50
30
18
70
70
45
ns
ns
ns
ns
MIN.
TYP.
MAX.
UNIT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
IDR
-
-
-
1.7
A
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
IF = 1.7 A; VGS = 0 V
-
0.85
6.8
1.1
A
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 1.7 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
90
0.30
-
ns
µC
MIN.
TYP.
MAX.
UNIT
-
-
45
mJ
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 1.7 A; VDD ≤ 25 V;
VGS = 5 V; RGS = 50 Ω;
Tamb = 25 ˚C
January 1998
2
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
Normalised Power Derating
PD%
10
ID / A
BUK582-100A
tp = 10 us
100 us
VD
S/
ID
120
BUK582-100A
110
R
D
S(
O
N
)=
100
90
80
1
1 ms
70
10 ms
60
50
100 ms
DC
40
0.1
30
1s
20
10 s
10
0.01
0.1
0
0
20
40
60
80
Tamb / C
100
120
140
Normalised Current Derating
ID%
10
VDS / V
100
Fig.4. Safe operating area Tamb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tamb)
120
1
ID / A
10
5
7
110
6
100
90
BUK582-100A
4
3.5
5
80
70
4
3
60
3
50
40
2
30
20
VGS/ V = 2.5
1
10
2
0
0
20
40
60
80
Tamb / C
100
120
0
140
0
1E+01
1E+00
4
6
8
10
VDS / V
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tamb); conditions: VGS ≥ 5 V
1E+02
2
BUKX82-100
Zth j-amb / (K/W)
1
D=
0.5
RDS(ON)/ Ohm
2.5
0.9
BUK582-100A
3
VGS/ V = 3.5
0.8
0.2
0.1
0.05
0.7
0.6
0.02
0.5
PD
tp
D=
tp
4
0.4
T
0.3
1E-01
5
0.2
0
1E-02
1E-07
t
T
0.1
0
1E-05
1E-03
1E-01
1E+01
0
1E+03
2
4
6
ID / A
t/s
Fig.3. Transient thermal impedance.
Zth j-amb = f(t); parameter D = tp/T
January 1998
10
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
3
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
7
BUK582-100A
VGS(TO) / V
BUK582-100A
ID/ A
max.
6
2
5
typ.
4
min.
3
1
2
Tj/ C = 150
1
25
0
0
0
1
2
VGS/ V
3
-60
4
gfs / S
-20
0
20
40
60
Tj / C
80
100
120
140
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
6
-40
BUK582-100A
5
SUB-THRESHOLD CONDUCTION
ID / A
1E-01
1E-02
4
2%
1E-03
98 %
typ
3
1E-04
2
1E-05
1
1E-06
0
0
1
3
2
4
5
6
7
0
0.4
0.8
1.2
VGS / V
ID/ A
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2.0
2
2.4
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
a
1.6
10000
C / pF
BUK5y2-100
1.5
1000
Ciss
1.0
100
Coss
0.5
Crss
0
-60 -40 -20
0
20
40 60
Tj / C
80
10
100 120 140
0
40
VDS / V
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 1.7 A; VGS = 5 V
January 1998
20
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
4
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
12
BUK582-100A
BUK582-100A
VGS / V
120
11
110
10
9
8
100
90
80
7
6
70
60
50
VDS/ V = 20
5
80
4
3
2
40
30
20
1
10
0
5
0
20
40
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 1.7 A; parameter VDS
7
IF/ A
Normalised Avalanche Energy
0
15
10
WDSS%
60
80
100
Tamb/ C
120
140
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tamb); conditions: ID = 1.7 A
BUK582-100A
VDD
+
6
L
5
VDS
-
4
VGS
-ID/100
3
Tj/ C = 150
25
T.U.T.
0
2
RGS
1
R 01
shunt
0
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VSDS/ V
2
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
January 1998
5
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK582-100A
PRINTED CIRCUIT BOARD
Dimensions in mm.
36
18
60
4.5
4.6
9
10
7
15
50
Fig.17. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick).
January 1998
6
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK582-100A
MECHANICAL DATA
Dimensions in mm
6.7
6.3
Net Mass: 0.11 g
B
3.1
2.9
0.32
0.24
0.2
4
A
A
0.10
0.02
16
max
M
7.3
6.7
3.7
3.3
13
2
1
10
max
1.8
max
1.05
0.80
2.3
0.60
0.85
4.6
3
0.1 M
B
(4x)
Fig.18. SOT223 surface mounting package.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".
January 1998
7
Rev 1.100
Philips Semiconductors
Product Specification
PowerMOS transistor
Logic level FET
BUK582-100A
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
January 1998
8
Rev 1.100