Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET FEATURES PHD24N03LT SYMBOL • ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance QUICK REFERENCE DATA d VDSS = 30 V ID = 24 A RDS(ON) ≤ 56 mΩ (VGS = 5 V) g RDS(ON) ≤ 50 mΩ (VGS = 10 V) s GENERAL DESCRIPTION PINNING N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. PIN SOT428 (DPAK) DESCRIPTION 1 gate 2 drain 1 3 source tab 2 tab drain 1 The PHD24N03LT is supplied in the SOT428 (DPAK) surface mounting package. 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current IDM PD Tj, Tstg Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS MIN. MAX. UNIT Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 55 30 30 ± 13 24 20 96 60 175 V V V A A A W ˚C TYP. MAX. UNIT - 2.5 K/W 50 - K/W Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS pcb mounted, minimum footprint 1 it is not possible to make connection to pin 2 of the SOT428 package. December 1999 1 Rev 1.100 Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET PHD24N03LT ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) Drain-source breakdown voltage Gate threshold voltage CONDITIONS MIN. VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C RDS(ON) Drain-source on-state resistance VGS = 10 V; ID = 12 A VGS = 5 V; ID = 12 A IGSS IDSS Gate source leakage current VGS = ±5 V; VDS = 0 V Zero gate voltage drain VDS = 30 V; VGS = 0 V; current Tj = 175˚C Tj = 175˚C TYP. MAX. UNIT 30 27 1.0 0.5 - 1.5 50 45 10 0.05 - 2.0 2.3 56 50 104 100 10 500 V V V V V mΩ mΩ mΩ nA µA µA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 24 A; VDD = 15 V; VGS = 5 V - 7 2.3 5 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 15 V; RD = 0.6 Ω; VGS = 5 V; RG = 10 Ω Resistive load - 12 50 30 36 - ns ns ns ns Ld Ls Internal drain inductance Internal source inductance Measured from tab to centre of die Measured from source lead to source bond pad - 3.5 7.5 - nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 460 144 78 - pF pF pF REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge ISM CONDITIONS MIN. TYP. MAX. UNIT - - 24 A - - 96 A IF = 24 A; VGS = 0 V - 1.05 1.5 V IF = 12 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 50 100 - ns nC AVALANCHE LIMITING VALUE SYMBOL PARAMETER WDSS CONDITIONS Drain-source non-repetitive ID = 12 A; VDD ≤ 15 V; VGS = 5 V; unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C energy December 1999 2 MIN. MAX. UNIT - 15 mJ Rev 1.100 Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET Normalised Power Derating PD% 120 PHD24N03LT Transient thermal impedance, Zth j-mb (K/W) PHP24N03T 10 110 100 D= 90 80 0.5 1 70 0.2 60 0.1 50 0.05 40 0.1 0.02 PD 30 tp D= 0 20 10 t T 0 0 20 40 60 80 100 Tmb / C 120 140 160 0.01 180 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 10us 100us 1ms 10ms pulse width, tp (s) 0.1s 1s 10s Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% 120 1us tp T 20 110 ID, Drain current (Amps) 5V 15 V PHP24N03LT 3.5 V 100 90 15 80 70 60 3V 10 50 40 30 5 VGS = 2.5 V 20 10 Tj = 25 C 0 0 20 40 60 80 100 Tmb / C 120 140 160 0 180 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V 100 5 ID N) 0.1 10 us O S( RD 0.08 100 us 3.5 V 0.06 10 DC 5V 1 ms 0.04 10 ms 15 V 0.02 Tmb = 25 C 1 Tj = 25 C 0 1 10 VDS, Drain-source voltage (Volts) 100 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp December 1999 30 RDS(on), Drain-Source on resistance (Ohms) PHP24N03LT 3V VGS = 2.5 V 0.12 S/ D =V 10 15 20 25 VDS, Drain-Source voltage (Volts) Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS PHP24N03T ID, Drain current (Amps) 0 0 5 10 15 ID, Drain current (Amps) 20 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 3 Rev 1.100 Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET PHD24N03LT Drain current, ID (A) 20 PHP24N03LT 2.5 VGS(TO) / V VDS = 25 V max. 2 15 typ. 1.5 10 min. 1 5 Tj = 25 C 175 C 0 0 1 0.5 2 3 Gate-source voltage, VGS (V) 4 0 -100 5 Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj 50 Tj / C 100 150 200 Sub-Threshold Conduction 1E-01 VDS = 25 V Tj = 25 C 10 0 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS PHP24N03LT Transconductance, gfs (S) 15 -50 1E-02 175 C 2% 1E-03 typ 98% 1E-04 5 1E-05 0 0 5 10 Drain current, ID (A) 15 20 1E-05 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) a 0.5 1 1.5 2 2.5 3 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 30V TrenchMOS 2 0 1000 Capacitances Ciss, Coss, Crss (pF) PHP24N03LT Ciss 1.5 100 1 Coss Crss 0.5 Tj = 25 C 0 -100 -50 0 50 Tj / C 100 150 10 200 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 12 A; VGS = 5 V December 1999 1 10 100 Drain-source voltage, VDS (V) 1000 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.100 Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET 15 VGS, Gate-Source voltage (Volts) PHD24N03LT PHP24N03LT 20 PHP24N03LT Source-Drain diode current, IF(A) VGS = 0 V VDD = 15 V ID = 24 A Tj = 25 C 15 10 10 175 C 5 Tj = 25 C 5 0 0 0 5 10 15 Qg, Gate charge (nC) 20 25 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS December 1999 0 0.2 0.4 0.6 0.8 1 Source-Drain voltage, VSDS (V) 1.2 1.4 Fig.14. Typical reverse diode current. IF = f(VSDS); parameter Tj 5 Rev 1.100 Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET PHD24N03LT MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) SOT428 seating plane y A E A2 A A1 b2 D1 mounting base E1 D HE L2 2 L1 L 1 3 b1 w M A b c e e1 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) A2 b b1 max. b2 c 0.65 0.45 0.89 0.71 0.89 0.71 1.1 0.9 5.36 5.26 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 2.285 4.57 HE max. L L1 min. L2 w y max. 10.4 9.6 2.95 2.55 0.5 0.7 0.5 0.2 0.2 Note 1. Measured from heatsink back to lead. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT428 EUROPEAN PROJECTION ISSUE DATE 98-04-07 Fig.15. SOT428 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". December 1999 6 Rev 1.100 Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET PHD24N03LT MOUNTING INSTRUCTIONS Dimensions in mm 7.0 7.0 2.15 1.5 2.5 4.57 Fig.16. SOT428 : soldering pattern for surface mounting. December 1999 7 Rev 1.100 Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET PHD24N03LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1999 8 Rev 1.100