PHILIPS 74ALVCH32501

INTEGRATED CIRCUITS
DATA SHEET
74ALVCH32501
36-bit universal bus transceiver with
direction pin; 5 V tolerant; 3-state
Product specification
File under Integrated Circuits, IC24
2000 Mar 16
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
The 74ALVCH32501 can be used as two 18-bit
transceivers or one 36-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CPAB and CPBA).
For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When input LEAB is
LOW, the A data is latched if input CPAB is held at a HIGH
or LOW level. If input LEAB is LOW, the A data is stored in
the latch/flip-flop on the LOW-to-HIGH transition of CPAB.
When input OEAB is HIGH, the outputs are active. When
input OEAB is LOW, the outputs are in the high-impedance
state.
FEATURES
• 3-state non-inverting outputs for bus oriented
applications
• Wide supply voltage range of 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A
• Current drive ±24 mA at 3.0 V
• Universal bus transceiver with D-type latches and
D-type flip-flops capable of operating in transparent,
latched or clocked mode
• CMOS low power consumption
• Direct interface with TTL levels
• All inputs have bus-hold circuitry
Data flow for B-to-A is similar to that of A-to-B, but uses
inputs OEBA, LEBA and CPBA. The output enables are
complimentary (OEAB is active HIGH, and OEBA is active
LOW).
• Output drive capability 50 Ω transmission lines at 85 °C
• Plastic fine-pitch ball grid array package.
DESCRIPTION
To ensure the high-impedance state during power-up or
power-down, pin OEBA should be tied to VCC through a
pull-up resistor and pin OEAB should be tied to GND
through a pull-down resistor. The minimum value of the
resistor is determined by the current-sinking or
current-sourcing capability of the driver.
The 74ALVCH32501 is a high-performance CMOS
product designed for VCC operation at 2.5 and 3.3 V with
I/O compatibility up to 5 V.
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPHL/tPLH
PARAMETER
propagation delay An to Bn; Bn to An
CONDITIONS
TYP.
UNIT
CL = 30 pF; VCC = 2.5 V
2.8
ns
CL = 50 pF; VCC = 3.3 V
3.0
ns
CI
input capacitance
4.0
pF
CI/O
input/output capacitance
8.0
pF
CPD
power dissipation capacitance per latch
VI = GND to VCC; note 1
outputs enabled
21
pF
outputs disabled
3
pF
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
2000 Mar 16
2
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
FUNCTION TABLE
See notes 1 and 2.
INPUT
OUTPUT
nOEAB
nLEAB
nCPAB
nAn
INTERNAL
REGISTERS
L
H
X
X
X
Z
disabled
L
L
↓
↓
X
X
h
l
H
L
Z
Z
disabled; latch data
L
L
H or L
X
NC
Z
disabled; hold data
L
L
L
L
↑
↑
h
l
H
L
Z
Z
disabled; clock data
H
H
H
H
X
X
H
L
H
L
H
L
transparent
H
H
↓
↓
X
X
h
l
H
L
H
L
latch data and display
H
H
L
L
↑
↑
h
l
H
L
H
L
clock data and display
H
H
L
L
H or L
H or L
X
X
H
L
H
L
hold data and display
OPERATING MODE
nBn
Notes
1. A-to-B data flow is shown; B-to-A flow is similar but uses nOEBA, nLEBA and nCPBA.
2. H = HIGH voltage level;
h = HIGH voltage level on set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level on set-up time prior to the enable or clock transition;
NC = no change;
X = don’t care;
↑ = LOW-to-HIGH enable or clock transition;
↓ = HIGH-to-LOW enable or clock transition;
Z = high impedance OFF-state.
2000 Mar 16
3
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
74ALVCH32501EC
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
−40 to +85 °C
114
LFBGA114
plastic
SOT537-1
PINNING
SYMBOL
DESCRIPTION
nAn
data inputs
nBn
data outputs
GND
ground (0 V)
VCC
DC supply voltage
nOEAB
output enable inputs A to B (active HIGH)
nOEBA
output enable inputs B to A (active LOW)
nLEAB
latch enable inputs A to B
nLEBA
latch enable inputs B to A
nCPAB
clock input A to B
nCPBA
clock input B to A
handbook, full pagewidth
1B1
1B3
6
1B5
1B7
1B9
1B11
1B13
1B14
1B16
n.c.
1B17 2CPAB
2B1
2B3
2B5
2B7
2B9
2B11
2B13
2B14
2B16
2B0
2B2
2B4
2B6
2B8
2B10
2B12
2B15
2B17
GND
5
1B0
1B2
1B4
1B6
1B8
1B10
1B12
1B15
4
1CPAB
GND
GND
VCC
GND
GND
VCC
GND 1CPBA
GND
VCC
GND
GND
VCC
GND 2CPBA GND
3
1LEAB 1OEAB
GND
VCC
GND
GND
VCC
GND 1OE BA 1LE BA 2OEAB GND
VCC
GND
GND
VCC
GND 2OE BA 2LE BA
GND
2
1A0
1A2
1A4
1A6
1A8
1A10
1A12
1A15
1A17 2LEAB
2A0
2A2
2A4
2A6
2A8
2A10
2A12
2A15
2A17
1
1A1
1A3
1A5
1A7
1A9
1A11
1A13
1A14
1A16
n.c.
2A1
2A3
2A5
2A7
2A9
2A11
2A13
2A14
2A16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
MNA562
Fig.1 Pin configuration.
2000 Mar 16
4
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
1OEAB
1CPBA
1LEBA
1CPAB
1LEAB
handbook, halfpage
VCC
1OEBA
data
input
C1
C1
1D
1D
to internal circuit
MNA473
1B0
1A0
C1
C1
1D
1D
Fig.3 Bus-hold circuit.
18 IDENTICAL CHANNELS
2OEAB
2CPBA
2LEBA
2CPAB
2LEAB
2OEBA
C1
C1
1D
1D
2B0
2A0
C1
C1
1D
1D
18 IDENTICAL CHANNELS
MNA563
Fig.2 Logic symbol.
2000 Mar 16
5
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
DC supply voltage
VI
DC input voltage
VO
DC output voltage
Tamb
ambient temperature
tr, tf
input rise and fall time ratios
(∆t/∆V)
CONDITIONS
MIN.
MAX.
UNIT
2.5 V range (for maximum speed 2.3
performance at 30 pF output load)
2.7
V
3.3 V range (for maximum speed 3.0
performance at 50 pF output load)
3.6
V
VCC
V
0
output HIGH or LOW state
0
VCC
V
−40
+85
°C
VCC = 1.2 to 2.7 V
0
20
ns/V
VCC = 2.7 to 3.6 V
0
10
ns/V
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
VCC
DC supply voltage
VI
DC input voltage
CONDITIONS
MIN.
MAX.
UNIT
−0.5
+4.6
V
for control pins; note 1
−0.5
+4.6
V
for data input pins; note 1
−0.5
VCC + 0.5 V
VI < 0
−
−50
mA
mA
IIK
DC input diode current
IOK
DC output clamping diode current VO < 0; note 1
−
50
VO
DC output voltage
see note 1
−0.5
VCC + 0.5 V
IO
DC output sink current
VO = 0 to VCC
−
−50
ICC, IGND
DC VCC or GND current
−
±100
mA
Tstg
storage temperature
−65
+150
°C
PD
power dissipation per packages
−
1000
mW
for temperature range:
−40 to +85 °C; note 2
mA
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of PD derates linearly with 1.8 mW/K.
2000 Mar 16
6
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
VIL
VOH
VOL
−40 to +85
PARAMETER
VCC (V)
OTHER
VIH
Tamb (°C)
TYP.(1)
MIN.
UNIT
MAX.
HIGH-level input
voltage
2.3 to 2.7
1.7
1.2
−
V
2.7 to 3.6
2.0
1.5
−
V
LOW-level input
voltage
2.3 to 2.7
−
1.2
0.7
V
2.7 to 3.6
−
1.5
0.8
V
HIGH-level output
voltage
LOW-level output
voltage
VI = VIH or VIL
IO = −100 µA
2.3 to 3.6
VCC − 0.2
VCC
−
V
IO = −6 mA
2.3
VCC − 0.3
VCC − 0.08 −
V
IO = −12 mA
2.3
VCC − 0.6
VCC − 0.26 −
V
IO = −12 mA
2.7
VCC − 0.5
VCC − 0.14 −
V
IO = −12 mA
3.0
VCC − 0.6
VCC − 0.09 −
V
IO = −24 mA
3.0
VCC − 1.0
VCC − 0.28 −
V
VI = VIH or VIL
IO = 100 µA
2.3 to 3.6
−
GND
0.20
V
IO = 6 mA
2.3
−
0.07
0.40
V
IO = 12 mA
2.3
−
0.15
0.70
V
IO = 12 mA
2.7
−
0.14
0.40
V
IO = 24 mA
3.0
−
0.27
0.55
V
II
input leakage current
VI = VCC or GND
2.3 to 3.6
−
±0.1
±5
µA
IOZ
3-state output
OFF-state current
VI = VIH or VIL;
2.3 to 3.6
VO = VCC or GND; note 2
−
0.1
±10
µA
ICC
quiescent supply
current
VI = VCC or GND; IO = 0
2.3 to 3.6
−
0.4
80
µA
∆ICC
additional quiescent
supply current given
per data I/O pin with
bus-hold
VI = VCC − 0.6 V; IO = 0
2.7 to 3.6
−
150
750
µA
IBHL
bus-hold LOW
sustaining current
VI = 0.7 V; note 3
2.3
45
−
−
µA
VI = 0.8 V; note 3
3.0
75
150
−
µA
IBHH
bus-hold HIGH
sustaining current
VI = 1.7 V; note 3
2.3
−45
−
−
µA
VI = 2.0 V; note 3
3.0
−75
−175
−
µA
IBHLO
bus-hold LOW
overdrive current
note 3
3.6
500
−
−
µA
IBHHO
bus-hold HIGH
overdrive current
note 3
3.6
−500
−
−
µA
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For I/O ports, the parameter IOZ includes the input leakage current.
3. Valid for data inputs of bus-hold parts.
2000 Mar 16
7
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
AC CHARACTERISTICS
GND = 0 V
TEST CONDITIONS
SYMBOL
PARAMETER
WAVEFORMS
CL
Tamb = −40 to +85 °C
MIN.
TYP.
UNIT
MAX.
VCC = 2.3 to 2.7 V; tr = tf ≤ 2.0 ns; note 1
tPHL/tPLH
propagation delay
nAn to nBn; nBn to nAn
see Figs 4 and 8 30 pF
1.0
2.8
5.1
ns
nLEBA to nAn; nLEAB to nBn
see Figs 5 and 8
1.1
3.5
6.1
ns
nCPBA to nAn; nCPAB to nBn
see Figs 5 and 8
1.0
3.3
6.1
ns
3-state output enable time nOEAB to nBn
see Figs 6 and 8
1.0
2.5
5.8
ns
3-state output enable time nOEBA to nAn
see Figs 6 and 8
1.3
2.8
6.3
ns
tPHZ/tPLZ
3-state output disable time nOEAB to nBn
see Figs 6 and 8
1.5
2.5
6.2
ns
3-state output disable time nOEBA to nAn
see Figs 6 and 8
1.3
2.5
5.3
ns
tW
nLEAB or nLEBA pulse width HIGH
see Figs 5 and 8
3.3
0.8
−
ns
nCPAB or nCPBA pulse width
HIGH or LOW
see Figs 5 and 8
3.3
2.0
−
ns
set-up time
see Figs 7 and 8
nAn before nCPAB↑ or nBn before nCPBA↑
1.7
0.1
−
ns
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA↓
see Figs 7 and 8
1.1
0.1
−
ns
hold time
nAn after nCPAB↑ or nBn after nCPBA↑
see Figs 7 and 8
1.7
0.3
−
ns
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA↓
see Figs 7 and 8
1.6
0.3
−
ns
maximum clock frequency
see Figs 5 and 8
150
330
−
MHz
nAn to nBn; nBn to nAn
see Figs 4 and 8 50 pF
−
3.0
4.6
ns
nLEBA to nAn; nLEAB to nBn
see Figs 5 and 8
−
3.6
5.3
ns
nCPBA to nAn; nCPAB to nBn
tPZH/tPZL
tsu
th
fmax
VCC = 2.7 V; tr = tf ≤ 2.5 ns; note 2
tPHL/tPLH
propagation delay
see Figs 5 and 8
−
3.4
5.6
ns
3-state output enable time nOEAB to nBn
see Figs 6 and 8
−
2.7
5.3
ns
3-state output enable time nOEBA to nAn
see Figs 6 and 8
−
3.3
6.0
ns
tPHZ/tPLZ
3-state output disable time nOEAB to nBn
see Figs 6 and 8
−
3.6
5.7
ns
3-state output disable time nOEBA to nAn
see Figs 6 and 8
−
3.3
4.6
ns
tW
pulse width nLEAB or nLEBA HIGH
see Figs 5 and 8
3.3
0.7
−
ns
pulse width nCPAB or nCPBA
HIGH or LOW
see Figs 5 and 8
3.3
1.4
−
ns
tPZH/tPZL
2000 Mar 16
8
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
TEST CONDITIONS
SYMBOL
PARAMETER
WAVEFORMS
tsu
th
fmax
CL
Tamb = −40 to +85 °C
MIN.
TYP.
UNIT
MAX.
set-up time
see Figs 7 and 8 50 pF
nAn before nCPAB↑ or nBn before nCPBA↑
+1.4
−0.1
−
ns
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA↓
see Figs 7 and 8
+1.0
−0.2
−
ns
hold time
nAn after nCPAB↑ or nBn after nCPBA↑
see Figs 7 and 8
1.6
0.3
−
ns
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA↓
see Figs 7 and 8
1.5
0.1
−
ns
maximum clock frequency
see Figs 5 and 8
150
333
−
MHz
nAn to nBn; nBn to nAn
see Figs 4 and 8 50 pF
1.0
3.0
4.2
ns
nLEBA to nAn; nLEAB to nBn
see Figs 5 and 8
1.3
3.4
4.8
ns
nCPBA to nAn; nCPAB to nBn
VCC = 3.0 to 3.6 V; tr = tf ≤ 2.5 ns; note 3
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
tW
tsu
th
fmax
propagation delay
see Figs 5 and 8
1.4
3.3
4.9
ns
3-state output enable time nOEAB to nBn
see Figs 6 and 8
1.0
2.4
4.6
ns
3-state output enable time nOEBA to nAn
see Figs 6 and 8
1.1
2.5
5.0
ns
3-state output disable time nOEAB to nBn
see Figs 6 and 8
1.4
2.9
5.0
ns
3-state output disable time nOEBA to nAn
see Figs 6 and 8
1.3
3.1
4.2
ns
pulse width nLEAB or nLEBA HIGH
see Figs 5 and 8
3.3
0.9
−
ns
pulse width nCPAB or nCPBA
HIGH or LOW
see Figs 5 and 8
3.3
1.1
−
ns
set-up time
see Figs 7 and 8
nAn before nCPAB↑ or nBn before nCPBA↑
+1.3
−0.3
−
ns
set-up time CP HIGH or LOW
nAn before nLEAB↓ or nBn before nLEBA↓
see Figs 7 and 8
1.0
0.3
−
ns
hold time
nAn after nCPAB↑ or nBn after nCPBA↑
see Figs 7 and 8
+1.3
−0.4
−
ns
hold time CP HIGH or LOW
nAn after nLEAB↓ or nBn after nLEBA↓
see Figs 7 and 8
1.2
0.1
−
ns
maximum clock frequency
see Figs 5 and 8
150
340
−
MHz
Notes
1. All typical values are measured at VCC = 2.5 V and Tamb = 25 °C.
2. All typical values are measured at Tamb = 25 °C.
3. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
2000 Mar 16
9
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
AC WAVEFORMS
handbook, halfpage VI
nAn, nBn
VM
input
GND
t PHL
t PLH
VOH
nBn, nAn
VM
output
VOL
VM
VCC
MNA564
VI
2.3 to 2.7 V
0.5 × VCC
VCC
2.7 V
1.5 V
2.7 V
3.0 to 3.6 V
1.5 V
2.7 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.4 Input nAn, nBn to output nBn, nAn propagation delay times.
1/fmax
handbook, full pagewidth
nLEAB, nLEBA,
nCPAB, nCPBA
input
VI
VM
GND
tW
t PHL
t PLH
VOH
nAn, nBn
VM
output
VOL
VCC
VM
MNA565
VI
2.3 to 2.7 V
0.5 × VCC
VCC
2.7 V
1.5 V
2.7 V
3.0 to 3.6 V
1.5 V
2.7 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5
Latch enable input (nLEAB, nLEBA) and clock input (nCPAB, nCPBA) to output propagation delays and their
pulse width.
2000 Mar 16
10
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
OEAB input
handbook, full pagewidth
VM
VM
OEBA input
t PLZ
output
LOW-to-OFF
OFF-to-LOW
t PZL
VCC
VM
VX
VOL
t PHZ
output
HIGH-to-OFF
OFF-to-HIGH
t PZH
VOH
VY
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA566
VCC
VM
VX
VY
VI
2.3 to 2.7 V
0.5 × VCC
VOL + 150 mV
VOH − 150 mV
VCC
2.7 V
1.5 V
VOL + 300 mV
VOH − 300 mV
2.7 V
3.0 to 3.6 V
1.5 V
VOL + 300 mV
VOH − 300 mV
2.7 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.6 3-state enable and disable times.
VI
handbook, full pagewidth
nAn, nBn
VM
input
GND
th
nLEAB, nLEBA,
th
tsu
tsu
VI
nCPAB, nCPBA
input
GND
VM
MNA567
The shaded areas indicate when the input is permitted to change for predictable output performance.
VCC
VM
VI
2.3 to 2.7 V
0.5 × VCC
VCC
2.7 V
1.5 V
2.7 V
3.0 to 3.6 V
1.5 V
2.7 V
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 Data set-up and hold times for the nAn and nBn inputs to the nLEAB, nLEBA, nCPAB and nCPBA inputs.
2000 Mar 16
11
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
S1
handbook, full pagewidth
VCC
PULSE
GENERATOR
VI
RL
500 Ω
VO
2 × VCC
open
GND
D.U.T.
CL
50 pF
RT
RL
500 Ω
MNA479
TEST
S1
tPLH/tPHL
open
tPLZ/tPZL
2 × VCC
tPHZ/tPZH
GND
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Z0 of the pulse generator.
Fig.8 Load circuitry for switching times.
2000 Mar 16
12
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
PACKAGE OUTLINE
LFBGA114: plastic low profile fine-pitch ball grid array package; 114 balls; body 16 x 5.5 x 1.05 mm SOT537-1
A
B
D
ball A1
index area
A2
A
E
A1
detail X
C
e1
v M B
b
e
y1 C
∅w M
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
y
v M A
e
e2
X
1 2 3 4 5 6
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
b
D
E
e
e1
e2
v
w
y
y1
mm
1.5
0.41
0.31
1.2
0.9
0.51
0.41
5.6
5.4
16.1
15.9
0.8
4.0
14.4
0.15
0.1
0.1
0.2
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
5
10 mm
scale
EUROPEAN
PROJECTION
ISSUE DATE
99-12-02
00-03-04
SOT537-1
2000 Mar 16
0
13
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
SOLDERING
74ALVCH32501
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Mar 16
14
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
5 V tolerant; 3-state
74ALVCH32501
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, LFBGA, SQFP, TFBGA
not suitable
suitable(2)
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Mar 16
15
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SCA 69
© Philips Electronics N.V. 2000
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613507/01/pp16
Date of release: 2000
Mar 16
Document order number:
9397 750 06819