INTEGRATED CIRCUITS DATA SHEET SAA7282 Terrestrial Digital Sound Decoder (TDSD2) Product specification File under Integrated Circuits, IC02 July 1993 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 FEATURES • Full EBU NICAM 728 specification decoder • Microcomputer controlled via I2C-bus • Automatic decoding and output configuration depending upon transmission: – digital stereo – error count byte – digital mono and data – additional data bits – 2 independent mono signals • On board RAM for de-interleaving and 10 to 14-bit word expansion and write: • Automatic mute function which silences the digital data and switches to FM sound (if valid) when error rate exceeds user definable limit – decoder control – switch control codes – upper and lower error rate limits. • User mute function (MUTE pin) to enable user to perform muting to their own software algorithm if required, or to simply silence the output APPLICATIONS • Television receivers • Video cassette recorders. • 4 times over-sampling digital filter • Selectable digital de-emphasis • 256 times over-sampling Noise Shapers GENERAL DESCRIPTION • Fully integrated 1-bit DACs Performing all digital decoding functions for a NICAM 728 digital stereo sound system, the SAA7282 is a highly integrated CMOS circuit which only requires a DQPSK (Differential Quadrature Phase Shift Keying) demodulator (TDA8732) and minimum external components to achieve a full NICAM solution. The device may also be interfaced to other DQPSK demodulators. • Integrated switching networks allowing selection between NICAM Sound, FM Sound or external “Daisy-Chain” input • Digital Audio Interface conforming with EBU/IEC 958 • I2C-bus transceiver enabling a master device to read – status information QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD positive supply voltage 4.5 5.0 5.5 V IDD supply current − 50 100 mA fXTAL crystal frequency − 8.192 − MHz Tamb operating ambient temperature 0 − 70 °C ORDERING INFORMATION EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE SAA7282ZP 32 DIL32SHR plastic SOT232A(1) SAA7282GP 44 QFP plastic SOT205AG(2) Note 1. SAA7282ZP: 32-DIL32SHR; plastic (SOT232A); SOT232-1; 1996 November 28. 2. SAA7282GP: 44-QFP; plastic (SOT205AG); SOT205-1; 1996 November 28. July 1993 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... PORT2 5 4 18 6 19 INTL 20 25 VRC 2 I C 2 24 1-BIT DAC 23 NOISE SHAPER 21 AUTO MUTE 22 32 NICAM 728 DECODING 10 FILTER DE-EMPH BIAS 26 DIGITAL AUDIO INTERFACE i.c. 11 VSS 27 14 NOISE SHAPER 12 29 FREQ. SYNTH. 1-BIT DAC XTAL OSC 8 VRC 9 1 30 31 7 28 17 16 15 OPL FML EXTL VRO VRC EXTR FMR OPR V DDAR V SSAR MLB152 PCLK XIN XOUT MUTE DOBM V REF CDR INTR Product specification Fig.1 Block diagram; pin numbering for SOT232A. SAA7282 handbook, full pagewidth 3 DIGITAL SWITCHING 13 VDD VSSAL SAA7282ZP RESET DATA V DDAL Philips Semiconductors 3 CDL Terrestrial Digital Sound Decoder (TDSD2) July 1993 VDAC SCL SDA ADSEL Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 PINNING SYMBOL SOT205AG SOT232A DESCRIPTION DOBM 1 28 digital audio interface output VSS 2 29 ground connection for the digital section n.c. 3 − not connected XIN 4 30 crystal input at 256fs (8.192 MHz) XOUT 5 31 crystal output at 256fs (8.192 MHz) DATA 6 32 serial data input at 728 kbits/s from DQPSK demodulator PCLK 7 1 output clock at 728 kHz to DQPSK demodulator RESET 8 2 active LOW reset; used to set the device in a valid initial condition SCL 9 3 clock input for I2C control bus SDA 10 4 data port for I2C control bus, input/open drain output PORT2 11 5 output mirroring the I2C control register bit PORT2 n.c. 12 − not connected ADSEL 13 6 I2C-bus slave address selection input; allows selection of one of two separate slave addresses, defaults to logic 1 MUTE 14 7 active LOW mute input; when set LOW, sets the digital data to zero and either silences the output or switches it to analog FM, depending on the status of MUTEDEF (control bit in the I2C register) and RSSF; overridden by automute (if automute is used, then MUTE is automatically pulled LOW) 15 to 17 − not connected VDDAR 18 8 analog supply voltage for the right audio channel VSSAR 19 9 analog ground connection for the right audio channel VRO 20 10 internal reference voltage buffer output VRC 21 11 internal reference voltage buffer HIGH impedance node n.c. n.c. 22 − not connected OPR 23 12 analog output from the right audio channel EXTR 24 13 external analog input to the right audio channel FMR 25 14 FM sound input to the right audio channel INTR 26 15 integrator output from the right audio channel CDR 27 16 integrator connection to an external damping capacitor n.c. 28 − not connected VREF 29 17 reference voltage input; 2.5 V (typical) VDAC 30 18 quiet VSS to DACs CDL 31 19 integrator connection to an external damping capacitor INTL 32 20 integrator output from the left audio channel FML 33 21 FM sound input to the left audio channel EXTL 34 22 external analog input to the left audio channel OPL 35 23 analog output from the left audio channel n.c. 36 − not connected VSSAL 37 24 analog ground connection for the left audio channel VDDAL 38 25 analog supply voltage for the left audio channel July 1993 4 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SYMBOL SOT205AG SOT232A SAA7282 DESCRIPTION 39 to 41 − not connected i.c. 42 26 internally connected; must be left open-circuit in application n.c. 43 − not connected VDD 44 27 digital supply voltage n.c. handbook, halfpage PCLK 1 32 DATA RESET 2 31 XOUT SCL 3 30 XIN SDA 4 29 V SS PORT2 5 28 DOBM ADSEL 6 27 VDD MUTE 7 26 i.c. VDDAR 8 V SSAR 25 VDDAL SAA7282ZP 9 24 VSSAL VRO 10 23 OPL VRC 22 EXTL 11 OPR 12 21 FML EXTR 13 20 INTL FMR 14 19 CDL INTR 15 18 VDAC CDR 16 17 VREF MLB153 Fig.2 Pin configuration (SOT232A). July 1993 5 Philips Semiconductors Product specification 34 EXTL 35 OPL SAA7282 36 n.c. 37 VSSAL 38 VDDAL 39 n.c. 40 n.c. 41 n.c. 42 i.c. handbook, full pagewidth 43 n.c. 44 VDD Terrestrial Digital Sound Decoder (TDSD2) DOBM 1 33 FML V SS 2 32 INTL n.c. 3 31 CDL XIN 4 30 V DAC XOUT 5 29 VREF DATA 6 28 n.c. SAA7282GP PCLK 7 27 CDR RESET 8 26 INTR SCL 9 25 FMR SDA 10 24 EXTR 23 OPR n.c. 22 VRC 21 VRO 20 V SSAR 19 n.c. 17 VDDAR 18 n.c. 16 n.c. 15 MUTE 14 ADSEL 13 n.c. 12 PORT2 11 Fig.3 Pin configuration (SOT205AG). July 1993 6 MLB154 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 I2C-BUS FORMATS The SAA7282 contains an I2C-bus slave transceiver permitting a master device to: • Read decoder status information derived from the transmitted digital audio signal • Read an error count byte to determine the bit error rate for user mute purposes and to indicate quality of NICAM signal • Read additional transmitted data bits. Their purpose has yet to be defined but accessibility is provided to allow future services to be implemented in receiver software • Write control codes to select the available analog switching configurations • Write upper and lower error count limits for automatic muting function The device slave address is A(7:1)(R/W) = 101101X(R/W). An ADSEL pin is provided to allow selection of one of two different slave addresses via programmable address bit A1. (X = ADSEL logic level). The SAA7282 does not acknowledge the I2C-bus general call address. The slave receiver format is: S SLAVE_ADDR.0 ACK SUB_ADDR ACK DATA BYTE ACK P <−n bytes−> Where S = start, ACK = acknowledge, P = stop. Auto-increment of the sub-address is provided with wrap-around from 02 (HEX) to 00 (HEX). The slave receiver data byte format, as a function of sub-address, is as shown in Table 1. Table 1 Slave receiver data byte. SUBADDRESS RESET VALUE HEX D7 D6 D5 D4 D3 D2 D1 D0 00 90 M1/M2 DMSEL SSWIT3 SSWIT2 SSWIT1 PORT2 MUTEDEF AMDIS 01 50 EMAX7 EMAX6 EMAX5 EMAX4 EMAX3 EMAX2 EMAX1 EMAX0 10 14 EMIN7 EMIN6 EMIN5 EMIN4 EMIN3 EMIN2 EMIN1 EMIN0 M1/M2 This bit in conjunction with DMSEL bit, determines the output configuration in dual mono mode (see Table 2). Power-on resets to logic 1. DMSEL This bit determines whether one or both of the dual mono signals are output (see Table 2). Power-on resets to logic 0. PORT2 PORT2 controls a bit out, providing direct access to a dedicated output pin (PORT2) via the I2C-bus. See Table 3. Power-on resets to logic 0. SSWIT3/2/1 These bits control the analog switching, selecting between the FM, external, and NICAM signals. With the NICAM source the signals select whether the de-emphasis is performed and what gain is applied after the filtering and de-emphasis stage. The signal states and their meaning are listed in Table 4. Power-on resets to 0/1/0. July 1993 7 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 AMOGMDIS ERROR LIMIT REGISTERS This bit enables and disables the automute function (which is activated according to the error limit registers). Power-on resets to enabled (i.e. AMDIS = logic 0). AMDIS should be disabled for the user definable mute (MUTE) to be used. UPPER ERROR LIMIT REGISTER This defines the number of errors in 128 ms period which will cause automute to switch IN. User definable, but power on resets to 50 Hex. LOWER ERROR LIMIT REGISTER MUTEDEF This defines the number of errors in 128 ms period which will cause automute to switch OUT. User definable, but power on resets to 14 Hex. This defines the operation of the user definable MUTE pin when it is pulled LOW externally. If MUTEDEF is HIGH and RSSF = logic 1, the output of the device is switched to FM input. If MUTEDEF is HIGH and RSSF = logic 0, or if MUTEDEF is LOW, the output is muted. Power on resets to LOW. Table 2 Output as a function of M1/M2 and DMSEL. DMSEL M1/M2 FUNCTION 0 0 selects DIGITAL; L = M2, R = M2 0 1 selects DIGITAL; L = M1, R = M1 1 0 selects DIGITAL; L = M2, R = M1 1 1 selects DIGITAL; L = M1, R = M2 Table 3 Table 4 Port 2 control. PORT2 PIN OUTPUT STATE 0 LOW 1 HIGH SSWIT signal states and function.(1) SSWIT3 SSWIT2 SSWIT1 FUNCTION 0 0 0 NICAM source de-emphasis switched out, no gain 0 0 1 NICAM source de-emphasis switched in, no gain 0 1 0 NICAM source de-emphasis switched in, −6 dB gain; power-on reset state 0 1 1 NICAM source de-emphasis switched in, +12 dB gain 1 x 0 external inputs switched in, no change to previous de-emphasis/gain setting 1 x 1 FM inputs switched in, no change to previous de-emphasis/gain setting Note 1. Where x = don’t care. July 1993 8 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 Slave Transmitter The slave transmitter formats are illustrated thus: • S SLAVE_ADDR.1 A STATUS_BYTE NA P In this format the bus master reads the STATUS_BYTE once. • S SLAVE_ADDR.1 A STATUS_BYTE A ERROR_BYTE NA P In this format the bus master reads two bytes of STATUS_BYTE and ERROR_BYTE. • S SLAVE_ADDR.1 A STATUS_BYTE A ERROR_BYTE A AD_BYTE_0 A AD_BYTE_1 NA P In this format the bus master reads four bytes of STATUS_BYTE, ERROR BYTE and two additional bytes, AD_BYTE_0 and AD_BYTE_1. The additional data bytes contain the eleven additional data bits AD0 to AD10 together with information regarding their status. Where NA = no acknowledge. Table 5 Data byte formats. BYTE D7 D6 D5 D4 D3 D2 D1 D0 STATUS_BYTE PONRES S/M D/S VDSP RSSF OS AM CFC ERROR_BYTE E7 E6 E5 E4 E3 E2 E1 E0 AD_BYTE_0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 AD_BYTE_1 OVW SAD 0 CI2 CI1 AD10 AD9 AD8 The bits may be defined as follows: RSSF PONRES RSSF is the reserve sound switching flag indication equal to the C4 bit in the NICAM transmission. RSSF = logic 1 when the FM sound signal is carrying the same programme material as the digitally modulated carrier (specifically the M1 signal in the event of a dual mono transmission). RSSF = logic 0 when the FM signal is not reproduced within the digital signal. This bit is a power-on reset detection bit. It is set HIGH after a power-on reset or supply reduction and is cleared LOW when the STATUS_BYTE is read. S/M (stereo/mono indication) S/M = logic 1 indicating an incoming stereo transmission. S/M = logic 0 indicating that the incoming transmission is not stereo. OS This bit provides an active LOW indication that the decoder is out of sync. If OS = logic 1 the decoder is frame synchronized and has obtained C0 (16 frame) sync. If OS = logic 0, the decoder is out of sync and the indicator bits are as given in Table 6. D/S (dual/single mono indication) D/S = logic 1 indicating an incoming dual mono transmission. D/S = logic 0 indicating that the incoming transmission is not dual mono. AM VDSP This bit indicates when the automuting function has switched from the NICAM sound to the conventional FM sound. This enables the software controller to display the relevant information to the customer, for example, on screen display. If AM bit = logic 0 no switching has been carried out by the automuting function. If AM bit = logic 1 then the automuting function has switched to the FM inputs. This bit indicates that the decoded signal is valid digital sound. When VDSP = logic 0 the incoming transmission carries either a 704 kbit/s transparent data channel or a currently undefined format and the device automatically switches to FM regardless of RSSF. July 1993 9 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 CFC OVW Signals a change of configuration at the 16-frame boundary. It is cleared to logic 1 by the I2C-bus reading the status register. OVW is the overwrite indicator for the additional data. This bit is set when the transmission overwrites additional data bits which have not been read by the bus master. This bit is automatically reset to logic 0 when AD_BYTE_1 is read by the bus master. E7 to E0 This is an error count byte which counts the number of error flags in a 128 ms period. The register is updated every 128 ms. CI1 to CI2 These represent the CI bits which are extracted by a majority logic process from the parity checks of the last ten samples in a frame (samples 55 to 64). CI1 will be conveyed by the parity grouping of samples 55 to 59 and CI2 will be conducted by the parity grouping of samples 60 to 64. Both parity groups will be even for UK transmissions such that CI2 = logic 0 and CI1 = logic 0. The transmissions of countries following the specification issued by the EBU (Document SPB424; “Digital sound transmissions in terrestrial television”) will allow odd or even parity groups, thus providing an additional 2 kbit/s data capacity. AD10 to AD0 These are the additional data bits from the transmission and are updated every 1 ms.This provides a data capacity of 11 kbit/s. SAD SAD is the 'status additional data' bit. This is set to logic 1 when new bits AD10 to AD0 are latched into the I2C-bus registers. It is automatically reset to logic 0 when AD_BYTE_1 is read by the bus master. Table 6 Indicator bits functional truth table. C1 C2 C3 S/M D/S VDSP OS Stereo 0 0 0 1 0 1 1 M1 + M2 0 1 0 0 1 1 1 M1 + data 1 0 0 0 0 1 1 Transparent data 1 1 0 0 0 0 1 0 0 0 1 note 1 note 1 0 0 TRANSMISSION Any currently undefined combination of C1, C2, C3 Decoder unsynchronized (OS = logic 0) Note 1. Holds last value before synchronization loss or stereo (S/M = logic 1; D/S = logic 0) if synchronization not achieved since power-on reset. July 1993 10 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 DIGITAL AUDIO INTERFACE IEC/EBU 958 Sub-frame structure Block structure Each frame is divided into 32 time-slots numbered 0 to 31. The output is grouped into a block of 192 consecutive frames providing, for each channel the 192 channel status data bits. The start of a block is designated by a special sub-frame preamble. Time-slots 0 to 3 carry one of three permitted preambles. These are used to affect synchronization of sub-frames, frames and blocks. Time-slots 4 to 27 carry the audio sample word in linear two's complement representation. The most significant bit is carried by time-slot 27. Frame structure Each frame is uniquely composed of two sub-frames. The rate of transmission of frames corresponds exactly to the source sampling frequency. In the 2-channel operation, samples taken from both channels are transmitted by time multiplexing in consecutive sub-frames. Sub-frames related to Channel 1 (left or 'A' channel in stereophonic operation and primary channel in monophonic operation) normally use preamble M. However the preamble is changed to preamble B once every 192 frames. This defines the block structure used to organize the channel status information. Sub-frames of Channel 2 (right or 'B' channel in stereophonic operation and secondary channel in monophonic operation) always use preamble W. handbook, full pagewidth M W channel 1 B channel 2 Time-slot 28 carries the validity flag associated with the audio sample word. This flag is set to logic 0 if the audio sample is reliable. If set to logic 1 then the sample is unreliable. Time-slot 29 carries one bit of the user data channel. In this application this is not used and so is set to logic 0. Time-slot 30 carries one bit of the channel status world associated with the audio channel transmitted in the same sub-frame. Time-slot 31 carries a parity bit such that time-slots 4 to 31 inclusive will carry an even number of ones and an even number of zeros. W channel 1 sub-frame frame 191 channel 2 M channel 1 W channel 2 sub-frame frame 1 frame 0 start of block MLB155 Fig.4 Frame format. 3 4 0 sync preamble 27 28 11 12 handbook, full pagewidth logical 0 bits L S B M S B audio sample word MLB156 validity flag user data = logic 0 channel status parity bit Fig.5 Sub-frame format. July 1993 11 31 V U C P Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 Channel coding Preambles Time-slots are encoded as biphase mark data. Each bit transmitted is represented by a symbol comprising two consecutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit being transmitted is logic 0, however it is different if the bit is logic 1 (see Table 7). Preambles are specific patterns providing synchronization and identification of the sub-frames and blocks. A set of three preambles is used. These preambles are transmitted in the time allocated to four time-slots and are represented by eight successive states. The first state of the preamble is always different from the second state of the previous symbol. Depending on this state the preambles are as shown in Table 8. Table 7 Table 8 Channel coding. Preceding state 0 Transmitted bit Channel coding Preceding state 1 0 11 00 1 10 01 Preambles. Preamble 0 1 Channel coding B 11101000 00010111 M 11100010 00011101 W 11100100 00011011 The preambles preceding each digital audio sample are used to indicate the beginning of a sample as follows: • Preamble B indicates the start of Channel A data and the beginning of a block • Preamble M indicates the start of Channel A data but not the beginning of a block • Preamble W indicates the start of Channel B data. Channel status The channel status information is organized in 192-bit words. The first bit of each word is carried in the frame with Preamble B. The 192-bit word is organized into sections as shown in Table 9. Table 9 Channel status codes. BIT CODE 0 0 consumer 1 0 sound data 2 1 digital copy permitted 3, 4 00 indicates digital de-emphasis switched in 11 indicates digital de-emphasis switched out 5 DESCRIPTION 0 6, 7 00 8 to 15 00110001 16 to 19 0000 source code (don't care) 20 to 23 0000 channel number (don't care) 24 to 27 1100 sampling frequency (32 kHz) 28, 29 00 30 to 191 all 0s July 1993 category code clock accuracy (level II) 12 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage (all supplies) −0.5 +6.5 V VI(max) maximum input voltage (any input) −0.5 VDD+0.5 V VO(max) maximum output voltage −0.3 VDD+0.5 V IIOK DC input or output diode current − ±20 mA IO(max) output current (each output) − ±10 mA Tamb ambient operating temperature 0 +70 °C Tstg storage temperature −55 +125 °C Vstat electrostatic handling −2000 +2000 V note 1 notes 2 and 3 Notes 1. All VDD and VSS connections must be made externally to the same power supply. 2. Electrostatic handling is equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor with a 15 ns rise time. 3. 1000 V VSSAL pin. July 1993 13 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 CHARACTERISTICS VDD = 4.5 to 5.5 V; Tamb = 0 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage IDD total supply current see Fig.9 VSS,VSSAL ground supply voltage VSSAR,VDAC VDDAL, VDDAR analog supply voltage see Fig.9 4.5 5.0 5.5 V − 50 100 mA 0 − 0 V 4.5 5.0 5.5 V Digital inputs DATA VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDD V ILI input leakage current −10 − +10 µA CI input capacitance − − 10 pF 0 − 0.8 V ADSEL (this pin is internally pulled HIGH when not connected) VIL LOW level input voltage VIH HIGH level input voltage 2.0 − VDD V ZI input impedance − 50 − kΩ CI input capacitance − − 10 pF RESET (Schmitt trigger input) VIL LOW level input voltage 0 − 1.5 V VIH HIGH level input voltage 3.0 − VDD V Vhys hysteresis 0.05VDD − − V VIL LOW level input voltage 0 − 1.5 V VIH HIGH level input voltage 3.0 − VDD V SCL Vhys hysteresis 0.05VDD − − V ILI input leakage current −10 − +10 µA CI input capacitance − − 10 pF July 1993 14 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SYMBOL PARAMETER SAA7282 CONDITIONS MIN. TYP. MAX. UNIT Digital input/output SDA VIL LOW level input voltage 0 − 1.5 V VIH HIGH level input voltage 3.0 − VDD V Vhys hysteresis 0.05VDD − − V ILI input leakage current −10 − +10 µA CI input capacitance − − 10 pF VOL LOW level output voltage 0 − 0.4 V CL load capacitance active pull-up − − 400 pF passive pull-up − − 200 pF IOL = 3 mA MUTE I/O (this pin has an internal pull-up) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VDD V − − 10 pF 0 − 0.4 V CI input capacitance VOL LOW level output voltage VOH HIGH level output voltage 2.4 − VDD V CL load capacitance − − 50 pF ZI input impedance − 50 − kΩ IOL = 2.8 mA Digital outputs PORT2, PCLK, DOBM VOL LOW level output voltage IOL = 2.8 mA 0 − 0.4 V VOH HIGH level output voltage IOH = 800 µA 2.4 − VDD V CL load capacitance − − 50 pF − 8.192 − MHz Crystal oscillator fc crystal frequency gm mutual conductance at 100 kHz 1.5 − − mA/V Av small signal gain Av = gm.Ro 3.5 − − V/V CI input capacitance − − 10 pF CFB feedback capacitance − − 5 pF CO output capacitance − − 10 pF VIL LOW level input voltage 0 − 1 V VIH HIGH level input voltage 3.5 − VDD V ILI input leakage current −10 − +10 µA CI input capacitance − − 10 pF XIN July 1993 15 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SYMBOL PARAMETER SAA7282 CONDITIONS MIN. TYP. MAX. UNIT Digital filter specification fs output sample frequency − 128 − kHz PR pass band ripple at 0 Hz to 15 kHz − − ±0.01 dB SBA stop band attenuation at f ≥17 kHz 30 − − dB − − ±0.09 dB 0.45VDDAR 0.5VDDAR 0.55VDDAR V − 0.5VDD − V Digital de-emphasis DEV deviation from ideal ANALOG SECTION (measured at VDD = 5 V and Tamb = 25 °C) Reference voltage buffer VRC output Vrc voltage reference at VRC see Fig.10 DACs VREF input Vref reference input voltage Switching operational amplifiers CL output load capacitance − − 300 pF RL output load resistance 3 − − kΩ ZO output impedance − 150 − Ω G output gain −0.35 0 +0.35 dB PSRR power supply rejection ratio − 40 − dB External inputs selected (FML, FMR, EXTL, EXTR) Vain input voltage level (RMS value) − − 1.1 V S/N signal-to-noise ratio (relative to 1 V RMS, unity gain) FM or EXT 90 100 − dB THD total harmonic distortion (unity gain, O/P = 1 V RMS) FM or EXT − −90 −70 dB CHM channel matching FM or EXT, 1 kHz − 0 0.5 dB NICAM inputs selected (INTL, INTR) Vain input voltage level (RMS value) at 0 dB; VREF = 2.5 V 0.9 1.0 1.1 V THD+N total harmonic distortion plus noise NICAM 728; notes 2 and 3 − −80 −75 dB CHM channel matching 0 dB, 1 kHz − 0 0.5 dB DIGS digital silence level MUTE on − −80 − dB Timing (all timing values refer to VIH and VIL levels) DATA with respect to PCLK (see Fig.7) tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 250 − − ns July 1993 16 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SYMBOL PARAMETER SAA7282 CONDITIONS MIN. TYP. MAX. UNIT SDA with respect to SCL (see Fig.8) fSCL SCL clock frequency 0 − 400 kHz tBUF bus free time 1300 − − ns tHD;STA start code hold time 600 − − ns tLOW SCL clock LOW time 1300 − − ns tHIGH SCL clock HIGH time 600 − − ns tSU;STA start code set-up time 600 − − ns tHD;DAT data hold time note 4 0 − − ns tSU;DAT data set-up time note 5 100 − − ns tr SDA and SCL rise time 50 − 300 ns tf SDA and SCL fall time 50 − 300 ns tSU;STO stop code set-up time 600 − − ns tof output fall time 50 − 200 ns note 6 Notes 1. Outputs OPL and OPR are measured with external components as recommended in Fig.11. 2. Total analog performance is limited by dynamic range of the NICAM 728 system. Due to compansion the quantization noise is never lower than approximately -62 dB with respect to the input level. 3. Measured with a -30 dB, 1 kHz NICAM 728 input signal. 4. Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. 5. If a fast I2C-bus device is used in an up to 100 kbit/s I2C-bus system, then the requirement tSU;DAT ≥250 ns is always fulfilled if this device cannot stretch the LOW level of the SCL signal. If a device stretches the LOW level of the SCL signal, then data to SD9A must be asserted (tRD(max) + tSU;DAT) = 1000 + 250 = 1250 ns before the SCL signal is released to be compatible with the up to 100 kbit/s I2C-bus specification. 6. The output fall time is measured between 3.0 V and 1.5 V for a bus capacitance of 400 pF and an active pull-up. July 1993 17 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) UHF handbook, full pagewidth INPUT TUNER SAA7282 SAW FILTER VISION IF DEMODULATOR (TDA3852) COMPOSITE VIDEO DOBM I2 C-bus EXTL EXTR I 2C DAI AUDIO O/P R FILTER DAC + SWITCHES 8.192 MHz AUTO - MUTE AUDIO O/P L NICAM DECODER 6 MHz (I) SAA7282 5.5 MHz (B/G) DATA 6.552 MHz (I) PCLK FML FMR PHILIPS DQPSK DEMODULATOR (TDA8732) NIDEM SOUND DEMODULATOR (TDA3857) 5.85 MHz (B/G) 13.104 MHz (I) 11.7 MHz (B/G) ANALOG FM SOUND MLB157 Fig.6 System block diagram showing SAA7282 with TDA8732. July 1993 18 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 handbook, full pagewidth PCLK DATA t SU;DAT MLB158 t HD;DAT Fig.7 Data output timing. t BUF t CYC handbook, full pagewidth SDA t HD;STA tr t HD;STA tf SCL P S t LOW t HD;DAT t HIGH t SU;DAT REPEATED START CONDITION STOP START CONDITION CONDITION Fig.8 I2C-bus interface timing. July 1993 t SU;STA Sr 19 t SU;STO P MLA396 - 1 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) handbook, full pagewidth SAA7282 supply 10 Ω 47 µF 100 nF 22 Ω 22 Ω 47 µF 100 nF VDDAR V DDAL 8 25 VDD 27 SAA7282ZP MEA257 - 1 Fig.9 VDD external circuitry. 10 Ω handbook, full pagewidth supply 100 nF 47 µF V DDAR 8 11 VRC 100 nF 47 µF SAA7282ZP MEA256 - 1 Fig.10 VRC external circuitry (same external circuit values also required for VRO). July 1993 20 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 51 kΩ handbook, full pagewidth 330 pF VREF 68 pF 220 nF 220 nF CDL INTL EXTL FML 19 20 22 21 23 VRC VRC SAA7282ZP OPL MLB159 Fig.11 External circuitry for left channel DAC (same external circuit values also required for right channel DAC). July 1993 21 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 PACKAGE OUTLINES SDIP32: plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1 ME seating plane D A2 A A1 L c e Z (e 1) w M b1 MH b 17 32 pin 1 index E 1 16 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.8 1.3 0.8 0.53 0.40 0.32 0.23 29.4 28.5 9.1 8.7 1.778 10.16 3.2 2.8 10.7 10.2 12.2 10.5 0.18 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT232-1 July 1993 EUROPEAN PROJECTION 22 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm SOT205-1 c y X 33 A 23 34 22 ZE e E HE A A2 (A 3) A1 wM θ bp Lp pin 1 index 44 L 12 detail X 1 11 ZD e v M A wM bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.60 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 14.1 13.9 1 19.2 18.2 19.2 18.2 2.35 2.0 1.2 0.3 0.15 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC SOT205-1 133E01A July 1993 JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 23 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 °C. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. If wave soldering cannot be avoided, the following conditions must be observed: The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). REPAIRING SOLDERED JOINTS During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. QFP REFLOW SOLDERING A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Reflow soldering techniques are suitable for all QFP packages. REPAIRING SOLDERED JOINTS The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). July 1993 Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 24 Philips Semiconductors Product specification Terrestrial Digital Sound Decoder (TDSD2) SAA7282 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. July 1993 25