Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset DESCRIPTION 74F114 PIN CONFIGURATION The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table regardless of the level at the other inputs. A High level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CP. TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 100MHz 15mA 74F114 RD 1 14 VCC K0 2 13 CP J0 3 12 K1 SD0 4 11 J1 Q0 5 10 SD1 Q0 6 9 Q1 GND 7 8 Q1 SF00110 ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG. DWG. # 14-pin plastic DIP N74F114N SOT27-1 14-pin plastic SO N74F114D SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW J0, J1 J inputs 1.0/1.0 20µA/0.6mA K0, K1 K inputs 1.0/1.0 20µA/0.6mA Set inputs (active Low) 1.0/5.0 20µA/3.0mA RD Reset input (active Low) 1.0/10.0 20µA/6.0mA CP Clock Pulse input (active falling edge) 1.0/8.0 20µA/4.8mA Data outputs 50/33 1.0mA/20mA SD0, SD1 Q0, Q0; Q1, Q1 NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 3 11 2 12 1 R 13 J0 13 J1 K0 CP 4 SD0 1 RD0 10 SD1 4 3 2 Q0 Q0 Q1 C1 K1 Q1 10 S 5 1K 1J 6 9 11 12 5 6 9 VCC = Pin 14 GND = Pin 7 SF00112 SF00111 1996 Mar 14 8 8 1 853–0340 16572 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 LOGIC DIAGRAM Q Q SD RD K J CP TO OTHER FLIP-FLOP SF00113 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE SD RD CP J K Q Q L H X X X H L Asynchronous Set H L X X X L H Asynchronous Reset L L X X X H* H* Undetermined * H H ↓ h l q q Toggle H H ↓ l h L H Load “0” (Reset) H H ↓ h l H L Load “1” (Set) H H ↓ l l q q Hold “no change” H = High voltage level h = High voltage level one setup time prior to High-to-Low clock transition L = Low voltage level l = Low voltage level one setup time prior to High-to-Low clock transition q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition X = Don’t care ↓ = High-to-Low clock transition Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level Set and Reset are independent of clock Simultaneous Low on both SD and RD makes both Q and Q High. * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously. ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C 1996 Mar 14 2 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range +70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN TYP2 ±10%VCC 2.5 VIH = MIN, IOH = MAX ±5%VCC 2.7 VCC = MIN, VIL = MAX ±10%VCC 0.35 0.50 VIH = MIN, IOL = MAX ±5%VCC 0.35 0.50 –0.73 –1.2 V VCC = MAX, VI = 7.0V 100 µA VCC = MAX, VI = 2.7V 20 µA –0.6 mA –4.8 mA –3.0 mA –6.0 mA –150 mA 21 mA High-level output voltage VOL Low-level output voltage VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage IIH High-level input current V 3.4 V Jn, Kn CP L Low-level l l input i current SDn VCC = MAX, MAX VI = 0 0.5V 5V RD current3 IOS Short-circuit output ICC Supply current (total)4 UNIT VCC = MIN, VIL = MAX VOH IIL MAX VCC = MAX VCC = MAX –60 15 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, with the Q and Q outputs High in turn. 1996 Mar 14 3 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω TEST CONDITION PARAMETER MIN TYP VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MAX MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 85 100 80 MHz tPLH tPHL Propagation delay CP to Qn or Qn Waveform 1 2.0 2.0 5.0 5.5 6.5 7.5 2.0 2.0 7.5 8.5 ns tPLH tPHL Propagation delay SDn, RD to Qn or Qn Waveform 2,3 2.0 2.0 4.5 4.5 6.5 6.5 2.0 2.0 7.5 7.5 ns TEST CONDITION VCC = +5.0V Tamb = +25°C CL = 50pF, RL = 500Ω AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER MIN TYP MAX VCC = +5.0V ± 10% Tamb = 0°C to +70°C CL = 50pF, RL = 500Ω MIN UNIT MAX tS(H) tS(L) Setup time, High or Low Jn, Kn to CP Waveform 1 4.0 3.5 5.0 4.0 ns th(H) th(L) Hold time, High or Low Jn, Kn to CP Waveform 1 0.0 0.0 0.0 0.0 ns tW(H) tW(L) CP Pulse width High or Low Waveform 1 4.5 4.5 5.0 5.0 ns tW(L) SDn, RD Pulse width Low Waveform 2,3 4.5 5.0 ns tREC Recovery time SDn, RD to CP Waveform 2,3 4.5 5.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. Kn Jn, Kn VM ts(L) Jn Jn VM VM ts(H) th(L) Kn VM th(H) fmax CP VM tw(L) VM tw(H) tPHL Qn tPLH VM VM tPHL tPLH Qn VM VM VM SF00114 Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width 1996 Mar 14 4 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 Jn, Kn SDn VM tw(L) VM tREC CP VM tPLH Qn VM tPHL VM Qn SF00115 Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock Jn, Kn RD VM tw(L) VM tREC CP VM tPHL Qn VM tPLH Qn VM SF00116 Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock 1996 Mar 14 5 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop with common clock and reset 74F114 TEST CIRCUIT AND WAVEFORMS VCC VIN tw 90% NEGATIVE PULSE 10% D.U.T. RT CL RL AMP (V) VM VM VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% POSITIVE PULSE VM VM 10% Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1996 Mar 14 6