INTEGRATED CIRCUITS DATA SHEET 74AHC86; 74AHCT86 Quad 2-input EXCLUSIVE-OR gate Product specification File under Integrated Circuits, IC06 1999 Sep 17 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL • For AHC only: operates with CMOS input levels • Specified from −40 to +85 °C and −40 to +125 °C. PARAMETER CONDITIONS UNIT AHC • Inputs accepts voltages higher than VCC • For AHCT only: operates with TTL input levels 74AHC86; 74AHCT86 AHCT tPHL/tPLH propagation delay nA, nB to nY CL = 15 pF; VCC = 5 V 3.4 3.4 ns CI input capacitance VI = VCC or GND 3.0 3.0 pF CO output capacitance VI = VCC or GND 4.0 4.0 pF CPD power dissipation capacitance 10 12 pF CL = 50 pF; f = 1 MHz; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; DESCRIPTION fo = output frequency in MHz; The 74AHC/AHCT86 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. ∑ (CL × VCC2 × fo) = sum of outputs; The 74AHC/AHCT86 provides the 2-input EXCLUSIVE-OR function. CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. FUNCTION TABLE See note 1. INPUT OUTPUT nA nB nY L L L L H H H L H H H L Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION OUTSIDE NORTH AMERICA PACKAGES NORTH AMERICA PINS PACKAGE MATERIAL CODE 74AHC86D 74AHC86D 14 SO plastic SOT108-1 74AHC86PW 74AHC86PW DH 14 TSSOP plastic SOT402-1 74AHCT86D 74AHCT86D 14 SO plastic SOT108-1 74AHCT86PW 74AHCT86PW DH 14 TSSOP plastic SOT402-1 1999 Sep 17 2 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 PINNING PIN SYMBOL DESCRIPTION 1, 4, 9 and 12 1A to 4A data inputs 2, 5, 10 and 13 1B to 4B data inputs 3, 6, 8 and 11 1Y to 4Y data outputs 7 GND ground (0 V) 14 VCC DC supply voltage handbook, halfpage handbook, halfpage 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 2B 5 10 3B 2Y 6 9 GND 7 8 3Y 86 11 4Y 3A 1 2 1A 1B 1Y 3 4 5 2A 2B 2Y 6 9 10 3A 3B 3Y 8 12 13 4A 4B 4Y 11 MNA455 MNA456 Fig.1 Pin configuration. handbook, halfpage 1 =1 3 =1 6 Fig.2 Logic symbol. 2 4 handbook, halfpage 5 9 A Y =1 8 10 12 B =1 MNA458 11 13 MNA457 Fig.3 IEC logic symbol. 1999 Sep 17 Fig.4 Logic diagram (one gate). 3 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. VCC DC supply voltage 2.0 5.0 5.5 MIN. TYP. 4.5 5.0 MAX. 5.5 V VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature −40 +25 +85 −40 +25 +85 °C −40 +25 +125 −40 +25 +125 °C ns/V see DC and AC characteristics per device tr,tf (∆t/∆f) input rise and fall VCC = 3.3 ±0.3 V times except for VCC = 5 ±0.5 V Schmitt trigger inputs − − 100 − − − − − 20 − − 20 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK DC input diode current − −20 mA VI < −0.5 V; note 1 IOK DC output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA IO DC output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC DC VCC or GND current − ±75 mA Tstg storage temperature −65 +150 °C PD power dissipation per package − 500 mW for temperature range: −40 to +125 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO package: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP package: above 60 °C the value of PD derates linearly with 5.5 mW/K. 1999 Sep 17 4 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 DC CHARACTERISTICS Family 74AHC Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH VIL VOH VOL −40 to +85 25 PARAMETER HIGH-level input voltage LOW-level input voltage VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 1.5 − − 1.5 − 1.5 − 3.0 2.1 − − 2.1 − 2.1 − 5.5 3.85 − − 3.85 − 3.85 − 2.0 − − 0.5 − 0.5 − 0.5 3.0 − − 0.9 − 0.9 − 0.9 5.5 − − 1.65 − 1.65 − 1.65 2.0 1.9 2.0 − 1.9 − 1.9 − 3.0 2.9 3.0 − 2.9 − 2.9 − 4.5 4.4 4.5 − 4.4 − 4.4 − V V HIGH-level output voltage; all outputs VI = VIH or VIL; IO = −50 µA V HIGH-level output voltage VI = VIH or VIL; IO = −4.0 mA 3.0 2.58 − − 2.48 − 2.40 − VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 3.0 − 0 0.1 − 0.1 − 0.1 4.5 − 0 0.1 − 0.1 − 0.1 LOW-level output voltage VI = VIH or VIL; IO = 4.0 mA 3.0 − − 0.36 − 0.44 − 0.55 VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 − 1.0 − 2.0 ±2.5 − ±10.0 µA V V V II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 2.0 − 20 − 40 µA CI input capacitance − − 3 10 − 10 − 10 pF 1999 Sep 17 5 µA Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 Family 74AHCT Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output VI = VIH or VIL; voltage; all outputs IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V HIGH-level output voltage VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V LOW-level output VI = VIH or VIL; voltage; all outputs IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V LOW-level output voltage VI = VIH or VIL; IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V II input leakage current VI = VIH or VIL 5.5 − − 0.1 − 1.0 − 2.0 µA IOZ 3-state output OFF VI = VIH or VIL; 5.5 current VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 − ±2.5 − ±10.0 µA ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 2.0 − 20 − 40 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF VOL 1999 Sep 17 − 6 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 AC CHARACTERISTICS Type 74AHC86 Voltage are referenced to GND (ground = 0 V); tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 WAVEFORMS CL MIN. −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 15 pF − 4.8 11.0 1.0 13.0 1.0 14.0 ns 50 pF − 6.8 14.5 1.0 16.5 1.0 18.5 ns 15 pF − 3.4 6.8 1.0 8.0 1.0 8.5 ns 50 pF − 4.8 8.8 1.0 10.0 1.0 11.0 ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. Type 74AHCT86 Ground = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 WAVEFORMS CL MIN. −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. 15 pF − 3.4 6.9 1.0 8.0 1.0 9.0 ns 50 pF − 4.9 8.8 1.0 10.0 1.0 11.0 ns VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 Note 1. Typical values at VCC = 5.0 V. 1999 Sep 17 7 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 AC WAVEFORMS VI handbook, halfpage VM nA, nB input GND tPHL tPLH VM nY output MNA244 VI INPUT REQUIREMENTS FAMILY VM INPUT VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.5 The input (nA, nB) to output (nY) propagation delays. S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO VCC open GND D.U.T. CL RT MNA245 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit: CL = load capacitance including jig and probe capacitance (see “AC characteristics” for values). RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 1999 Sep 17 8 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.244 0.039 0.050 0.041 0.228 0.016 0.010 0.057 inches 0.069 0.004 0.049 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06S MS-012AB 1999 Sep 17 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 9 o 8 0o Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 1999 Sep 17 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 MO-153 10 o Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Sep 17 11 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable(2) suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Sep 17 12 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 NOTES 1999 Sep 17 13 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 NOTES 1999 Sep 17 14 Philips Semiconductors Product specification Quad 2-input EXCLUSIVE-OR gate 74AHC86; 74AHCT86 NOTES 1999 Sep 17 15 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245002/01/pp16 Date of release: 1999 Sep 17 Document order number: 9397 750 06109