PHILIPS 74AHC1GU04

INTEGRATED CIRCUITS
DATA SHEET
74AHC1GU04
Inverter
Product specification
File under Integrated Circuits, IC06
1999 May 19
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
FEATURES
• Symmetrical output impedance
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
• High noise immunity
SYMBOL
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V;
MM EIA/JESD22-A115-A
exceeds 200 V
tPHL/tPLH
propagation delay
inA to outY
CI
input capacitance
CPD
power dissipation
capacitance
• Low power dissipation
• Balanced propagation delays
• Very small 5-pin package
PARAMETER
CONDITIONS
TYPICAL UNIT
CL = 15 pF; VCC = 5 V 2.6
notes 1 and 2
ns
3
pF
14
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
• Output capability: standard.
fi = input frequency in MHz;
fo = output frequency in MHz;
DESCRIPTION
CL = output load capacitance in pF;
The 74AHC1GU04 is a high-speed
Si-gate CMOS device.
The 74AHC1GU04 provides the
inverting single stage function.
VCC = supply voltage in V;
2. The condition is VI = GND to VCC.
PINNING
FUNCTION TABLE
See note 1.
PIN
SYMBOL
DESCRIPTION
1
n.c.
not connected
INPUT
OUTPUT
2
inA
data input
inA
outY
3
GND
ground (0 V)
L
H
4
outY
data output
L
5
VCC
DC supply voltage
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
PACKAGES
TYPE NUMBER
74AHC1GU04GW
1999 May 19
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
−40 to +85 °C
5
SC-88A
plastic
SOT353
2
MARKING
AD
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
handbook, halfpage
n.c. 1
inA 2
GND
5 VCC
handbook, halfpage
2
U04
3
4
inA
outY
outY
MNA043
MNA042
Fig.1 Pin configuration.
handbook, halfpage
2
1
Fig.2 Logic symbol.
4
handbook, halfpage
MNA044
outY
MNA045
Fig.3 IEC logic symbol.
1999 May 19
inA
Fig.4 Logic diagram.
3
4
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
RECOMMENDED OPERATING CONDITIONS
74AHC1G
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN.
TYP.
MAX.
VCC
DC supply voltage
2.0
5.0
5.5
V
VI
input voltage
0
−
5.5
V
0
−
VCC
V
−40
+25
+85
°C
−
−
100
ns/V
−
−
20
VO
output voltage
Tamb
operating ambient
temperature range
tr, tf (∆t/∆f)
input rise and fall times except VCC = 3.3 V ±0.3 V
for Schmitt-trigger inputs
VCC = 5 V ±0.5 V
see DC and AC
characteristics per device
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
DC supply voltage
−0.5
+7.0
V
VI
input voltage range
−0.5
+7.0
V
IIK
DC input diode current
VI < −0.5
−
−20
mA
IOK
DC output diode current
VO < −0.5 or VO > VCC + 0.5 V; note 1
−
±20
mA
IO
DC output source or sink current −0.5 V < VO < VCC + 0.5 V
−
±25
mA
ICC
DC VCC or GND current
−
±75
mA
Tstg
storage temperature
−65
+150
°C
PD
power dissipation per package
200
mW
temperature range: −40 to +85 °C; note 2 −
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of PD derates linearly with 2.5 mW/K.
1999 May 19
4
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
DC CHARACTERISTICS
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
Tamb (°C)
TEST CONDITIONS
SYMBOL
OTHER
VIH
VIL
VOH
HIGH-level input
voltage
HIGH-level output
voltage
VOL
LOW-level output
voltage; all outputs
LOW-level output
voltage
VCC (V)
MIN.
TYP.
MAX.
MIN.
2.0
1.7
−
−
1.7
−
3.0
2.4
−
−
2.4
−
5.5
4.4
−
−
4.4
−
2.0
−
−
0.3
−
0.3
−
−
0.6
−
0.6
5.5
−
−
1.1
−
1.1
2.0
1.9
2.0
−
1.9
−
3.0
2.9
3.0
−
2.9
−
4.5
4.4
4.5
−
4.4
−
VI = VIH or VIL;
IO = −4.0 mA
3.0
2.58
−
−
2.48
−
VI = VIH or VIL;
IO = −8.0 mA
4.5
3.94
−
−
3.8
−
VI = VIH or VIL;
IO = 50 µA
2.0
−
0
0.1
−
0.1
3.0
−
0
0.1
−
0.1
4.5
−
0
0.1
−
0.1
VI = VIH or VIL;
IO = 4 mA
3.0
−
−
0.36
−
0.44
VI = VIH or VIL;
IO = 8 mA
4.5
−
−
0.36
−
0.44
VI = VIH or VIL;
IO = −50 µA
UNIT
MAX.
3.0
LOW-level input voltage
HIGH-level output
voltage; all outputs
−40 to +85
+25
PARAMETER
V
V
V
V
V
V
II
input leakage current
VI = VCC or GND
5.5
−
−
0.1
−
1.0
µA
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
−
−
1.0
−
10
µA
CI
input capacitance
−
3
−
−
10
pF
1999 May 19
5
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
AC CHARACTERISTICS
Type 74AHC1GU04
GND = 0 V; tr = tf ≤ 3.0 ns.
Tamb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
WAVEFORMS
CL
VCC (V)
MIN.
+25
−40 to +85
TYP.
MAX. MIN. MAX.
UNIT
tPHL/tPLH
propagation delay
inA to outY
see Figs 5 and 6
15 pF
3.0 to 3.6
−
3.4(1)
7.1
1.0
8.5
ns
tPHL/tPLH
propagation delay
inA to outY
see Figs 5 and 6
50 pF
3.0 to 3.6
−
4.9(1)
10.6
1.0
12.0
ns
tPHL/tPLH
propagation delay
inA to outY
see Figs 5 and 6
15 pF
4.5 to 5.5
−
2.6(2)
5.5
1.0
6.0
ns
tPHL/tPLH
propagation delay
inA to outY
see Figs 5 and 6
50 pF
4.5 to 5.5
−
3.6(2)
7.0
1.0
8.0
ns
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
AC WAVEFORMS
handbook, halfpage
inA INPUT
VCC
handbook, halfpage
VM(1)
tPHL
PULSE
GENERATOR
tPLH
VI
VO
D.U.T.
RT
outY OUTPUT
VM(1)
CL
50 pF
MNA034
MNA046
Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance. (See
Chapter “AC characteristics” for values).
RT = Termination resistance should be equal to the output
impedance ZO of the pulse generator.
(1) VM = 50%; VI = GND to VCC.
Fig.5
The input (inA) to output (outY) propagation
delays.
1999 May 19
Fig.6 Load circuitry for switching times.
6
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
TYPICAL TRANSFER CHARACTERISTICS
MNA397
MNA398
handbook, halfpage
2.0
VO
handbook, halfpage
VO
(V)
1.6
1.0
ICC
3.0
(mA)
0.8
VO
1.2
0.6
0.8
0.4
10
VO
ICC
(mA)
(V)
8
6
1.5
0.4
4
ID (drain current)
0.2
ID (drain current)
0
0
0
0.4
0.8
1.2
1.6
2
0
2.0
0
0
VI (V)
1
Fig.7 VCC = 2.0 V; IO = 0.
2
3
VI (V)
Fig.8 VCC = 3.0 V; IO = 0.
MNA399
handbook, halfpage
6
50
VO
(V)
handbook, halfpage
ICC
(mA)
40
VO
Rbias = 560 kΩ
VCC
0.47 µF
30
input
output 100 µF
3
VI
(f = 1 kHz)
20
A IO
GND
ID (drain current)
MNA050
10
0
0
0
2
4
VI (V)
6
Fig.10 Test set-up for measuring forward
transconductance gfs = ∆IO/∆VI at VO is
constant.
Fig.9 VCC = 5.5 V; IO = 0.
1999 May 19
7
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
APPLICATION INFORMATION
Some applications for the HC1GU04 are:
• Linear amplifier (see Fig.12)
MNA400
40
• In crystal oscillator design (see Fig.13).
handbook, halfpage
gfs
Note to the application information.
(mA/V)
30
All values given are typical unless otherwise specified.
20
10
0
0
2
4
VCC (V)
6
Fig.11 Typical forward transconductance gfs as a
function of the supply voltage at
Tamb = 25 °C.
R2
handbook, halfpage
VCC
1 µF
R1
handbook, halfpage
U04
R1
ZL
R2
U04
GND
MNA052
C1
C2
out
MNA053
ZL > 10 kΩ; AOL = 20 (typical)
A OL
A u = – -----------------------------------------------;
R1
1 + -------- ( 1 + A OL )
R2
1
V 0 max (p-p) ≈ V CC – 1.5 V centered at --- V CC
2
R1 ≥ 3 kΩ, R2 ≤ 1 MΩ.
Typical unity gain bandwidth product is 5 MHz.
C1 = 47 pF (typical).
C2 = 22 pF (typical).
R1 = 1 to 10 MΩ (typical).
R2 optimum value depends on the frequency and required stability
against changes in VCC or average minimum ICC (ICC is typically
2 mA at VCC = 3 V and f = 1 MHz).
C1 see Fig.13.
AOL = open loop amplification.
Au = voltage amplification.
Fig.12 Used as a linear amplifier.
1999 May 19
Fig.13 Crystal oscillator configuration.
8
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
External components for resonator (f < 1 MHz)
FREQUENCY
(kHz)
R1 (MΩ) R2 (kΩ) C1 (pF)
Optimum value for R2
FREQUENCY
(kHz)
C2 (pF)
R2 (kΩ)
OPTIMUM FOR
10 to 15.9
22
220
56
20
16 to 24.9
22
220
56
10
25 to 54.9
22
100
56
10
55 to 129.9
22
100
47
5
130 to 199.9
22
47
47
5
4.7
minimum influence by VCC
0.5
minimum required ICC
2.0
minimum influence by VCC
0.5
minimum required ICC
1.0
minimum influence by VCC
200 to 349.9
22
47
47
5
350 to 600
22
47
47
5
3
6
10
14
Where:
All values given are typical and must be used as an initial
set-up.
1999 May 19
>14
9
2.0
minimum required ICC
8.0
minimum influence due to
change in VCC
1.0
minimum required ICC
replace R2 by C3 with a typical value
of 35 pF
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
PACKAGE OUTLINE
Plastic surface mounted package; 5 leads
SOT353
D
E
B
y
X
A
HE
5
v M A
4
Q
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E (2)
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
SOT353
1999 May 19
REFERENCES
IEC
JEDEC
EIAJ
SC-88A
10
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
If wave soldering is used the following conditions must be
observed for optimal results:
SOLDERING
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
1999 May 19
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
11
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, SMS
not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 May 19
12
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
NOTES
1999 May 19
13
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
NOTES
1999 May 19
14
Philips Semiconductors
Product specification
Inverter
74AHC1GU04
NOTES
1999 May 19
15
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209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA 64
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
245002/00/01/pp16
Date of release: 1999 May 19
Document order number:
9397 750 05742