PHILIPS TDA8787

INTEGRATED CIRCUITS
DATA SHEET
TDA8787
10-bit, 3.0 V analog-to-digital
interface for CCD cameras
Preliminary specification
Supersedes data of 1998 Mar 27
File under Integrated Circuits, IC02
1998 Oct 15
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
FEATURES
APPLICATIONS
• Correlated Double Sampling (CDS), Automatic Gain
Control (AGC), 10-bit Analog-to-Digital Converter (ADC)
and reference regulator included
• Low-power, low-voltage CCD camera systems.
GENERAL DESCRIPTION
• Fully programmable via a 3-wire serial interface
• Low power consumption of only 190 mW (typ.)
The TDA8787 is a 10-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
sampling circuit, AGC and a low-power 10-bit ADC
together with its reference voltage regulator.
• Power consumption in standby mode of 4.5 mW (typ.)
AGC gain is controlled via the serial interface.
• 3.0 V operation and 2.5 to 3.6 V operation for the digital
outputs
The ADC input clamp level is controlled via the serial
interface.
• Sampling frequency up to 18 MHz
• AGC gain range of 36 dB (in steps of 0.1 dB)
• Active control pulses polarity selectable via serial
interface
An additional DAC is provided for additional system
controls; its output voltage range is 1.0 V (p-p) which is
available at pin OFDOUT.
• 8-bit DAC included for analog settings
• TTL compatible inputs, CMOS compatible outputs.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
2.7
3.0
3.6
V
VCCD
digital supply voltage
2.7
3.0
3.6
V
VCCO
digital outputs supply voltage
ICCA
analog supply current
ICCD
digital supply current
ICCO
digital outputs supply current
ADCres
ADC resolution
Vi(CDS)(p-p)
maximum CDS input voltage
(peak-to-peak value)
fpix(max)
maximum pixel rate
fpix(min)
minimum pixel rate
DRAGC
AGC dynamic range
Ntot(rms)
total noise from CDS input to
ADC output
AGC gain = 0 dB; see Fig.8
Ptot
total power consumption
VCCA = VCCD = VCCO = 3 V
2.5
2.6
3.6
V
−
55
70
mA
−
8
11
mA
fpix = 18 MHz; CL = 20 pF;
−
input ramp response time is 800 µs
1
2
mA
−
10
−
bits
VCC = 2.85 V
650
−
−
mV
VCC ≥ 3.0 V
800
−
−
mV
18
−
−
MHz
5
−
−
MHz
−
36
−
dB
−
0.25
−
LSB
−
190
−
mW
all clamps active
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
TDA8787HL
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
1998 Oct 15
2
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48
1
DGND3
VCCA2
2
18
AGND2 CLPOB CLPDM
17
13
PBK
AGND5
12
11
43
CLK
40
OE
37
20
19
CDS CLOCK GENERATOR
39
38
26
CPCDS1
7
CLAMP
CPCDS2
VCCA3
AGND3
IN
36
8
35
COMPARATOR
42
34
41
CORRELATED
DOUBLE
SAMPLING
4
33
AGC
SHIFT
PREBLANKING
SHIFTER
DATA
FLIPFLOP
32
OUTPUT
BUFFER
31
30
10-bit ADC
29
3
CLAMP
28
27
VCCA1
AGND1
DAC
Vref
6
9-BIT
REGISTER
5
7-BIT
REGISTER
TDA8787
25
DGND1
VCCD1
DGND2
VCCD2
OGND
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Philips Semiconductors
47
VCCD3
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
SHD
BLOCK DIAGRAM
ook, full pagewidth
1998 Oct 15
SHP
VCCO
OFD DAC
OFDOUT
9
SERIAL
INTERFACE
8-BIT
REGISTER
14
15
16
3
45
46
OAGC
OAGCC
23
22
21
REGULATOR
24
44
DCLPC
10
MGM541
TEST1 TEST2
TEST3
AGND4
SEN
STDBY
Preliminary specification
TDA8787
Fig.1 Block diagram.
SCLK SDATA VSYNC
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
PINNING
SYMBOL
PIN
DESCRIPTION
VCCD3
1
digital supply voltage 3
DGND3
2
digital ground 3
AGND4
3
analog ground 4
IN
4
input signal from CCD
AGND1
5
analog ground 1
VCCA1
6
analog supply voltage 1
CPCDS1
7
clamp storage capacitor pin 1
CPCDS2
8
clamp storage capacitor pin 2
OFDOUT
9
analog output of the additional 8-bit control DAC
STDBY
10
standby mode control input (LOW: TDA8787 active; HIGH: TDA8787 standby)
PBK
11
pre-blanking control input
CLPDM
12
clamp pulse input at dummy pixel
CLPOB
13
clamp pulse input at optical black
TEST1
14
test pin input 1 (should be connected to AGND2)
TEST2
15
test pin input 2 (should be connected to AGND1)
TEST3
16
test pin input 3 (should be connected to AGND2)
AGND2
17
analog ground 2
VCCA2
18
analog supply voltage 2
VCCD1
19
digital supply voltage 1
DGND1
20
digital ground 1
SDATA
21
serial data input for serial interface control
SCLK
22
serial clock input for serial interface
SEN
23
strobe pin for serial interface
VSYNC
24
vertical sync pulse input
VCCO
25
output supply voltage
OGND
26
digital output ground
D0
27
ADC digital output 0 (LSB)
D1
28
ADC digital output 1
D2
29
ADC digital output 2
D3
30
ADC digital output 3
D4
31
ADC digital output 4
D5
32
ADC digital output 5
D6
33
ADC digital output 6
D7
34
ADC digital output 7
D8
35
ADC digital output 8
D9
36
ADC digital output 9 (MSB)
OE
37
output enable control input (LOW: outputs active; HIGH: outputs in high impedance)
VCCD2
38
digital supply 2
DGND2
39
digital ground 2
CLK
40
data clock input
1998 Oct 15
4
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
41
analog ground 3
AGC output (test pin)
46
AGC complementary output (test pin)
SHP
47
preset sample-and-hold pulse input
SHD
48
data sample-and-hold pulse input
40 CLK
45
OAGCC
41 AGND3
OAGC
42 VCCA3
regulator decoupling pin
43 AGND5
44
44 DCLPC
DCLPC
45 OAGC
analog ground 5
46 OAGCC
analog supply 3
43
47 SHP
42
48 SHD
VCCA3
AGND5
VCCD3
1
36 D9
DGND3
2
35 D8
AGND4
3
34 D7
IN
4
33 D6
AGND1
5
32 D5
VCCA1
6
CPCDS1
7
30 D3
CPCDS2
8
29 D2
OFDOUT
9
28 D1
STDBY 10
27 D0
31 D4
TDA8787
5
VSYNC 24
SEN 23
SDATA 21
DGND1 20
VCCD1 19
VCCA2 18
AGND2 17
TEST3 16
25 VCCO
TEST2 15
CLPDM 12
TEST1 14
26 OGND
CLPOB 13
PBK 11
Fig.2 Pin configuration.
1998 Oct 15
37 OE
AGND3
38 VCCD2
DESCRIPTION
39 DGND2
PIN
SCLK 22
SYMBOL
TDA8787
MGM542
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCCA
analog supply voltage
note 1
−0.3
+7.0
V
VCCD
digital supply voltage
note 1
−0.3
+7.0
V
VCCO
output stages supply voltage
note 1
−0.3
+7.0
V
∆VCC
supply voltage difference
between VCCA and VCCD
−1.0
+1.0
V
between VCCA and VCCO
−1.0
+1.0
V
between VCCD and VCCO
−1.0
+1.0
V
Vi
input voltage
−0.3
+7.0
V
Io
data output current
−
±10
mA
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
−20
+75
°C
Tj
junction temperature
−
150
°C
referenced to AGND
Note
1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply
voltage difference ∆VCC remains as indicated.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1998 Oct 15
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
in free air
6
VALUE
UNIT
76
K/W
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
CHARACTERISTICS
VCCA = VCCD = 3.0 V; VCCO = 2.6 V; fpix = 18 MHz; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VCCA
analog supply voltage
2.7
3.0
3.6
V
VCCD
digital supply voltage
2.7
3.0
3.6
V
VCCO
digital outputs supply
voltage
2.5
2.6
3.6
V
−
55
70
mA
−
8
11
mA
−
1
2
mA
ICCA
analog supply current
ICCD
digital supply current
ICCO
digital outputs supply
current
all clamps active
CL = 20 pF on all data
outputs; input ramp
frequency
Digital inputs
INPUTS: SHP, SHD, STDBY, CLPDM, CLPOB, SCLK, SDATA, SEN, VSYNC, OE AND PBK
VIL
LOW-level input voltage
0
−
0.6
V
VIH
HIGH-level input voltage
2.2
−
VCCD
V
Ii
input current
−2
−
+2
µA
18
−
−
pixels
1.5
2.7
3.5
mS
−
0.27
−
−
AGC code = 0
−
±350
−
µA
AGC code = 383
−
±10
−
µA
0 ≤ Vi ≤ VCCD
Clamps
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp)
clamp active pulse width
in number of pixels
AGC code = 383 for
maximum 4 LSB error
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS)
CDS input clamp
transconductance
OPTICAL BLACK CLAMP (DRIVEN BY CLPOB)
Gshift
gain from CPCDS1 and 2
to AGC inputs
ILSB(cp)
charge pump current for
±1 LSB error at ADC
output
Ipush(cp)
available push current of
the charge pump
−
650
−
µA
Ipull(cp)
available pull current of
the charge pump
−
−650
−
µA
1998 Oct 15
7
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
SYMBOL
PARAMETER
TDA8787
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
maximum peak-to-peak
CDS input amplitude
(video signal)
VCC = 2.85 V
650
−
−
mV
VCC ≥ 3.0 V
800
−
−
mV
500
−
−
mV
Vreset(max)
maximum CDS input reset
pulse amplitude
Ii(IN)
input current into pin IN
(pin 4)
at floating gate level
−1
−
+1
µA
tCDS(min)
CDS control pulses
minimum active time
video input = Vi(CDS)(p-p);
2 LSB error at ADC output
11
15
−
ns
th(IN-SHP)
CDS input hold time
(pin IN) compared to
control pulse SHP
VCCA = VCCD = 30 V;
Tamb = 25 °C; see Fig.9
3
5
7
ns
th(IN-SHD)
CDS input hold time
(pin IN) compared to
control pulse SHD
VCCA = VCCD = 30 V;
Tamb = 25 °C; see Fig.9
3
5
7
ns
Amplifier
DRAGC
AGC dynamic range
−
36
−
dB
∆GAGC
maximum AGC gain step
−0.3
−
+0.3
dB
Analog-to-Digital Converter (ADC)
LEi
integral linearity error
fpix = 18 MHz; ramp input
−
±1.3
±2.5
LSB
LEd
differential linearity error
fpix = 18 MHz; ramp input
−
±0.5
±0.9
LSB
Total chain characteristics (CDS + AGC + ADC)
fpix(max)
maximum pixel frequency
18
−
−
MHz
tCLKH
CLK pulse width HIGH
15
−
−
ns
tCLKL
CLK pulse width LOW
15
−
−
ns
td(SHD-CLK)
time delay between
SHD and CLK
10
−
−
ns
tsu(PBK-CLK)
set-up time of PBK
compared to CLK
10
−
−
ns
Vi(IN)
video input dynamic signal AGC code = 00
for ADC full-scale output
AGC code = 383
800
−
−
mV
12.7
−
−
mV
AGC gain = 0 dB
−
0.25
−
LSB
AGC gain = 9 dB
−
0.8
−
LSB
Ntot(rms)
total output noise (RMS
value)
see Fig.9
see Fig.8
OCCD(max)
maximum offset between
CCD floating level and
CCD dark pixel level
−70
−
+70
mV
Vn(i)(eq)(rms)
equivalent input noise
voltage (RMS value)
−
110
−
µV
1998 Oct 15
8
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
SYMBOL
PARAMETER
TDA8787
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Digital-to-analog converter (OFDOUT DAC)
VOFDOUT(p-p)
additional 8-bit control
Ri = 1 MΩ
DAC (OFD) output voltage
(peak-to-peak value)
−
1.0
−
V
VOFDOUT(0)
DC output voltage for
code 0
−
AGND
−
V
VOFDOUT(255) DC output voltage for
code 255
−
AGND + 1.0 −
V
TCDAC
DAC output range
temperature coefficient
−
250
−
ppm/°C
ZOFDOUT
DAC output impedance
−
2000
−
Ω
IOFDOUT
OFD output current drive
−
−
100
µA
VCCO
V
static
Digital outputs (fpix = 18 MHz; CL = 22 pF)
VOH
HIGH-level output voltage
IOH = −1 mA
VCCO − 0.5 −
VOL
LOW-level output voltage
IOL = 1 mA
0
−
0.5
V
IOZ
output current in 3-state
mode
0.5 V < Vo < VCCO
−20
−
+20
µA
th(o)
output hold time
see Fig.9
11
−
−
ns
td(o)
output delay time
CL = 22 pF; VCCO = 3.0 V
−
28
tbf
ns
CL
output load capacitance
CL = 22 pF; VCCO = 2.7 V
−
27
tbf
ns
−
−
22
pF
5
−
−
MHz
Serial interface
fSCLK(max)
1998 Oct 15
maximum frequency of
serial interface
9
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
handbook, full pagewidth
IN
N+1
N
N+2
N+3
t CDS(min)
2.2 V
SHP
0.6 V
t h(IN-SHP)
t CDS(min)
2.2 V
SHD
0.6 V
0.6 V
t h(IN-SHD)
tCLKH
2.2 V
CLK
0.6 V
0.6 V
t d(SHD-CLK)
50%
SDATA
N−1
N
th(o)
td(o)
2.2 V
PBK
0.6 V
MGM764
t su(PBK-CLK)
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
1998 Oct 15
10
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
handbook, full pagewidth
IN
N+1
N
N+2
N+3
2.2 V
SHP
0.6 V
t CDS(min)
t h(IN-SHP)
2.2 V
2.2 V
SHD
0.6 V
t CDS(min)
t h(IN-SHD)
2.2 V
2.2 V
CLK
0.6 V
tCLKL
t d(SHD-CLK)
N−1
50%
SDATA
N
th(o)
td(o)
2.2 V
PBK
0.6 V
FCE088
t su(PBK-CLK)
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
MGM543
handbook, full pagewidth
1.0
OFDOUT DAC
voltage
output
(V)
0
255
0
OFDOUT control DAC input code
Fig.5 DAC voltage output as a function of DAC input code.
1998 Oct 15
11
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
4 pixels(1)
handbook, full pagewidth
4 pixels(1)
CLPOB
WINDOW
AGCOUT
VIDEO
CLPDM
WINDOW
OPTICAL BLACK
HORIZONTAL FLYBACK
DUMMY
VIDEO
CLPOB
(active HIGH)
(2)
CLPDM
(active HIGH)
PBK
(active HIGH)
PBK window
MGM544
(1) In case the number of clamp pixels is limited to 18tW(clamp); otherwise this timing interval can be smaller.
(2) When dummy pixels are not available.
Fig.6 Line frequency timing diagram.
FCE057
42
handbook, halfpage
AGC
gain 36
(dB)
30
24
18
12
6
0
−6
0
64
128
192
256
320
384
AGC input code
Fig.7 AGC gain as a function of AGC input code.
1998 Oct 15
12
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
FCE098
10
handbook, halfpage
Ntot(rms)
(LSB)
8
6
4
2
0
0
64
128
192
256
320
383
AGC code
Noise measurement at ADC outputs:
Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 18 Mpixels with line of 1024 pixels
whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this,
the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into account as no signal is inputted.
Fig.8 Total noise performance as a function of AGC gain.
1998 Oct 15
13
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
handbook, full pagewidth
SDATA
TDA8787
SHIFT REGISTER
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
A0
A1
SCLK
LSB
MSB
10
LATCH
SELECTION
SEN
8
9
7
6
OFDOUT DAC
LATCHES
AGC GAIN
LATCHES
ADC CLAMP
LATCHES
CONTROL PULSE
POLARITY
LATCHES
8-bit DAC
AGC control
ADC clamp
control
control pulses
polarity settings
MGM546
Fig.9 Serial interface block diagram.
tsu2
handbook, full pagewidth
thd4
MSB
SDATA
A1
A0
D9
D8
D7
D6
LSB
D5
D4
D3
D2
D1
D0
SCLK
SEN
tsu1
tsu3
thd3
tsu1 = tsu2 = tsu3 = 10 ns (min.); thd3 = thd4 = 10 ns (min.).
Fig.10 Loading sequence of control input data via the serial interface.
1998 Oct 15
14
MGM547
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
Table 1
TDA8787
Serial interface programming
ADDRESS BITS
DATA BITS D9 TO D0
A1
A0
0
0
AGC gain control (D8 to D0); bit D9 should be set to logic 0
0
1
DAC OFDOUT output control (D7 to D0); bits D8 and D9 should be set to logic 0
1
0
ADC clamp reference control (D6 to D0); bits D7, D8 and D9 should be set to logic 0
1
1
control pulses (pins SHP, SHD, CLPDM, CLPOB, PBK and CLK) polarity settings
Table 2
Polarity settings
PIN
SERIAL CONTROL BIT(1)
ACTIVE EDGE OR LEVEL
47 and 48
D0
1 = HIGH; 0 = LOW
CLK
40
D1
1 = rising; 0 = falling
CLPDM
12
D2
1 = HIGH; 0 = LOW
CLPOB
13
D3
1 = HIGH; 0 = LOW
PBK
11
D5
1 = HIGH; 0 = LOW
VSYNC
24
D6
0 = rising; 1 = falling
SYMBOL
SHP and SHD
Note
1. Bit D4 is not used.
Table 3
Standby selection
STDBY
1998 Oct 15
ADC DIGITAL OUTPUTS D9 TO D0
ICCA + ICCO + ICCD (TYP.)
1
logic state LOW
1 mA
0
active
64 mA
15
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
APPLICATION DIAGRAM
VCCD
VCCA
handbook, full pagewidth
1 µF
100
nF
VCCD
OE
DGND2
VCCD2
AGND3
CLK
VCCA3
AGND5
DCLPC
OAGC
SHD
SHP
CCD(2)
1 µF
100
nF
(2)
OAGCC
(2)
48 47 46 45 44 43 42 41 40 39 38 37
VCCD
VCCD3
1 µF
DGND3
AGND4
IN
VCCA
100
nF
AGND1
VCCA1
CPCDS1
1 µF
CPCDS2
OFDOUT
STDBY
1 µF
PBK
CLPDM
1
36
2
35
3
34
4
33
5
32
6
31
TDA8787HL
7
30
8
29
9
28
10
27
11
26
12
25
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
VCCO
100
nF
SEN
VSYNC
SCLK
SDATA
DGND1
VCCD1
VCCA2
AGND2
TEST3
TEST2
TEST1
VCCD
CLPOB
13 14 15 16 17 18 19 20 21 22 23 24
VCCD
(1)
serial
interface
100
nF
100
nF
VCCA
VCCD
MGM548
(1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN-SHP) and th(IN-SHD) (see Chapter “Characteristics”).
Fig.11 Application diagram.
1998 Oct 15
16
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
94-12-19
97-08-01
SOT313-2
1998 Oct 15
EUROPEAN
PROJECTION
17
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
SOLDERING
Introduction
•A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
•The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
CAUTION
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
1998 Oct 15
TDA8787
18
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V analog-to-digital interface for
CCD cameras
TDA8787
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Oct 15
19
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/750/02/pp20
Date of release: 1998 Oct 15
Document order number:
9397 750 04259