Philips Semiconductors Product specification PowerMOS transistor GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a full pack plastic envelope featuring high avalanche energy capability, stable off-state characteristics, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. PINNING - SOT186A PIN PHX1N40 QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance PIN CONFIGURATION MAX. UNIT 400 1.7 25 3.5 V A W Ω SYMBOL DESCRIPTION d case 1 gate 2 drain 3 source g case isolated 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS ID Continuous drain current IDM PD ∆PD/∆Tmb VGS EAS Pulsed drain current Total dissipation Linear derating factor Gate-source voltage Single pulse avalanche energy Peak avalanche current Ths = 25 ˚C; VGS = 10 V Ths = 100 ˚C; VGS = 10 V Ths = 25 ˚C Ths = 25 ˚C Ths > 25 ˚C IAS Tj, Tstg Operating junction and storage temperature range VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 10 V VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 10 V MIN. MAX. UNIT - 1.7 1.1 7 25 0.2 ± 30 100 A A A W W/K V mJ - 2.5 A - 55 150 ˚C ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Visol R.M.S. isolation voltage from all three terminals to external heatsink f = 50-60 Hz; sinusoidal waveform; R.H. ≤ 65% ; clean and dustfree Cisol Capacitance from T2 to external f = 1 MHz heatsink June 1997 1 MIN. TYP. - - 10 MAX. UNIT 2500 V - pF Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHX1N40 THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-hs Thermal resistance junction to heatsink Thermal resistance junction to ambient with heatsink compound Rth j-a MIN. TYP. MAX. UNIT - - 5 K/W - 55 - K/W ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS VGS = 0 V; ID = 0.25 mA 400 - - V ∆V(BR)DSS / ∆Tj RDS(ON) VGS(TO) gfs IDSS Drain-source breakdown voltage Drain-source breakdown voltage temperature coefficient Drain-source on resistance Gate threshold voltage Forward transconductance Drain-source leakage current VDS = VGS; ID = 0.25 mA - 0.45 - V/K VGS = 10 V; ID = 1.25 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 1.25 A VDS = 400 V; VGS = 0 V VDS = 320 V; VGS = 0 V; Tj = 125 ˚C VGS = ±30 V; VDS = 0 V 2.0 0.5 - 2.0 3.0 1.5 1 30 10 3.5 4.0 25 250 200 Ω V S µA µA nA IGSS Gate-source leakage current Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 2.5 A; VDD = 320 V; VGS = 10 V - 20 2 8 25 3 12 nC nC nC td(on) tr td(off) tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 200 V; ID = 2.5 A; RG = 24 Ω; RD = 78 Ω - 10 25 46 25 - ns ns ns ns Ld Internal drain inductance - 4.5 - nH Ls Internal source inductance Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 240 44 26 - pF pF pF MIN. TYP. MAX. UNIT SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IS Ths = 25˚C - - 2.5 A Ths = 25˚C - - 10 A VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage IS = 2.5 A; VGS = 0 V - - 1.2 V trr Reverse recovery time IS = 2.5 A; VGS = 0 V; dI/dt = 100 A/µs - 200 - ns Qrr Reverse recovery charge - 2.0 - µC ISM June 1997 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Normalised Power Derating PD% 120 PHX1N40 1E+01 with heatsink compound 110 Zth j-hs / (K/W) 100 90 ZTHX43 0.5 80 70 1E+00 60 50 0.2 0.1 0.05 1E-01 0.02 40 PD 30 tp D= tp T 20 0 10 0 20 40 60 80 Ths / C 100 120 140 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Ths) 8 with heatsink compound 110 1E-05 1E-03 t/s 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-hs = f(t); parameter D = tp/T Normalised Current Derating ID% 120 t T 1E-02 1E-07 0 ID, Drain current (Amps) PHP2N40 Tj = 25 C 100 90 7 20 V 6 10 V 7V 80 70 5 60 4 50 6.5 V 6V 3 40 30 5.5 V 2 5V 20 1 10 0 0 20 40 60 80 Ths / C 100 120 0 140 VGS = 4.5 V 0 5 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 10 V 10 Drain current, ID (Amps) /ID DS =V ) N S(O RD 10 15 20 25 VDS, Drain-Source voltage (Volts) 30 Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS PHX1N40 6 tp = 10 us Drain-Source on resistance, RDS(ON) (Ohms) 5V 5.5 V 6V 6.5 V PHP2N40 Tj = 25 C 5 100us 7V 1 4 10 V 1ms DC 3 10ms 100ms 0.1 VGS = 20 V 2 1 0.01 10 100 Drain-source voltage, VDS (Volts) 0 1000 Fig.3. Safe operating area. Ths = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp June 1997 0 1 2 3 4 5 Drain current, ID (Amps) 6 7 8 Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 8 PHX1N40 VGS(TO) / V PHP2N40 Drain current, ID (A) VDD = 30 V max. 4 7 Tj = 25 C 6 typ. 3 5 150 C min. 4 2 3 2 1 1 0 0 0 2 4 6 Gate-source voltage, VGS (V) 8 -60 10 Transconductance, gfs (S) -20 0 20 40 60 Tj / C 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj 2.5 -40 PHP2N40 1E-01 SUB-THRESHOLD CONDUCTION ID / A VDD = 30 V 1E-02 2 Tj = 25 C 2% 1E-03 1.5 typ 98 % 150 C 1 1E-04 0.5 1E-05 0 1E-06 0 1 2 3 4 5 Drain current, ID (A) 6 7 0 8 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj 2 VGS / V 3 4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) a 1 1000 PHP2N40 Capacitances, Ciss, Coss, Crss (pF) 2 Ciss 100 Coss 1 10 0 -60 -40 -20 0 20 40 60 Tj / C 80 1 100 120 140 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 1.25 A; VGS = 10 V June 1997 Crss 1 10 100 Drain-source voltage, VDS (V) 1000 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 20 PHX1N40 Gate-Source voltage, VGS (Volts) ID = 2.5 A PHP2N40 10 100 V 15 PHP2N40 Source-drain diode current, IF(A) VGS = 0 V 200 V 8 VDD = 320 V 150 C Tj = 25 C 6 10 4 5 2 0 0 10 20 Gate charge, Qg (nC) 30 0 40 Switching times, td(on), tr, td(off), tf (ns) 0.5 1 Source-Drain voltage, VSDS (V) 1.5 Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS 1000 0 PHP2N40 120 VDD = 200V RD = 78 Ohms Tj = 25 C EAS, Normalised unclamped inductive energy (%) 110 100 90 100 80 70 td(off) 60 tr tf 50 td(on) 30 10 40 20 10 1 0 20 40 60 Gate resistance, RG (Ohms) 80 0 100 20 Fig.14. Typical switching times. td(on), tr, td(off), tf = f(RG) 1.15 40 60 80 100 Starting Tj ( C) 120 140 Fig.17. Normalised unclamped inductive energy. EAS% = f(Tj) Normalised Drain-source breakdown voltage V(BR)DSS @ Tj + V(BR)DSS @ 25 C 1.1 VDD L 1.05 VDS - VGS 1 -ID/100 0 0.95 0.9 0.85 -100 RGS -50 0 50 Tj, Junction temperature (C) 100 R 01 shunt 150 Fig.18. Unclamped inductive test circuit. EAS = 0.5 ⋅ LID2 ⋅ V(BR)DSS /(V(BR)DSS − VDD ) Fig.15. Normalised drain-source breakdown voltage. V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj) June 1997 T.U.T. 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHX1N40 MECHANICAL DATA Dimensions in mm Net Mass: 2 g 10.3 max 4.6 max 3.2 3.0 2.9 max 2.8 Recesses (2x) 2.5 0.8 max. depth 6.4 15.8 19 max. max. 15.8 max seating plane 3 max. not tinned 3 2.5 13.5 min. 1 0.4 2 3 M 1.0 (2x) 0.6 2.54 0.9 0.7 0.5 2.5 5.08 1.3 Fig.19. SOT186A; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". June 1997 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHX1N40 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1997 7 Rev 1.000