Philips Semiconductors Product specification PowerMOS transistor GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope featuring high avalanche energy capability, stable off-state characteristics, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. PINNING - SOT429 (TO247) PIN QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance PIN CONFIGURATION gate 2 drain 3 source MAX. UNIT 600 7 147 1.2 V A W Ω SYMBOL DESCRIPTION 1 tab PHW7N60 d g drain 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS ID Continuous drain current IDM PD ∆PD/∆Tmb VGS EAS Pulsed drain current Total dissipation Linear derating factor Gate-source voltage Single pulse avalanche energy Peak avalanche current Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C Tmb > 25 ˚C IAS Tj, Tstg Operating junction and storage temperature range VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 10 V VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 10 V MIN. MAX. UNIT - 7 4.5 28 147 1.176 ± 30 570 A A A W W/K V mJ - 7 A - 55 150 ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient Rth j-a June 1997 CONDITIONS 1 MIN. TYP. MAX. UNIT - - 0.85 K/W - 45 - K/W Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHW7N60 ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS VGS = 0 V; ID = 0.25 mA 600 - - V ∆V(BR)DSS / ∆Tj RDS(ON) VGS(TO) gfs IDSS Drain-source breakdown voltage Drain-source breakdown voltage temperature coefficient Drain-source on resistance Gate threshold voltage Forward transconductance Drain-source leakage current VDS = VGS; ID = 0.25 mA - 0.7 - V/K IGSS Gate-source leakage current VGS = 10 V; ID = 4.1 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 4.1 A VDS = 600 V; VGS = 0 V VDS = 480 V; VGS = 0 V; Tj = 125 ˚C VGS = ±30 V; VDS = 0 V 2.0 3 - 0.9 3.0 4.5 2 50 10 1.2 4.0 100 500 200 Ω V S µA µA nA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 6.2 A; VDD = 360 V; VGS = 10 V - 90 6 44 110 7 60 nC nC nC td(on) tr td(off) tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 300 V; ID = 6.2 A; RG = 9.1 Ω; RD = 47 Ω - 17 43 118 50 - ns ns ns ns Ld Internal drain inductance - 5 - nH Ls Internal source inductance Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad - 12.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1100 140 80 - pF pF pF MIN. TYP. MAX. UNIT SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IS Tmb = 25˚C - - 7 A Tmb = 25˚C - - 28 A VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage IS = 7 A; VGS = 0 V - - 1.5 V trr Reverse recovery time IS = 6.2 A; VGS = 0 V; dI/dt = 100 A/µs - 530 - ns Qrr Reverse recovery charge - 6.7 - µC ISM June 1997 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 120 PHW7N60 Normalised Power Derating PD% 1 BUKx57-mv Zth j-mb / (K/W) D= 0.5 110 100 90 0.2 80 0.1 70 0.1 0.05 60 50 0.02 40 0.01 30 tp PD 0 20 10 0 0 20 40 60 80 100 Tmb / C 120 1E-05 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% 1E-03 t/s tp T t T 0.001 140 D= ID, Drain current (Amps) 20 PHP6N60 Tj = 25 C 110 10 V 7V 100 90 15 6V 80 5.5 V 70 60 50 10 5V 40 30 VGS = 4.5 V 5 20 10 0 0 20 40 60 80 Tmb / C 100 120 0 140 0 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V 100 ID / A 5 10 15 20 25 VDS, Drain-Source voltage (Volts) 30 Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS BUK457-600B PHP6N60 RDS(on), Drain-Source on resistance (Ohms) 4 Tj = 25 C 5V VGS = 4.5 V ID S/ = N) VD 3 tp = 10 us O S( 10 RD 5.5 V 100 us 2 6V 1 ms 1 10 V DC 10 ms 100 ms 1 0.1 10 100 0 1000 VDS / V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp June 1997 0 5 10 ID, Drain current (Amps) 15 20 Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHW7N60 ID, Drain current (Amps) VDS = 30 V 20 VGS(TO) / V PHP6N60 max. 4 Tj = 25 C 15 typ. 3 Tj = 150 C 10 min. 2 5 0 1 0 0 2 4 6 VGS, Gate-Source voltage (Volts) 8 -60 10 gfs, Transconductance (S) 0 20 40 60 Tj / C 80 100 120 140 PHP6N60 1E-01 SUB-THRESHOLD CONDUCTION ID / A VDS = 30 V 8 1E-02 6 1E-03 Tj = 25 C 150 C 4 1E-04 2 1E-05 0 -20 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj 10 -40 2% typ 98 % 1E-06 0 5 10 ID, Drain current (A) 15 0 20 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj 2 VGS / V 3 4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) a 1 10000 PHP6N60 Junction capacitances (pF) 2 Ciss 1000 1 100 Coss Crss 0 -60 -40 -20 0 20 40 60 Tj / C 80 10 100 120 140 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 6.2 A; VGS = 10 V June 1997 1 10 100 VDS, Drain-Source voltage (Volts) 1000 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 15 PHW7N60 PHP6N60 VGS, Gate-Source voltage (Volts) 20 PHP6N60 IF, Source-Drain diode current (Amps) VGS = 0 V ID = 6.2 A Tj = 25 C 240 V 120 V VDD = 360 V 15 10 10 Tj = 25 C 150 C 5 5 0 0 50 100 Qg, Gate charge (nC) 0 150 Switching times (ns) PHP6N60 120 VDD = 300 V VGS = 10 V RD = 47 Ohms ID = 6.2 A Tj = 25 C 0.4 0.6 0.8 1 VSDS, Source-Drain voltage (Volts) 1.2 1.4 EAS, Normalised unclamped inductive energy (%) 110 100 90 80 70 td(off) 100 0.2 Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS 1000 0 60 50 tf tr 40 30 20 td(on) 10 0 10 10 20 30 40 RG, Gate resistance (Ohms) 50 0 60 20 Fig.14. Typical switching times. td(on), tr, td(off), tf = f(RG) 1.15 40 60 80 100 Starting Tj ( C) 120 140 Fig.17. Normalised unclamped inductive energy. EAS% = f(Tj) Normalised Drain-source breakdown voltage V(BR)DSS @ Tj + V(BR)DSS @ 25 C 1.1 VDD L 1.05 VDS - VGS 1 -ID/100 0 0.95 0.9 0.85 -100 RGS -50 0 50 Tj, Junction temperature (C) 100 R 01 shunt 150 Fig.18. Unclamped inductive test circuit. EAS = 0.5 ⋅ LID2 ⋅ V(BR)DSS /(V(BR)DSS − VDD ) Fig.15. Normalised drain-source breakdown voltage. V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj) June 1997 T.U.T. 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHW7N60 MECHANICAL DATA Dimensions in mm 5.3 max 16 max 1.8 Net Mass: 5 g 5.3 o 3.5 max 7.3 3.5 21 max seating plane 15.5 max 2.5 15.5 min 4.0 max 1 2 3 0.9 max 2.2 max 1.1 3.2 max 5.45 0.4 M 5.45 Fig.19. SOT429 (TO247); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelopes. 3. Epoxy meets UL94 V0 at 1/8". June 1997 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHW7N60 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1997 7 Rev 1.000