Philips Semiconductors Product specification PowerMOS transistor GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting featuring high avalanche energy capability, stable off-state characteristics, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. PINNING - SOT404 PIN PHB2N50 QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance PIN CONFIGURATION MAX. UNIT 500 2 50 5 V A W Ω SYMBOL DESCRIPTION d mb 1 gate 2 drain 3 source mb g 2 drain 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS ID Continuous drain current IDM PD ∆PD/∆Tmb VGS EAS Pulsed drain current Total dissipation Linear derating factor Gate-source voltage Single pulse avalanche energy Peak avalanche current Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C Tmb > 25 ˚C IAS Tj, Tstg Operating junction and storage temperature range MIN. MAX. UNIT - 2 1.3 8 50 0.4 ± 30 100 A A A W W/K V mJ - 2 A - 55 150 ˚C VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 10 V VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 10 V THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient Rth j-a June 1997 CONDITIONS pcb mounted, minimum footprint 1 TYP. MAX. UNIT - 2.5 K/W 50 - K/W Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHB2N50 ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V(BR)DSS VGS = 0 V; ID = 0.25 mA 500 - - V ∆V(BR)DSS / ∆Tj RDS(ON) VGS(TO) gfs IDSS Drain-source breakdown voltage Drain-source breakdown voltage temperature coefficient Drain-source on resistance Gate threshold voltage Forward transconductance Drain-source leakage current VDS = VGS; ID = 0.25 mA - 0.6 - V/K IGSS Gate-source leakage current 2.0 0.5 - 3.1 3.0 1.3 1 30 10 5 4.0 25 250 200 Ω V S µA µA nA Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 2 A; VDD = 400 V; VGS = 10 V - 20 2 12 25 3 15 nC nC nC td(on) tr td(off) tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 250 V; ID = 2 A; RG = 24 Ω; RD = 120 Ω - 10 20 60 20 - ns ns ns ns Ld Ld Internal drain inductance Internal drain inductance - 3.5 4.5 - nH nH Ls Internal source inductance Measured from tab to centre of die Measured from drain lead solder point to centre of die Measured from source lead solder point to source bond pad - 7.5 - nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 236 40 22 - pF pF pF MIN. TYP. MAX. UNIT VGS = 10 V; ID = 1 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 1 A VDS = 500 V; VGS = 0 V VDS = 400 V; VGS = 0 V; Tj = 125 ˚C VGS = ±30 V; VDS = 0 V SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IS Tmb = 25˚C - - 2 A Tmb = 25˚C - - 8 A VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage IS = 2 A; VGS = 0 V - - 1.2 V trr Qrr Reverse recovery time Reverse recovery charge IS = 2 A; VGS = 0 V; dI/dt = 100 A/µs - 300 2.1 - ns µC ISM June 1997 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Normalised Power Derating PD% 120 PHB2N50 1E+01 Zth j-mb / (K/W) 110 D= 100 90 80 0.5 1E+00 70 0.2 60 50 0.1 0.05 40 1E-01 30 0.02 20 10 PD tp D= tp T 0 0 0 20 40 60 80 100 Tmb / C 120 140 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 1E-05 1E-03 t/s 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% 120 t T 1E-02 1E-07 6 PHP2N50 ID, Drain current (Amps) Tj = 25 C 110 100 90 5 20 V 80 4 10 V 70 60 50 3 40 2 7V 6.5 V 6V 30 20 10 1 0 0 5.5 V VGS = 5 V 0 20 40 60 80 Tmb / C 100 120 140 0 5 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V 10 )= tp = 10 us VD N S(O 30 PHP2N50 Drain-Source on resistance, RDS(ON) (Ohms) 5V 5.5 V 6 V 6.5 V 10 D S/I Tmb = 25 C 25 Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS PHP2N50 Drain current, ID (Amps) 10 15 20 VDS, Drain-Source voltage (Volts) Tj = 25 C 8 RD 7V 100us 1 6 1 ms DC 0.1 10 V 10 ms VGS = 20 V 4 100ms 2 0.01 10 100 Drain-source voltage, VDS (Volts) 0 1000 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp June 1997 0 1 2 3 Drain current, ID (Amps) 4 5 Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 6 PHB2N50 VGS(TO) / V PHP2N50 Drain current, ID (A) VDD = 30 V max. 4 5 Tj = 25 C typ. 3 4 150 C 3 min. 2 2 1 1 0 0 0 2 4 6 Gate-source voltage, VGS (V) 8 -60 10 Transconductance, gfs (S) -20 0 20 40 60 Tj / C 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj 2.5 -40 PHP2N50 1E-01 SUB-THRESHOLD CONDUCTION ID / A VDD = 30 V 1E-02 2 Tj = 25 C 150 C 1 typ 98 % 1E-04 1E-05 0.5 0 2% 1E-03 1.5 1E-06 0 1 2 3 4 Drain current, ID (A) 5 0 6 Fig.8. Typical transconductance. gfs = f(ID); parameter Tj 2 VGS / V 3 4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) a 1 1000 PHP2N50 Capacitances, Ciss, Coss, Crss (pF) 2 Ciss 100 Coss 1 10 0 -60 -40 -20 0 20 40 60 Tj / C 80 1 100 120 140 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 1 A; VGS = 10 V June 1997 Crss 1 10 100 Drain-source voltage, VDS (V) 1000 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor 20 PHB2N50 Gate-Source voltage, VGS (Volts) ID = 2 A PHP2N50 10 200 V 15 PHP2N50 Source-drain diode current, IF(A) VGS = 0 V 300 V 8 VDD = 400 V Tj = 25 C 150 C 6 10 4 5 2 0 0 10 20 Gate charge, Qg (nC) 30 0 40 Switching times, td(on), tr, td(off), tf (ns) 0.5 1 Source-Drain voltage, VSDS (V) 1.5 Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS 1000 0 PHP2N50 120 VDD = 250V RD = 120 Ohms Tj = 25 C EAS, Normalised unclamped inductive energy (%) 110 100 90 100 80 td(off) 70 60 50 tr tf 10 40 30 td(on) 20 10 1 0 20 40 60 Gate resistance, RG (Ohms) 80 0 100 20 Fig.14. Typical switching times. td(on), tr, td(off), tf = f(RG) 1.15 40 60 80 100 Starting Tj ( C) 120 140 Fig.17. Normalised unclamped inductive energy. EAS% = f(Tj) Normalised Drain-source breakdown voltage V(BR)DSS @ Tj + V(BR)DSS @ 25 C 1.1 VDD L 1.05 VDS - VGS 1 -ID/100 0 0.95 0.9 0.85 -100 RGS -50 0 50 Tj, Junction temperature (C) 100 R 01 shunt 150 Fig.18. Unclamped inductive test circuit. EAS = 0.5 ⋅ LID2 ⋅ V(BR)DSS /(V(BR)DSS − VDD ) Fig.15. Normalised drain-source breakdown voltage. V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj) June 1997 T.U.T. 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHB2N50 MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.19. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.20. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". June 1997 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHB2N50 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1997 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1997 7 Rev 1.000