PHILIPS PCF8549U/2/F1

INTEGRATED CIRCUITS
DATA SHEET
PCF8549
65 × 102 pixels matrix LCD driver
Product specification
File under Integrated Circuits, IC12
1997 Nov 21
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
FEATURES
• Single chip LCD controller/driver
• 65 row and 102 column outputs
• Display data RAM 65 × 102 bits
• On-chip:
– Generation of LCD supply voltage
GENERAL DESCRIPTION
– Generation of intermediate LCD bias voltages
• Logic supply voltage range VDD1 − VSS: 1.5 to 6 V
The PCF8549 is a low power CMOS LCD controller driver,
designed to drive a graphic display of 65 rows and
102 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD supply and bias voltages, resulting in a minimum of
external components and low power consumption. The
PCF8549 interfaces to most microcontrollers via an
I2C interface.
• Voltage generator voltage range VDD2/2_HV − VSS:
2.4 to 5 V
Packages
– Oscillator requires no external components (external
clock also possible)
• 400 kHz Fast I2C Interface
• CMOS compatible inputs
• Mux rate: 65
• Display supply voltage range VLCD − VSS: 7.0 to 16 V
• Low power consumption, suitable for battery operated
systems
The PCF8549U/2 is available as bumped die. Sawn wafer
as chip sorted in chip tray. For further details see
Section “Bonding pads”.
• Temperature compensation of VLCD
Customized TCP upon request.
• Interlacing for better display quality
• Slim chip layout, suited for chip-on-glass applications.
APPLICATIONS
• Telecom equipment
• Portable instruments
• Point of sale terminals.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8549U/2/F1
1997 Nov 21
TRAY
DESCRIPTION
chip with bumps in tray
2
VERSION
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
BLOCK DIAGRAM
R0 to R64
C0 to C101
COLUMN DRIVERS
ROW DRIVERS
DATA LATCHES
VLCD2
SHIFT REGISTER
Bias voltage generator
OSCILLATOR
VLCD1
Dual Ported RAM
65x102 Bit
HVGEN
7 stages
TIMING GENERATOR
Fig.1 Block diagram.
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VDD1
VDD2
VDD2_HV
VSS1
VSS2
VSS2_HV
T6
T7
T1
T2
T3
T4
T5
DISPLAY CONTROL LOGIC
RES
SA0
SDA_out
SDA
SCL
IIC INTERFACE
OSC
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
PINNING
SYMBOL
DESCRIPTION
R0 to R64
LCD row driver outputs
C0 to C101
LCD column driver outputs
VSS1,2,2_HV
negative power supply
VDD1,2,2_HV
supply voltage
VLCD1,2
LCD supply voltage
T1
test 1 input
T2
test 2 output
T3
test 3 I/O
T4
test 4 I/O
T5
test 5 input
T6
test 6 input
T7
test 7 input
SDA
I2C data input
SCL
I2C clock line
SDA_OUT
I2C output
SA0
least significant bit of slave address
OSC
oscillator
RES
external reset input, low active
Pin functions
R0 TO R64: ROW DRIVER OUTPUTS
These pads output the row signals.
C0 TO C101: COLUMN DRIVER OUTPUTS
These pads output the column signals.
VSS1,2,2_HV: NEGATIVE POWER SUPPLY RAILS
Negative power supplies.
VDD1,2,2_HV: POSITIVE POWER SUPPLY RAILS
VDD2 and VDD2_HV are the supply voltages for the internal voltage generator. Both have to be on the same voltage and
may be connected together outside of the chip. If the internal voltage generator is not used, they should be both
connected to ground. VDD1 is used as power supply for the rest of the chip. This voltage can be a different voltage than
VDD2 and VDD2_HV.
VLCD1,2: LCD POWER SUPPLY
Positive power supply for the liquid crystal display. If the internal voltage generator is used, the two supply rails
VLCD1 and VLCD2 must be connected together. An external LCD supply voltage can be supplied using the V pad. In this
case, VLCD1 has to be connected to ground, and the internal voltage generator has to be programmed to zero. If the
PCF8549 is in power-down mode, the external LCD supply voltage has to be switched off.
1997 Nov 21
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
T1, T2, T3, T4, T5, T6 AND T7: TEST PADS
FUNCTIONAL DESCRIPTION
T1, T3, T4, T5, T6 and T7 must be connected to VSS1, T2
is to be left open. Not accessible to user.
Block diagram functions
SDA/SDA_OUT: I2C DATA LINES
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to VDD1. An external
clock signal, if used, is connected to this input.
OSCILLATOR
Output and input are separated. If both pads are
connected together they behave like a standard I2C pad.
SCL: I2C CLOCK SIGNAL
Input for the
I2C-bus
I2C INTERFACE
clock signal.
The I2C interface receives and executes the commands
sent via the I2C-bus. It also receives RAM-data and sends
them to the RAM. During read access the 8-bit parallel
data or the status register content is converted to a serial
data stream and output via the I2C-bus.
SA0: SLAVE ADDRESS
With the SA0 pin two different slave addresses can be
selected. That allows to connect two PCF8549 LCD
drivers to the same I2C-bus.
DISPLAY CONTROL LOGIC
OSC: OSCILLATOR
When the on-chip oscillator is used this input must be
connected to VDD1. An external clock signal, if used, is
connected to this input.
The display control logic generates the control signals to
read out the RAM via the 101 bit parallel port. It also
generates the control signals for the row, and
column drivers.
RES: RESET
DISPLAY DATA RAM (DDRAM)
This signal will reset the device. Signal is active low.
The PCF8549 contains a 65 × 102 bit static RAM which
stores the display data. The RAM is divided into 8 banks of
102 bytes and one bank of 102 bits
((8 × 8 + 1) × 102 bits). During RAM access, data is
transferred to the RAM via the I2C interface. There is a
direct correspondence between X-address and column
output number.
TIMING GENERATOR
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the I2C-bus.
LCD ROW AND COLUMN DRIVERS
The PCF8549 contains 65 row and 102 column drivers,
which connect the appropriate LCD bias voltages to the
display in accordance with the data to be displayed.
Figure 2 shows typical waveforms. Unused outputs should
be left unconnected.
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
frame n
ROW 0
R0 (t)
VLCD
V2
V3
V4
V5
VSS
ROW 2
R2 (t)
VLCD
V2
V3
V4
V5
VSS
COL 0
C0 (t)
VLCD
V2
V3
V4
V5
VSS
COL 1
C1 (t)
VLCD
V2
V3
V4
V5
VSS
frame n+1
Vstate1(t)
Vstate2(t)
VLCD
Vstate1(t)
V3
VLCD - V2
0V
V 3 - V2
V4 - V5
0V
V5
V4 - VLCD
- VLCD
VLCD
Vstate2(t)
V3
VLCD - V2
0V
V 3 - V2
V4 - V5
0V
V5
V4 - VLCD
- VLCD
0 2 4 6 8 10 ...
... 64 1 3 5 7 9 ...
... 63 0 2 4 6 8 10 ...
... 64 1 3 5 7 9 ...
... 63
VSS=0V
Vstate1(t) = C1(t) - R0(t)
Vstate2(t) = C1(t) - R2(t)
Fig.2 Typical LCD driver waveforms.
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
DDRAM
bank 0
bank 1
bank 2
bank 3
bank 7
bank 8
Fig.3 DDRAM to display mapping.
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
The MX bit allows a horizontal mirroring: When MX = 1,
the X address space is mirrored: The address X = 0 is
then located at the right side (column 101) of the display
(see Fig.4). When MX = 0 the mirroring is disabled and the
address X = 0 is located at the left side (column 0) of the
display (see Fig.4).
Addressing
The Display data RAM of the PCF8549 is accessed as
indicated in Figs 3, 4, 4, 6 and 7. The display RAM has a
matrix of 65 × 102 bits. The columns are addressed by the
address pointer. The address ranges are:
X 0 to 101 (1100101b) and Y 0 to 8 (1000b). Addresses
outside these ranges are not allowed. In vertical
addressing mode (V = 1) the Y address increments (see
Fig.7) after each byte. After the last Y address (Y = 8)
Y wraps around to 0 and X increments to address the next
column. In horizontal addressing mode (V = 0) the
X address increments (see Fig.6) after each byte. After the
last X address (X = 101) X wraps around to
0 and Y increments to address the next row. After the very
last address (X = 101 and Y = 8) the address pointers
wrap around to address (X = 0 and Y = 0).
1997 Nov 21
If the RM-bit (read-modify-write mode) is set, the address
is only incremented after a write, otherwise the address is
incremented after both read and write access to the
display data RAM.
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
DISPLAY DATA RAM STRUCTURE
MSB
0
LSB
MSB
8
LSB
0
X-address
101
Y-address
Fig.4 RAM format, addressing (MX = 0).
MSB
0
LSB
MSB
8
LSB
101
X-address
Y-address
Fig.5 RAM format, addressing (MX = 1).
1997 Nov 21
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0
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
0
1
PCF8549
2
0
102 103 104
204 205 206
306 307 308
Y-address
408 409 410
510 511 512
612 613 614
714 715 716
816 817 818
917
8
101
0
X-address
Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
0
9
1
10
0
2
3
Y-address
4
5
6
7
8
917
0
101
8
Fig.7 Sequence of writing data bytes into RAM with vertical addressing (V = 1).
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
period of the clock pulse as changes in the data line at this
time will be interpreted as a control signal.
RAM access
If the D/C bit is 1 the RAM can be accessed in both read
and write access mode, depending on the R/W bit. The
data is written to the RAM during the acknowledge cycle.
START AND STOP CONDITIONS (see Fig.10)
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is
HIGH is defined as the STOP condition (P).
Set Address
SYSTEM CONFIGURATION (see Fig.11)
Set Read
Modify Write Mode
• Transmitter: The device which sends the data to the bus
• Receiver: The device which receives the data from the
bus
• Master: The device which initiates a transfer, generates
clock signals and terminates a transfer
Read Data
• Slave: The device addressed by a master
• Multi-Master: More than one master can attempt to
control the bus at the same time without corrupting the
message
Write Data
no
• Arbitration: Procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Finished?
• Synchronisation: Procedure to synchronize the clock
signals of two or more devices.
yes
ACKNOWLEDGE (see Fig.12)
END
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH signal put on the bus by
the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The
device that acknowledges must pull-down the SDA line
during the acknowledge clock pulse, so that the SDA line
is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken
into consideration). A master receiver must signal an end
of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a stop
condition.
Fig.8 Read modify write access.
I2C-BUS INTERFACE
Characteristics of the I2C-bus
The I2C-bus is for bi-directional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
BIT TRANSFER (see Fig.9)
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
SDA
SCL
change
of data
allowed
data line
stable;
data valid
MBC621
Fig.9 Bit transfer.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.10 Definition of start and stop conditions.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.11 System configuration.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
START
CONDITION
MBC602
Fig.12 Acknowledgement on the I2C-bus.
1997 Nov 21
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clock pulse for
acknowledgement
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
of the D/C-bit defines whether the data-byte is interpreted
as a command or as RAM-data.The control and data bytes
are also acknowledged by all addressed slaves on the bus.
I2C-bus protocol
The PCF8549 supports both read and write access. The
R/W bit is part of the slave address.
After the last control byte, depending on the D/C bit
setting, either a series of display data bytes or command
data bytes may follow. If the D/C bit was set to ‘1’, these
display bytes are stored in the display RAM at the address
specified by the data pointer. The data pointer is
automatically updated and the data is directed to the
intended PCF8549 device. If the D/C bit of the last control
byte was set to ‘0’, these command bytes will be decoded
and the setting of the device will be changed according to
the received commands. The acknowledgement after
each byte is made only by the addressed slave. At the end
of the transmission the I2C-bus master issues a stop
condition (P).
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. Two 7-bit slave
addresses (0111100 and 0111101) are reserved for the
PCF8549. The least significant bit of the slave address is
set by connecting the input SA0 to either logic 0 (VSS1) or
1 (VDD1).
The I2C-bus protocol is illustrated in Fig.13.
The sequence is initiated with a START condition (S) from
the I2C-bus master which is followed by the slave address.
All slaves with the corresponding address acknowledge in
parallel, all the others will ignore the I2C-bus transfer. After
acknowledgement, one or more command words follow
which define the status of the addressed slaves. A
command word consists of a control byte, which defines
Co and D/C, plus a data byte (see Fig.13 and Table 1).
If the R/W bit is set to one in the slave-address, the chip
will output data immediately after the slave-address
according to the D/C bit, which was sent during the last
write access. If no acknowledge is generated by the
master after a byte, the driver stops transferring data to the
master.
The last control byte is tagged with a cleared most
significant bit, the continuation bit Co. After a control byte
with a cleared Co-bit, only data bytes will follow. The state
acknowledgement
from PCF8549
S
S 0 1 1 1 1 0 A 0 A 1 DC
acknowledgement
from PCF8549
control byte
A
acknowledgement
from PCF8549
data byte
A 0 DC
acknowledgement
from PCF8549
acknowledgement
from PCF8549
control byte
A P
data byte
A
0
slave address
n > 0 bytes
MSB................. LSB
1 byte
2n > 0 bytes
Co
Co
acknowledgement
from Master
acknowledgement
from Master
acknowledgement
from Master
acknowledgement
from Master
S
S 0 1 1 1 1 0 A 1 A
data byte
A
data byte
A
data byte
A P
data byte
A
0
slave address
S
0 1 1 1 1 0 A R
0 W
CO DC 0 0
0 0 0
Control Byte
PCF8549
slave address
Fig.13 I2C-bus protocol.
1997 Nov 21
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13
A
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
INSTRUCTIONS
The instruction format is divided into two modes: If D/C is set low, the status byte can be read or commands can be sent
to the chip, depending on the R/W signal. If D/C is set high, the DDRAM will be accessed. Every instruction can be sent
in any order to the PCF8549.
Table 1
Instruction set
COMMAND BYTE
INSTRUCTION
D/C
R/W
DESCRIPTION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
H = 0 or 1
NOP
0
0
0
0
0
0
0
0
0
0
no operation
Function Set
0
0
0
0
1
MX
MY
PD
V
H
power down control; entry mode;
Extended Instruction Set control (H)
Read Status Byte
0
1
PD
X
X
D
E
MX
MY
X
reads status byte
Write Data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
writes data to RAM
Read Data
1
1
D7
D6
D5
D4
D3
D2
D1
D0
reads data from RAM
Set Read Modify
Write
0
0
0
0
0
0
0
0
1
RM
sets the read-modify-write mode
Reserved
0
0
0
0
0
0
0
1
X
X
do not use
Display Control
0
0
0
0
0
0
1
D
0
E
sets display configuration
Reserved
0
0
0
0
0
1
X
X
X
X
do not use
Set Y address of
RAM
0
0
0
1
0
0
Y3
Y2
Y1
Y0
sets Y-address of RAM: 0 ≤ Y ≤ 8
Set X address of
RAM.
0
0
1
X6
X5
X4
X3
X2
X1
X0
sets X-address of RAM: 0 ≤ X ≤ 101
Reserved
0
0
0
0
0
0
0
0
0
1
do not use
Reserved
0
0
0
0
0
0
0
0
1
X
do not use
Temperature Control 0
0
0
0
0
0
0
1
TC1
TC0
set temperature coefficient (TCx)
Reserved
0
0
0
0
0
0
1
X
X
X
do not use
Bias System
0
0
0
0
0
1
0
BS2
BS1
BS0
Set Bias System(BSx)
Reserved
0
0
0
1
X
X
X
X
X
X
do not use (reserved for test...)
Set VOP
0
0
1
VOP6
VOP5
VOP4
VOP3
VOP2
VOP1
VOP0
write VOP to register
H=0
H=1
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
Table 2
PCF8549
Explanations for symbols in Table 1
BIT
0
1
RESET STATE
PD
chip is active
chip is in power down mode
1
V
horizontal addressing
vertical addressing
0
H
use basic instruction set
use extended instruction set
0
MX
normal X-addressing
X-address is mirrored
0
MY
display is not vertically mirrored
display is vertically mirrored
0
RM
read-modify-write mode is disabled read-modify-write mode is enabled 0
D and E
00
display blank
10
normal mode
01
all display segments on
11
inverse video mode
TC[1 : 0] 00
VLCD temperature coefficient 0
01
VLCD temperature coefficient 1
10
VLCD temperature coefficient 2
11
VLCD temperature coefficient 3
BS[2 : 0]
D=0
E=0
TC[1 : 0] = 00
bias system
BS[2 : 0] = 000
External reset (RES)
After power-on a reset pulse has to be applied immediately to the chip, as it is in an undefined state. A reset of the chip
can be achieved with the external reset pin. After the reset the LCD driver is set to the following status:
• Power down mode (PD = 1)
• All LCD-outputs at VSS (display off)
• Read-modify-write mode is disabled (RM = 0)
• Horizontal addressing (V = 0)
• Normal instruction set (H = 0)
• Normal display (MX = MY = 0)
• Display blank (E = D = 0)
• Address counter X[6 : 0] = 0 and Y[3 : 0] = 0
• Temperature coefficient (TC[1 : 0] = 0)
• Bias system (BS[2 : 0] = 0)
• Read-modify-write mode disabled (RM = 0)
• VLCD is equal to 0, the HV generator is switched off (VOP[6 : 0] = 0)
• After power-on, RAM data are undefined; The reset signal does not change the content of the RAM.
Set read-modify-write
When RM = 0, the read-modify-write mode is disabled. The X/Y-address counter is incremented after every read or write
access to the display data RAM.
When RM = 1, the read-modify-write mode is enabled. In this mode the X/Y-address is incremented only after a write
access to the display data RAM. The X/Y-address will not be incremented after a read access to the RAM.
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
Function Set
MX
PD (POWER DOWN)
When MX = 0, the display is written from left to right (X = 0
is on the left side, X = 100 is on the right side of the
display). When MX = 1 the display is written from right to
left (X = 0 is on the right side, X = 100 is on the left side of
the display).
• All LCD outputs at VSS (display off)
• Bias generator and VLCD generator off
• Oscillator off (external clock possible)
• VLCD can be disconnected
MY
• Parallel bus, command, etc. function
When MY = 1, the display is mirrored vertically.
• RAM contents not cleared; RAM data can be written.
Display Control
V
D AND E
When V = 0, the horizontal addressing is selected. The
data is written into the RAM as shown in Fig.6. When
V = 1, the vertical addressing is selected. The data is
written into the RAM as shown in Fig.7.
The bits D and E select the display mode (see Table 2).
Set Y address of RAM
Y[3 : 0] defines the Y address vector address of the RAM.
H
When H = 0 the commands ‘display control’, ‘set
Y address’ and ‘set X address’ can be performed, when
H = 1 the other commands can be executed. The
commands ‘write data’ and ‘function set’ can be executed
in both cases.
Table 3
X-/Y-Address range
YYYY
3 210
CONTENT
ALLOWED X-RANGE
0000
bank 0 (display RAM)
0 to 101
0001
bank 1 (display RAM)
0 to 101
0010
bank 2 (display RAM)
0 to 101
0011
bank 3 (display RAM)
0 to 101
0100
bank 4 (display RAM)
0 to 101
0101
bank 5 (display RAM)
0 to 101
0110
bank 6 (display RAM)
0 to 101
0111
bank 7 (display RAM)
0 to 101
1000
bank 8 (display RAM)
0 to 101
In bank 8 only the MSB is accessed.
Set X address of RAM
The X address points to the columns. The range of X is 0 to 101(65 hex).
Temperature Control
Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage VLCD must be increased
with lower temperature to maintain optimal contrast. There are 4 different temperature coefficients available in the
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
PCF8549 (see Fig.14). The coefficients are selected by the two bits TC[1 : 0]. Table 6 shows the typical values of the
different temperature coefficients. The coefficients are proportional to the programmed VLCD.
VLCD
16oC(typ)
temperature
Fig.14 Temperature coefficients.
Bias value:
1
The bias voltage levels are set in the ratio of R − R − nR − R − R giving a ------------- bias system. The resulting bias levels
n+4
are shown in table 5.
Different multiplex rates require different factors n (see Table 4). This is programmed by BS[2 : 0]. For MUX 1 : 65 the
optimum bias value n is given by: n =
m–3 =
65 – 3 = 5.06 = 5
resulting in 1⁄9bias.
Table 4
Programming the required Bias system
BS[2]
BS[1]
BS[0]
n
b (RES. COUNT)
MUX RATE
0
0
0
7
11
1 : 100
0
0
1
6
10
1 : 81
0
1
0
5
9
1 : 64
0
1
1
4
8
1 : 49
1
0
0
3
7
1 : 36
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Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
BS[2]
BS[1]
BS[0]
n
b (RES. COUNT)
MUX RATE
1
0
1
2
6
1 : 24
1
1
0
1
5
1 : 16
1
1
1
0
4
1:9
Table 5
LCD bias voltage
SYMBOL
BIAS VOLTAGES⁄
V1
VLCD
V2
(b-1)/b × VLCD
V3
(b-2)/b × VLCD
V4
2/b × VLCD
V5
1/b × VLCD
V6
VSS
Set VOP value:
The operation voltage VLCD can be set by software. The generated voltage is dependent of the temperature, the
programmed temperature coefficient (TC), and the programmed voltage at reference temperature (TCUT).
(1)
V LCD = ( a + VOP ⋅ b ) + ( T – T CUT ) ⋅ TC
The voltage at reference temperature (VLCD(T=TCUT)) can be calculated as:
(2)
V LCD = ( a + VOP ⋅ b )
The parameters are explained in table 6.
The maximum voltage that can be generated is depending on the VDD2/2_HV Voltage and the display load current. The
relation ship is shown in Fig.16.
The charge pump is turned off if Vop[6 : 0] is set to zero.
For Mux 1 : 65 the optimum operation voltage of the liquid can be calculated as:
1 + 65
V LCD = --------------------------------------- ⋅ V th = 6.85 ⋅ V th
1
2 ⋅  1 – ---------- 

65 
where Vth is the threshold voltage of the liquid crystal material used.
1997 Nov 21
18
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
VLCD
b
a
00 01 02 03 04 05 06 07 08 09 0A ...
VOP[6:0] (programmed) [00 hex ... 7F hex]
Fig.15 VOP programming of PCF8549.
Table 6
Typical values for parameters for the HV-Generator programming
SYMBOL
VALUE
a
7.06
UNIT
V
b
0.06
V
TCUT
16
0C
TC
V/oC
00
– 0.142 ⋅ 10
–3
⋅ V LCD ( T = T CUT )
V/oC
01
– 1.3 ⋅ 10
–3
⋅ V LCD ( T = T CUT )
V/oC
10
– 2.467 ⋅ 10
–3
⋅ V LCD ( T = T CUT )
V/oC
11
– 3.483 ⋅ 10
1997 Nov 21
–3
⋅ V LCD ( T = T CUT )
19
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134); all voltages referred to VSS = 0V unless otherwise
specified.
SYMBOL
PARAMETER
MIN
MAX
UNIT
V
VDD
supply voltage range
-0.5
+7
VLCD
supply voltage range LCD
-0.5
+17
V
ISS
supply current
-50
50
mA
Vi/VO
input/output voltage range
-0.5
VDD+0.5
V
VOLCD
LCD output voltage range
-0.5
VLCD+0.5
V
Ii
DC input current
-10
10
mA
Io
DC output current
-10
10
mA
PTOT
power dissipation per package
-
300
mW
PO
power dissipation per output
-
50
mW
TAMB
operating ambient temperature.
range
-40
+85
°C
TSTG
storage temperature range
-65
+150
°C
Notes
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3. with external LCD supply voltage external supplied (voltage generator disabled). VDDmax (VDD2,VDD2_HV) is 5V if
LCD supply voltage is internally generated (voltage generator enabled).
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”). The PCF8549
withstands the following stress:
• approximately 1.0kV Human Body Model
• approximately 150V Machine Model
1997 Nov 21
20
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
DC CHARACTERISTICS
Table 7
VDD1 = 1.5 to 6 V; VDD2/2_HV = 2.4 to 5.0 V; VDD2 = VDD2_HV; VSS1 = VSS2 = VSS2_HV = 0 V; VLCD = 7 to 16 V;
Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD1
Logic supply
voltage range
1.5
VDD2,
VDD2_HV
HV Generator
supply range
2.4
IVDD1
supply current
internal VLCD
VLCD = 10.0V; fscl = 0;
display load = 0;
IVDD2/2_HV
supply current
internal VLCD
IVDD1
TYP
3
MAX
UNIT
6
V
5
V
30
80
µA
VLCD = 10.0V; fscl = 0;
display load = 0; (1)(5)
600
1200
µA
supply current
external VLCD
VLCD = 10.0V; fscl = 0;
display load = 0;
30
80
µA
IVDD2/2_HV
supply current
external VLCD
VLCD = 10.0V; fscl = 0;
display load = 0; (2)(5)
0
10
µA
IVDD1
supply current
power-down mode; VLCD = 0V;
fscl = 0; display load = 0
0.5
10
µA
ILCD
supply current
external VLCD
VLCD = 10 V; fSCL= 0,
display load = 0; (2)
50
130
µA
VLCD(tol)
VLCD tolerance
internal generated
VDD = 2.7V; VLCD = 10V; fSCL = 0;
display load = 0;(3)(4)(6)
VIL
LOW level input voltage
VSS
0.3VDD V
VIH
HIGH level input
voltage
0.7 VDD
VDD
IOL
LOW level output
current (SDA)
VOL = 0.4V;
VDD1 = 5 V
VI = VDD1 or VSS1
+/- 500 mV
3.0
V
mA
IL
leakage current
+1
µA
RROW
Row output resistance R0 to R64
12
20
kOhm
RCOL
Column output resistance C0 to C101
12
20
kOhm
-1
Note
1. When a display is connected the IVDD2_HV increases with 7 x display load current due to 7 stage charge pump.
2. With external VLCD, the display load current does not translate into increased IVDD2_HV.
3. For TC1, TC2 and TC3
4. The maximum possible VLCD voltage that may be generated is dependent on voltage (VDD2/2_HV), temperature and
(display) load.
5. VDD2 VDD2_HV connected together
6. Difference to the theoretical value given by equation 1
1997 Nov 21
21
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
AC CHARACTERISTICS
Table 8
VDD1 = 1.5 to 6 V; VDD2/2_HV = 2.4 to 5.0 V; VDD2 = VDD2_HV; VSS1 = VSS2 = VSS2_HV = 0 V; VLCD = 7 to 16 V;
Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
fOSC
oscillator frequency
fEXT
external clock frequency
(2)
oscillator start up time
(5)
tstart
fFRAME
frame frequency
tVHRL
VDD to RES Low
tPWRES
reset low pulse width
fEXT
(5)
= 32
kHz;(1)
MIN.
TYP.
MAX.
UNIT
19
32
64
kHz
10
32
64
kHz
−
450
1600
us
−
62
−
Hz
1
ms
400
−
−
ns
I2C timing characteristics
fSCLK
SCL clock frequency
DC
−
400
kHz
tLOW
SCL clock low period
1.3
−
−
us
tHIGH
SCL clock high period
0.6
−
−
us
tSU;Data
Data set-up time
100
−
−
ns
tHD;Data
Data hold time
0
−
0.9
us
tR
SCL and SDA rise time
(3)
20 + 0.1 Cb −
300
ns
tF
SCL and SDA fall time
(3)
20 + 0.1 Cb −
300
ns
cb
Capacitive load represented by each
bus line
−
−
400
pF
tSU;STA
setup time for a repeated START condition
0.6
−
−
us
tHD;STA
start condition hold time
0.6
−
−
us
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold-time
0
−
−
ns
tSU;STO
setup time for STOP condition
0.6
−
−
us
−
−
50
ns
1.3
−
−
us
tSW
tolerable spike width on bus
tBUF
BUS free time between a STOP and
START condition
(6)
(4)
Note
1.
f EXT
f FRAME = ---------520
2. Duty cycle of 50 +/-5%.
3. The rise and fall times specified here refer to the driver device (i.e. not PCF8549) and are part of the general fast
I2C-bus specification. When PCF8549 asserts an acknowledge on SDA, the minimum fall time is 10ns. Cb=
capacitive load per bus line.
4. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width < tSW(max).
5. Not tested in production
6. Only for VDD1= 2V to 6V
1997 Nov 21
22
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
TYPICAL CHARACTERISTICS
16V
VLCD
15V
I=0uA
14V I=10uA
I=20uA
13V
I=40uA
12V
0V
1V
2V
3V
4V
5V
VDD2, VDD2_HV
Fig.16 VLCD dependency of VDD2,
VDD2_HV and load current. Programmed
VLCD=15.8V (@ Room Temperature in
special Test mode)
RESET
VDD
tVHRL
tPWRES
RES
Fig.17 Reset timing.
1997 Nov 21
23
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
APPLICATION INFORMATION
Table 9
programming example for PCF8549
STEP
DISPLAY
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
I2C start
2
0
1
1
1
1
0
0
0
Slave address for write
3
0
0
0
0
0
0
0
0
Control byte with cleared CO bit
and D/C set to 0.
4
0
0
1
0
0
0
0
1
Function Set
PD = 0; V = 0; select extended
instruction set (H = 1 mode)
5
0
0
0
1
0
0
1
0
Set Bias System 2. This is the
recommended Bias System for a
multiplex rate 1:65
6
1
1
1
0
1
0
1
0
set VOP
VOP is set to a +16 × b [V].
Please note: The required
voltage is depending on the
liquid.
7
0
0
1
0
0
0
0
0
Function Set
PD = 0; V = 0; select normal
instruction set (H = 0 mode)
8
0
0
0
0
1
1
0
0
Display Control
set normal mode
(D = 1 and E = 0)
9
I2C start
Restart: To write into the Display
RAM the D/C must be set to 1;
therefore a control byte is
needed.
10
0
1
1
1
1
0
0
0
Slave address for write
11
0
1
0
0
0
0
0
0
Control byte with cleared CO bit
and D/C set to 1.
12
1
1
1
1
1
0
0
0
Data Write
Y and X are initialized to 0 by
default, so they aren’t set here
13
1
0
1
0
0
0
0
0
Data Write
14
1
1
1
0
0
0
0
0
Data Write
1997 Nov 21
24
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
STEP
DISPLAY
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
15
0
0
0
0
0
0
0
0
Data Write
16
1
1
1
1
1
0
0
0
Data Write
17
0
0
1
0
0
0
0
0
Data Write
18
1
1
1
1
1
0
0
0
Data Write
19
I2C start
Restart
20
0
1
1
1
1
0
0
0
Slave address for write
21
1
0
0
0
0
0
0
0
Control byte with set CO bit and
D/C set to 0.
22
0
0
0
0
1
1
0
1
Display Control
Set inverse video mode
(D = 1 and E = 1)
23
1
0
0
0
0
0
0
0
Control byte with set CO bit and
D/C set to 0.
24
1
0
0
0
0
0
0
0
Set X address of RAM
set address to ‘0000000’
25
1
1
0
0
0
0
0
0
Control byte with set CO bit and
D/C set to 1.
26
0
0
0
0
0
0
0
0
Data Write
27
0
0
0
0
0
0
0
0
Control byte with cleared CO bit
and D/C set to 0.
28
1
0
0
0
0
0
0
0
Set X address of RAM
Set address to ‘0000000’
29
0
0
0
0
0
0
0
1
Set Read Modify Write Mode
1997 Nov 21
25
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
STEP
DISPLAY
OPERATION
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
30
I2C start
Restart
31
0
1
1
1
1
0
0
0
Slave address for write
32
1
1
0
0
0
0
0
0
Control byte with set CO bit and
D/C set to 1.
33
I2C start
Restart
34
0
1
1
1
1
0
0
1
Slave address for read
35
1
0
0
0
0
0
0
0
Read Data From
Address ‘0000000’
36
1
0
0
0
0
0
0
0
Read Data From
Address ‘0000000’ again.
Master does not send an
acknowledge to stop the read
access.
37
I2C start
Restart
38
0
1
1
1
1
0
0
0
Slave address for write
39
1
1
0
0
0
0
0
0
Control byte with set CO bit and
D/C set to 1.
40
1
1
1
1
1
0
0
0
Write Data
41
1
0
0
0
0
0
0
0
Control byte with set CO bit and
D/C set to 0.
42
I2C start
Restart
43
0
1
1
1
1
0
0
1
Slave address for read
44
1
0
0
0
0
0
0
0
Read Status Byte
APPLICATION INFORMATION
1997 Nov 21
26
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
SCL
PCF8549
SCL
VDD1
SDA
SDA
SDA_OUT
Fig.18 Application diagram: Connecting the I2C Interface
1997 Nov 21
27
Microcontroller
VDD1
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
DISPLAY 102x65
33
102
32
PCF8549
13
C4
VDD1
C3
VLCD
C1
I/O
VDD2
VDD2_HV
C 1 ≥ 100nF
C 2 ≥ 100nF
C 3 ≥ 1uF
C 4 ≥ 100nF
C2
VSS
VDD1 – VSS ≥ 1.5V
VDD2 – VSS ≥ 2.4V
VDD2HV = VDD2
Fig.19 Application diagram: Connecting the power supplies
The pinning of the PCF8549 is optimized for single plane wiring e.g. for chip-on-glass display modules.
Display size: 65 × 102 pixels.
CHIP INFORMATION
The PCF8549 is manufactured in n-well CMOS technology.
The substrate is on VSS potential.
1997 Nov 21
28
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
BONDING PADS
VALUE
UNIT
min. 100
µm
Pad size, alumin. 80 × 100
µm
Pad pitch
Passivation.
48 × 78
µm
Bumps
60 (±6) × 90 (±6) × 17.5 (±5) µm
Wafer thickness
380 (±25)
1997 Nov 21
µm
29
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
VDD2
VDD2_HV
RES
SDA_OUT
SDA
SCL
T2
SA0
T7
T6
T5
T4
T3
T1
VSS1
VSS2_HV
VSS2
VLCD_1
VLCD2
R0
R30
Dummy
2.74mm
Fig.20 Pads.
1997 Nov 21
30
DUMMY
R63
R33
C0
16.39mm
VDD1
111
11
111
1111
111
1111111
1111
1111
111
111
111
11111
11111
111
1111
111
111
1111
11111
111
111
11111
1111
111
111
111
11111
11111
111
1111111111111
OSC
Recognition
Pattern
Recognition
pattern
R1
111
111
1111
111
11 11 1 1111
1111111111111111 11 111 1111111 1 11 11111111111
PC8549
11
Pad 1
Dummy
R31
PCF8549
C101
R32
R34
R64
DUMMY
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
Table 10 Bonding pad locations (dimensions in um).
Pad
Pad name
X
Pad
Pad name
X
Y
Y
41
ROW<60>
570
84
1
T2
7359.5
2462
42
ROW<58>
670
84
2
SA0
6958
2462
43
ROW<56>
770
84
3
T7
6679
2462
44
ROW<54>
870
84
4
T6
6400
2462
45
ROW<52>
970
84
5
T5
6121
2462
46
ROW<50>
1070
84
6
T4
5841.5
2462
47
ROW<48>
1170
84
7
T3
5431.5
2462
48
ROW<46>
1270
84
8
T1
5022
2462
49
ROW<44>
1370
84
9
VSS1
4724
2458
50
ROW<42>
1470
84
10
VSS1
4624
2458
51
ROW<40>
1570
84
11
VSS2_HV
4359
2458
52
ROW<38>
1670
84
12
VSS2_HV
4259
2458
53
ROW<36>
1770
84
13
VSS2_HV
4159
2458
54
ROW<34>
1870
84
14
VSS2
3458.5
2458
55
ROW<32>
2137
84
15
VLCD1
2580
2462
56
COL<101>
2812
84
16
VLCD2
2294
2462
57
COL<100>
2914
84
17
ROW<0>
1870
2437
58
COL<99>
3014
84
18
ROW<2>
1770
2437
59
COL<98>
3114
84
19
ROW<4>
1670
2437
60
COL<97>
3214
84
20
ROW<6>
1570
2437
61
COL<96>
3314
84
21
ROW<8>
1470
2437
62
COL<95>
3560
84
22
ROW<10>
1370
2437
63
COL<94>
3660
84
23
ROW<12>
1270
2437
64
COL<93>
3760
84
24
ROW<14>
1170
2437
65
COL<92>
3860
84
25
ROW<16>
1070
2437
66
COL<91>
3960
84
26
ROW<18>
970
2437
67
COL<90>
4060
84
27
ROW<20>
870
2437
68
COL<89>
4160
84
28
ROW<22>
770
2437
69
COL<88>
4260
84
29
ROW<24>
670
2437
70
COL<87>
4360
84
30
ROW<26>
570
2437
71
COL<86>
4460
84
31
ROW<28>
470
2437
72
COL<85>
4560
84
32
ROW<30>
370
2437
73
COL<84>
4660
84
33
Dummy 4
270
2437
74
COL<83>
4760
84
34
Dummy 5
170
2437
75
COL<82>
4860
84
35
Dummy 6
70
2437
76
COL<81>
4960
84
36
Dummy 3
70
84
77
COL<80>
5060
84
37
Dummy 2
170
84
78
COL<79>
5306
84
38
Dummy 1
270
84
79
COL<78>
5406
84
39
ROW<64>
370
84
80
COL<77>
5506
84
40
ROW<62>
470
84
1997 Nov 21
31
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
Pad
Pad name
X
PCF8549
Y
Pad
Pad name
X
Y
81
COL<76>
5606
84
121
COL<36>
9898
84
82
COL<75>
5706
84
122
COL<35>
9998
84
83
COL<74>
5806
84
123
COL<34>
10098
84
84
COL<73>
5906
84
124
COL<33>
10198
84
85
COL<72>
6006
84
125
COL<32>
10298
84
86
COL<71>
6106
84
126
COL<31>
10544
84
87
COL<70>
6206
84
127
COL<30>
10644
84
88
COL<69>
6306
84
128
COL<29>
10744
84
89
COL<68>
6406
84
129
COL<28>
10844
84
90
COL<67>
6506
84
130
COL<27>
10944
84
91
COL<66>
6606
84
131
COL<26>
11044
84
92
COL<65>
6706
84
132
COL<25>
11144
84
93
COL<64>
6806
84
133
COL<24>
11244
84
94
COL<63>
7052
84
134
COL<23>
11344
84
95
COL<62>
7152
84
135
COL<22>
11444
84
96
COL<61>
7252
84
136
COL<21>
11544
84
97
COL<60>
7352
84
137
COL<20>
11644
84
98
COL<59>
7452
84
138
COL<19>
11744
84
99
COL<58>
7552
84
139
COL<18>
11844
84
100
COL<57>
7652
84
140
COL<17>
11944
84
101
COL<56>
7752
84
141
COL<16>
12044
84
102
COL<55>
7852
84
142
COL<15>
12290
84
103
COL<54>
7952
84
143
COL<14>
12390
84
104
COL<53>
8052
84
144
COL<13>
12490
84
105
COL<52>
8152
84
145
COL<12>
12590
84
106
COL<51>
8252
84
146
COL<11>
12690
84
107
COL<50>
8352
84
147
COL<10>
12790
84
108
COL<49>
8452
84
148
COL<9>
12890
84
109
COL<48>
8552
84
149
COL<8>
12990
84
110
COL<47>
8798
84
150
COL<7>
13090
84
111
COL<46>
8898
84
151
COL<6>
13190
84
112
COL<45>
8998
84
152
COL<5>
13290
84
113
COL<44>
9098
84
153
COL<4>
13390
84
114
COL<43>
9198
84
154
COL<3>
13490
84
115
COL<42>
9298
84
155
COL<2>
13590
84
116
COL<41>
9398
84
156
COL<1>
13690
84
117
COL<40>
9498
84
157
COL<0>
13790
84
118
COL<39>
9598
84
158
ROW<33>
14204
84
119
COL<38>
9698
84
159
ROW<35>
14304
84
120
COL<37>
9798
84
160
ROW<37>
14404
84
1997 Nov 21
32
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
Pad
Pad name
X
PCF8549
Y
Pad
Pad name
X
Y
201
VDD2_HV_I 11145
N
2461
202
VDD2_HV_I 11045
N
2461
203
VDD2_HV_I 10945
N
2461
204
RES_B_IN
10627
2462
205
SDA_OUT
10333.5
5
2462
161
ROW<39>
14504
84
162
ROW<41>
14604
84
163
ROW<43>
14704
84
164
ROW<45>
14804
84
165
ROW<47>
14904
84
166
ROW<49>
15004
84
167
ROW<51>
15104
84
168
ROW<53>
15204
84
169
ROW<55>
15304
84
206
SDA_IN
9412.4
2462
170
ROW<57>
15404
84
207
SDA_IN
9212.4
2462
171
ROW<59>
15504
84
208
SCL_IN
8256.8
2462
172
ROW<61>
15604
84
209
SCL_IN
8056.8
2462
173
ROW<63>
15704
84
Recpat C1
16275
2437
174
Dummy 7
15804
84
Recpat C2
2301
80
175
Dummy 8
15904
84
Recpat F
304
1824
176
Dummy 9
16004
84
177
Dummy 12
15961
2437
178
Dummy 11
15861
2437
179
Dummy 10
15761
2437
180
ROW<31>
15661
2437
181
ROW<29>
15561
2437
182
ROW<27>
15461
2437
183
ROW<25>
15361
2437
184
ROW<23>
15261
2437
185
ROW<21>
15161
2437
186
ROW<19>
15061
2437
187
ROW<17>
14961
2437
188
ROW<15>
14861
2437
189
ROW<13>
14761
2437
190
ROW<11>
14661
2437
191
ROW<9>
14561
2437
192
ROW<7>
14461
2437
193
ROW<5>
14361
2437
194
ROW<3>
14261
2437
195
ROW<1>
14161
2437
196
OSC
13738
2462
197
VDD1
13147
2461
198
VDD1
13047
2461
199
VDD1
12947
2461
200
VDD2
12145
2461
1997 Nov 21
33
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1997 Nov 21
34
Philips Semiconductors
Product specification
65 × 102 pixels matrix LCD driver
PCF8549
NOTES
1997 Nov 21
35
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/01/pp36
Date of release: 1997 Nov 21
Document order number:
9397 750 03044