INTEGRATED CIRCUITS DATA SHEET PCF2104x LCD controller/driver Product specification Supersedes data of 1997 Apr 01 File under Integrated Circuits, IC12 1997 Dec 16 Philips Semiconductors Product specification LCD controller/driver PCF2104x CONTENTS 9.4 9.4.1 9.4.2 9.4.3 9.5 9.6 9.6.1 9.6.2 9.7 9.8 9.9 9.10 9.11 Display on/off control D C B Cursor/display shift Function set DL (parallel mode only) N, M Set CGRAM address Set DDRAM address Read busy flag and address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM 10 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) 11 INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 11.2 11.3 11.4 11.5 11.6 Characteristics of the I2C-bus Bit transfer Start and stop conditions System configuration Acknowledge I2C-bus protocol 12 LIMITING VALUES 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 3.1 3.2 Packages Available types 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 PIN FUNCTIONS 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 RS: register select (parallel control) R/W: read/write (parallel control) E: data bus clock (parallel control) DB0 to DB7: data bus (parallel control) C1 to C60: column driver outputs R1 to R32: row driver outputs VLCD: LCD power supply OSC: oscillator SCL: serial clock line SDA: serial data line SA0: address pin T1: test pad 8 FUNCTIONAL DESCRIPTION 13 HANDLING 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 14 DC CHARACTERISTICS 15 AC CHARACTERISTICS 16 TIMING DIAGRAMS 17 APPLICATION INFORMATION 17.1 17.3 17.4 17.5 8-bit operation, 2 × 12 display using internal reset 4-bit operation, 2 × 12 display using internal reset 8-bit operation, 2 × 24 display I2C operation, 2 × 12 display Initializing by instruction 18 BONDING PAD LOCATIONS 19 DEFINITIONS 20 LIFE SUPPORT APPLICATIONS 8.16 LCD bias voltage generator Oscillator External clock Power-on reset Registers Busy Flag Address Counter (AC) Display data RAM (DDRAM) Character generator ROM (CGROM) Character generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Programming of MUX 1 : 16 displays with PCF2104x Programming of MUX 1 : 32 displays with PCF2104x Reset function 21 PURCHASE OF PHILIPS I2C COMPONENTS 9 INSTRUCTIONS 9.1 9.2 9.3 9.3.1 9.3.2 Clear display Return home Entry mode set I/D S 8.15 1997 Dec 16 17.2 2 Philips Semiconductors Product specification LCD controller/driver 1 PCF2104x but does not contain the high voltage generator of that device. FEATURES • Single chip LCD controller/driver The PCF2104x is optimized for chip-on-glass applications. The ‘x’ in ‘PCF2104x’ represents a specific letter code for a character set in the character generator ROM (CGROM). • 1 or 2-line display of up to 24 characters per line, or 2 or 4 lines of up to 12 characters per line • 5 × 7 character format plus cursor; 5 × 8 for kana (Japanese syllabary) and user-defined symbols Two standard character sets are currently available, specified by the letters ‘C’ and ‘L’ (see Figs 5 and 6). Other character sets are available on request. • On-chip: – generation of intermediate LCD bias voltages The PCF2104x is a low-power CMOS LCD controller and driver, designed to drive a split screen dot matrix LCD display of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with a 5 × 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages which results in a minimum of external components and lower system power consumption. To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD. – oscillator requires no external components (external clock also possible) • Display data RAM: 80 characters • Character generator ROM: 240 characters • Character generator RAM: 16 characters • 4 or 8-bit parallel bus or 2-wire I2C-bus interface • CMOS/TTL compatible • 32 row, 60 column outputs • MUX rates 1 : 32 and 1 : 16 The chip contains a character generator and displays alphanumeric and kana characters. The PCF2104x interfaces to most microcontrollers via a 4 or 8-bit bus, or via the 2-wire I2C-bus. • Uses common 11 code instruction set • Logic supply voltage range, VDD − VSS: 2.5 to 6 V • Display supply voltage range, VDD − VLCD: 3.5 to 9 V • Low power consumption. 3.1 Packages • I2C-bus address: 011101 SA0. • PCF2104xU/2; chip with bumps in tray • PCF2104xU/7; chip with bumps on tape. 2 APPLICATIONS For further details see Chapter 18. • Telecom equipment 3.2 • Portable instruments • PCF2104CU/x: character set ‘C’ in CGROM • Point-of-sale terminals. 3 Available types • PCF2104LU/x: character set ‘L’ in CGROM • PCF2104NU/x: character set ‘N’ in CGROM. GENERAL DESCRIPTION The PCF2104x integrated circuit is similar to the PCF2114x (described in the “PCF2116 family” data sheet) 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCF2104CU/2 − chip with bumps in tray − PCF2104CU/7 − chip with bumps on tape − PCF2104LU/2 − chip with bumps in tray − PCF2104LU/7 − chip with bumps on tape − PCF2104NU/2 − chip with bumps in tray − PCF2104NU/7 − chip with bumps on tape − 1997 Dec 16 3 Philips Semiconductors Product specification LCD controller/driver 5 PCF2104x BLOCK DIAGRAM C1 to C60 handbook, full pagewidth R1 to R32 5-20 81-96 32 80-21 60 V LCD 111 BIAS VOLTAGE GENERATOR COLUMN DRIVERS ROW DRIVERS 60 6 32 SHIFT REGISTER 32-BIT DATA LATCHES 60 SHIFT REGISTER 5 x 12-bit 5 PCF2104x CURSOR + DATA CONTROL VDD V SS T1 5 2 CHARACTER GENERATOR RAM (CGRAM) 16 CHARACTERS 4 101 CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS OSCILLATOR 1 TIMING GENERATOR 8 DISPLAY DATA RAM (DDRAM) 80 CHARACTERS 7 7 DISPLAY ADDRESS COUNTER ADDRESS COUNTER (AC) 7 POWER - ON RESET INSTRUCTION DECODER 8 8 DATA REGISTER (DR) BUSY FLAG 8 INSTRUCTION REGISTER (IR) 7 8 I/O BUFFER 4 109-106 4 105-102 98 100 99 97 110 3 MGC627 DB0 to DB3 DB4 to DB7 E R/W RS Fig.1 Block diagram. 1997 Dec 16 4 SCL SDA SA0 OSC Philips Semiconductors Product specification LCD controller/driver 6 PCF2104x PINNING SYMBOL FFC PAD TYPE DESCRIPTION OSC 1 I oscillator/external clock input VDD 2 P logic supply voltage SA0 3 I I2C-bus address pin input VSS 4 P ground R8 to R5 5 to 8 O LCD row driver outputs R32 to R29 9 to12 O LCD row driver outputs R24 to R17 13 to 20 O LCD row driver outputs C60 to C1 21 to 80 O LCD column driver outputs R9 to R16 81 to 88 O LCD row driver outputs R25 to R28 89 to 92 O LCD row driver outputs R1 to R4 93 to 96 O LCD row driver outputs SCL 97 I I2C-bus serial clock input E 98 I data bus clock input RS 99 I register select input R/W 100 I read/write input T1 101 I test pad input DB7 to DB0 102 to 109 I/O 8-bit bidirectional data bus input/output SDA 110 I/O I2C-bus serial data input/output VLCD 111 I 7 7.1 PIN FUNCTIONS 7.4 R/W: read/write (parallel control) 7.5 R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when control is by the parallel interface. There is an internal pull-up on this pin. 7.3 DB0 to DB7: data bus (parallel control) The bidirectional, 3-state data bus transfers data between the system controller and the PCF2104x. DB7 may be used as the Busy Flag, signalling that internal operations are not yet completed. In 4-bit operations the 4 higher order lines DB4 to DB7 are used; DB0 to DB3 must be left open circuit. There is an internal pull-up on each of the data lines. Note that these pins must be left open circuit when I2C-bus control is used. RS: register select (parallel control) RS selects the register to be accessed for read and write when the device is controlled by the parallel interface. RS = logic 0 selects the instruction register for write and the Busy Flag and Address Counter for read. RS = logic 1 selects the data register for both read and write. There is an internal pull-up on pin RS. 7.2 LCD supply voltage input C1 to C60: column driver outputs These pins output the data for pairs of columns. This arrangement permits optimized chip-on-glass (COG) layout for 4-line by 12 characters. E: data bus clock (parallel control) 7.6 The E pin is set HIGH to signal the start of a read or write operation when the device is controlled by the parallel interface. Data is clocked in or out of the chip on the negative edge of the clock. Note that this pin must be tied to logic 0 (VSS) when I2C-bus control is used. R1 to R32: row driver outputs These pins output the row select waveforms to the left and right halves of the display. 7.7 VLCD: LCD power supply Negative power supply for the liquid crystal display. 1997 Dec 16 5 Philips Semiconductors Product specification LCD controller/driver 7.8 PCF2104x OSC: oscillator 8.2 Oscillator When the on-chip oscillator is used, this pin must be connected to VDD. An external clock signal, if used, is input at this pin. The on-chip oscillator provides the clock signal for the display system. No external components are required. Pin OSC must be connected to VDD. 7.9 8.3 SCL: serial clock line Input for the I2C-bus clock signal. 7.10 If an external clock is to be used, it must be input at pin OSC. The resulting display frame frequency is given by fframe = 1⁄2304fosc. A clock signal must always be present, otherwise the LCD may be frozen in a DC state. SDA: serial data line Input/output for the I2C-bus data line. 7.11 8.4 SA0: address pin 8.5 The instruction register stores instruction codes such as display clear and cursor shift, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written to, but not read from, by the system controller. FUNCTIONAL DESCRIPTION (see Fig.1) 8.1 LCD bias voltage generator The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system power consumption. The optimum levels depend on the multiplex rate and are selected automatically when the number of lines in the display is defined. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM (corresponding to the address in the Address Counter) is written to the data register prior to being read by the ‘Read data’ instruction. The optimum value of VOP depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels. The relationships are given in Table 1. 8.6 Optimum values for VOP MUX RATE NUMBER OF BIAS LEVELS VOP/Vth DISCRIMINATION Von/Voff 1 : 16 5 3.67 1.277 1 : 32 6 5.19 1.196 1997 Dec 16 Busy Flag The Busy Flag indicates the free/busy status of the PCF2104x. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The Busy Flag is output at pin DB7 when RS = logic 0 and R/W = logic 1. Instructions should only be written after checking that the Busy Flag is at logic 0 or waiting for the required number of clock cycles. Using a 5-level bias scheme for 1 : 16 MUX rate allows VOP < 5 V for most LCD liquids. The effect on the display contrast is negligible. Table 1 Registers The PCF2104x has two 8-bit registers, an instruction register (IR) and a data register (DR). The register select signal (RS) determines which register will be accessed. T1: test pad Must be connected to VSS. Not user accessible. 8 Power-on reset The Power-on reset block initializes the chip after power-on or power failure. The hardware sub-address line is used to program the device sub-address for 2 different PCF2104xs on the same I2C-bus. 7.12 External clock 6 Philips Semiconductors Product specification LCD controller/driver 8.7 PCF2104x 8.10 Address Counter (AC) Up to 16 user-defined characters may be stored in the character generator RAM. The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.5). Figure 8 shows the addressing principle for the CGRAM. The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions ‘Set CGRAM address’ and ‘Set DDRAM address’. After a read/write operation the Address Counter is automatically incremented or decremented by 1. The Address Counter contents are output to the bus (DB0 to DB6) when RS = logic 0 and R/W = logic 1. 8.8 8.11 Display data RAM (DDRAM) 8.12 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.13 LCD row and column drivers The PCF2104x contains 32 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display, in accordance with the data to be displayed. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 10 and 11 show typical waveforms. The address range for a 1-line display is 00 to 4F; for a 2-line display from 00 to 27 (line 1) and 40 to 67 (line 2); for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and 60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and 4-line displays the end address of one line and the start address of the next line are not consecutive. When the display is shifted each line wraps around independently of the others (see Figs 3 and 4). In the 1-line mode (1 : 16) the row outputs are driven in pairs: R1/R17, R2/R18 for example. This allows the output pairs to be connected in parallel, thereby providing greater drive capability. When data is written to the DDRAM wrap-around occurs from 4F to 00 in 1-line mode and from 27 to 40 and 67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60 and 73 to 00 in 4-line mode. Unused outputs should be left unconnected. Character generator ROM (CGROM) The character generator ROM generates 240 character patterns in 5 × 8 dot format from 8-bit character codes. Figures 5 and 6 show the character sets currently available. 1997 Dec 16 Cursor control circuit The cursor control circuit generates the cursor (underline and/or character blink as shown in Fig.9) at the DDRAM address contained in the Address Counter. When the Address Counter contains the CGRAM address the cursor will be inhibited. The DDRAM stores up to 80 characters of display data, represented by 8-bit character codes. DDRAM locations not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping scheme is shown in Fig.2. With no display shift, the characters represented by the codes in the first 12 or 24 RAM locations, starting at address 00 in line 1, are displayed. Subsequent lines display data starting at addresses 20, 40, or 60 Hex. Figures 3 and 4 show the DDRAM-to-display mapping scheme when the display is shifted. 8.9 Character generator RAM (CGRAM) 7 Philips Semiconductors Product specification LCD controller/driver Display handbook, 4 columns Position (decimal) 1 PCF2104x 2 3 4 5 22 23 24 00 01 02 03 04 DDRAM Address (hex) non-displayed DDRAM addresses 15 16 17 18 19 4C 4D 4E 4F 1-line display non-displayed DDRAM address DDRAM Address (hex) 00 01 02 03 04 15 16 17 18 19 24 25 26 27 line 1 40 41 42 43 44 55 56 57 58 59 64 65 66 67 line 2 MLA792 2-line display non-displayed DDRAM addresses handbook, 4 columns 1 2 3 4 5 6 7 8 9 10 11 12 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 line 1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 line 2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 line 3 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 line 4 DDRAM Address (hex) 4 line display MLA793 Fig.2 DDRAM-to-display mapping; no shift (PCF2104x). 1997 Dec 16 8 Philips Semiconductors Product specification LCD controller/driver Display Position (decimal) DDRAM Address (hex) 1 2 3 4 5 22 23 24 4F 00 01 02 03 14 15 16 Display Position (decimal) DDRAM Address (hex) 1-line display 14 15 16 27 00 01 02 03 DDRAM Address (hex) PCF2104x 67 40 41 42 43 54 55 56 DDRAM Address (hex) line 2 8 9 10 11 12 22 23 24 16 17 18 4 1-line display 01 02 03 04 05 16 17 18 line 1 41 42 43 44 45 56 57 58 line 2 1 2 MLA815 3 4 5 6 7 8 9 10 11 12 13 00 01 02 03 04 05 06 07 08 09 0A line 1 01 02 03 04 05 06 07 08 09 0A 0B 0C line 1 33 20 21 22 23 24 25 26 27 28 29 2A line 2 21 22 23 24 25 26 27 28 29 2A 2B 2C line 2 DDRAM Address (hex) Address (hex) 53 40 41 42 43 44 45 46 47 48 49 4A line 3 41 42 43 44 45 46 47 48 49 4A 4B 4C line 3 73 60 61 62 63 64 65 66 67 68 69 6A line 4 61 62 63 64 65 66 67 68 69 6A 6B 6C line 4 4-line display MLA803 4-line display DDRAM-to-display mapping; right shift (PCF2104x). 1997 Dec 16 2 3 2-line display DDRAM Fig.3 5 01 02 03 04 05 MLA802 2-line display 1 2 3 4 5 6 7 line 1 1 Fig.4 9 MLA816 DDRAM-to-display mapping; left shift (PCF2104x). Philips Semiconductors Product specification LCD controller/driver PCF2104x handbook, full pagewidth upper 4 bits 0000 xxxx 0000 CG RAM 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 4 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MLB895 Fig.5 Character set ‘C’ in CGROM; PCF2104C. 1997 Dec 16 10 Philips Semiconductors Product specification LCD controller/driver PCF2104x handbook, full pagewidth upper 4 bits 0000 xxxx 0000 CG RAM 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 6 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MGC629 Fig.6 Character set ‘L’ in CGROM; PCF2104L. 1997 Dec 16 11 Philips Semiconductors Product specification LCD controller/driver PCF2104x handbook, full pagewidth upper 4 bits 0000 xxxx 0000 CG RAM 1 xxxx 0001 2 xxxx 0010 3 xxxx 0011 4 xxxx 0100 5 xxxx 0101 6 xxxx 0110 7 xxxx 0111 8 xxxx 1000 9 xxxx 1001 10 xxxx 1010 11 xxxx 1011 12 xxxx 1100 13 xxxx 1101 14 xxxx 1110 15 xxxx 1111 16 lower 4 bits 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MGM134 Fig.7 Character set ‘N’ in CGROM; PCF2104N. 1997 Dec 16 12 Philips Semiconductors Product specification LCD controller/driver character codes (DDRAM data) handbook, full pagewidth 7 6 5 4 3 2 higher order bits 0 0 PCF2104x 0 0 0 0 CGRAM address 1 0 6 lower order bits 0 0 0 0 0 0 0 0 5 4 3 2 higher order bits 0 1 0 0 0 0 0 0 character patterns (CGRAM data) 1 0 lower order bits 0 1 4 3 higher order bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 2 1 0 lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cursor position 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 1 character pattern example 2 MGA800 - 1 Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4; bit 4 being at the left end, as shown in the figure. CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the ‘Set CGRAM address’ instruction. Bit 6 can be set using the ‘Set DDRAM address’ instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read Busy Flag and address’ instruction. Fig.8 Relationship between CGRAM addresses, data and display patterns. 1997 Dec 16 13 Philips Semiconductors Product specification LCD controller/driver PCF2104x cursor MGA801 5 x 7 dot character font alternating display cursor display example blink display example Fig.9 Cursor and blink display examples. 1997 Dec 16 14 Philips Semiconductors Product specification LCD controller/driver PCF2104x frame n handbook, full pagewidth frame n 1 state 1 (ON) state 2 (ON) VDD V2 V3 /V4 V5 V LCD ROW 1 VDD V2 ROW 9 V3 /V4 V5 V LCD 1-line display (1:16) VDD V2 V3 /V4 V5 V LCD ROW 2 VDD V2 V3 /V4 V5 V LCD COL 1 VDD V2 V3 /V4 V5 V LCD COL 2 VOP 0.25 VOP state 1 0 V 0.25 VOP VOP VOP 0.25 VOP state 2 0 V 0.25 VOP VOP MGA802 - 1 1 2 3 16 1 2 3 Fig.10 Typical LCD waveforms; 1-line mode. 1997 Dec 16 15 16 Philips Semiconductors Product specification LCD controller/driver PCF2104x frame n 1 frame n handbook, full pagewidth ROW 1 V DD V2 V3 V4 V5 V LCD ROW 9 V DD V2 V3 V4 V5 V LCD ROW 2 V DD V2 V3 V4 V5 V LCD COL 1 V DD V2 V3 V4 V5 V LCD COL 2 V DD V2 V3 V4 V5 V LCD state 1 (ON) state 2 (ON) 2-line display (1:32) VOP state 1 0.15 VOP 0V 0.15 VOP VOP VOP state 2 0.15 VOP 0V 0.15 VOP VOP MGA803 - 1 123 32 1 2 3 32 Fig.11 Typical LCD waveforms; 2-line mode. 1997 Dec 16 16 Philips Semiconductors Product specification LCD controller/driver 8.14 PCF2104x Using the ‘Function set’ instruction, M and N are set to 0, 0 (respectively). Figures 12, 13 and 14 show the DDRAM addresses of the display characters. The second row of each table corresponds to either the right half of a 1-line display or to the second line of a 2-line display. Wrap around of data during display shift or when writing data is non-standard. Programming of MUX 1 : 16 displays with PCF2104x The PCF2104x can be used in the following ways: • 1-line mode to drive a 2-line display • 2 × 12 characters with MUX rate 1 : 16, resulting in better contrast. The internal data flow of the chip is optimized for this purpose. handbook, full pagewidth display position 1 2 3 4 5 6 7 8 9 10 11 12 DDRAM address 00 01 02 03 04 05 06 07 08 09 0A 0B 24 display position 13 14 15 16 17 18 19 20 21 22 23 DDRAM address 0C 0D 0E 0F 10 11 12 13 14 15 16 17 MLB899 Fig.12 DDRAM-to-display mapping; no shift (PCF2104x). handbook, full pagewidth display position DDRAM address 1 2 3 4 5 6 7 8 9 10 11 12 4F 00 01 02 03 04 05 06 07 08 09 0A display position 13 14 15 16 17 18 19 20 21 22 23 24 DDRAM address 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 MLB900 Fig.13 DDRAM-to-display mapping; right shift (PCF2104x). handbook, full pagewidth display position 1 2 3 4 5 6 7 8 9 10 11 12 DDRAM address 01 02 03 04 05 06 07 08 09 0A 0B 0C display position 13 14 15 16 17 18 19 20 21 22 23 24 DDRAM address 0D 0E 0F 10 11 12 13 14 15 16 17 18 MLB901 Fig.14 DDRAM-to-display mapping; left shift (PCF2104x). 1997 Dec 16 17 Philips Semiconductors Product specification LCD controller/driver 8.15 PCF2104x Programming of MUX 1 : 32 displays with PCF2104x 9 Only two PCF2104x registers, the instruction register (IR) and the data register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF2104x operation is controlled by the instructions shown in Table 3 together with their execution time. Details are explained in subsequent sections. To drive a 2-line by 24 characters MUX 1 : 32 display, use instruction ‘Function set’ to set M, N to 0, 1 (respectively). To drive a 4-line by 12 characters MUX 1:32 display, use instruction ‘Function set’ to set M, N to 1, 1 (respectively). 8.16 Reset function The PCF2104 automatically initializes (resets) when power is turned on. The state after reset is given in Table 2. Table 2 Instructions are of 4 categories, those that: 1. Designate PCF2104x functions such as display format, data length, etc. State after reset STEP INSTRUCTIONS DESCRIPTION 2. Set internal RAM addresses 1 Display clear. 3. Perform data transfer with internal RAM 2 Function set: 4. Others. DL = 1: 8-bit interface In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, thus enabling the designer to develop systems in minimum time with maximum programming efficiency. M, N = 0 1-line display G = 0: not used 3 Display on/off control: D = 0: display off C = 0: cursor off; B = 0: blink off; 4 Entry mode set: During internal operation, no instruction other than the Busy Flag/address read instruction will be executed. I/D = 1: +1 (increment) G = 0: not used 5 Default address pointer to DDRAM. The Busy Flag (BF) indicates the busy state (BF = logic 1) until initialization ends. The busy state lasts 2 ms. The chip may also be initialized by software. See Tables 10 and 11. 6 I2C-bus interface reset. 1997 Dec 16 Because the Busy Flag is set to logic 1 while an instruction is being executed, it is advisable to ensure that the flag it is at logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 3. An instruction sent while the Busy Flag is HIGH will not be executed. 18 INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTION REQUIRED CLOCK CYCLES(2) 0 0 0 0 0 0 0 0 0 0 No operation. Clear display 0 0 0 0 0 0 0 0 0 1 Clears entire display and sets DDRAM address 0 in Address Counter. Return home 0 0 0 0 0 0 0 0 1 0 Sets DDRAM address 0 in Address Counter Also returns shifted display to original position DDRAM contents remain unchanged. 3 Entry mode set 0 0 0 0 0 0 0 1 I/D S Sets cursor move direction and specifies shift of display. These operations are performed during data write and read. 3 Display control 0 0 0 0 0 0 1 D C B Sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B). 3 Cursor/display shift 0 0 0 0 0 1 S/C R/L 0 0 Moves cursor and shifts display without changing DDRAM contents. 3 Function set 0 0 0 0 1 DL N M G 0 Sets interface data length (DL), number of display lines (N, M) and voltage generator control (G). 3 Set CGRAM address 0 0 0 1 Sets CGRAM address. 3 Set DDRAM address 0 0 1 ADD Sets DDRAM address. 3 Read busy flag and address 0 1 BF AC Reads Busy Flag (BF) indicating internal operation is being performed and reads Address Counter contents. 0 19 NOP ACG 0 165 Read data 1 1 read data Reads data from CGRAM or DDRAM. 3 Write data 1 0 write data Writes data to CGRAM or DDRAM. 3 Philips Semiconductors Instructions (note 1) LCD controller/driver 1997 Dec 16 Table 3 Notes 1 2. Example: fosc = 150 kHz, T cy = --------- = 6.67 µs; 3 cycles = 20 µs, 165 cycles = 1.1 ms. f osc Product specification In the I2C-bus mode a control byte is required when RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0. PCF2104x 1. In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed. Philips Semiconductors Product specification LCD controller/driver Table 4 PCF2104x Command bit identities BIT LOGIC 0 LOGIC 1 I/D decrement increment S display freeze display shift D display off display on C cursor off cursor on B character at cursor position does not blink character at cursor position blinks S/C cursor move display shift R/L left shift right shift DL 4 bits 8 bits N (M = 0) 2 line × 12 characters; MUX 1 : 16 2 lines × 24 characters; MUX 1 : 32 N (M = 1) reserved 4 lines × 12 characters; MUX 1 : 32 BF end of internal operation internal operation in progress Co last control byte, only data bytes to follow next two bytes are a data byte and another control byte RS R/W E DB7 IR7 IR3 BF AC3 DR7 DR3 DB6 IR6 IR2 AC6 AC2 DR6 DR2 DB5 IR5 IR1 AC5 AC1 DR5 DR1 DB4 IR4 IR0 AC4 AC0 DR4 DR0 instruction write busy flag and address counter read Fig.15 4-bit transfer example. 1997 Dec 16 20 data register read MGA804 Philips Semiconductors Product specification LCD controller/driver PCF2104x RS R/W E internal internal operation DB7 IR7 IR3 busy instruction write not busy AC3 busy flag check AC3 D7 busy flag check D3 instruction write MGA805 IR7, IR3: instruction 7th bit, 3rd bit. AC3: Address Counter 3rd bit. Fig.16 An example of 4-bit data transfer timing sequence. RS R/W E internal DB7 internal operation data instruction write busy busy flag check busy busy flag check not busy busy flag check Fig.17 Example of Busy Flag check timing sequence. 1997 Dec 16 21 data instruction write MGA806 Philips Semiconductors Product specification LCD controller/driver 9.1 PCF2104x 9.4.2 Clear display C The cursor is displayed when C = logic 1 and inhibited when C = logic 0. Even if the cursor disappears, the display functions I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.9). ‘Clear display’ writes space code 20 (hexadecimal) into all DDRAM addresses (the character pattern for character code 20 must be a blank pattern), sets the DDRAM Address Counter to logic 0 and returns the display to its original position if it was shifted. Consequently, the display disappears and the cursor or blink position goes to the left edge of the display (the first line if 2 or 4 lines are displayed) and sets the entry mode to I/D = logic 1 (increment mode). S of entry mode does not change. 9.4.3 B The instruction ‘Clear display’ requires extra execution time. This may be allowed for by checking the Busy Flag (BF) or by waiting until 2 ms has elapsed. The latter must be applied where no read-back options are foreseen, as in some chip-on-glass (COG) applications. The character indicated by the cursor blinks when B = logic 1. The blink is displayed by switching between display characters and all dots on with a period of 1 second when fosc = 150 kHz (see Fig.9). At other clock frequencies the blink period is equal to 150 kHz/fosc. The cursor and the blink can be set to display simultaneously. 9.2 9.5 Return home ‘Return home’ sets the DDRAM Address Counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the display (the first line if 2 or 4 lines are displayed). I/D and S of entry mode do not change. 9.3 9.3.1 ‘Cursor/display shift’ moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2 or 4-line displays, the cursor moves to the next line when it passes the last position of the line (40 or 20 decimal). When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift. Entry mode set I/D When I/D = logic 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written to or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor and blink are inhibited when the CGRAM is accessed. 9.3.2 9.6 9.6.1 S DL (PARALLEL MODE ONLY) Function set from I2C-bus interface: DL bit can not bet set to logic 0 from the I2C-bus interface. If bit DL has been set to logic 0 via the parallel bus, programming via the I2C-bus interface is complicated. 9.6.2 9.4.1 Function set Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = logic 1 or in two nibbles (DB7 to DB4) when DL = logic 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus(1). When S = logic 1, the entire display shifts either to the right (I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM write. Consequently, it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = logic 0 the display does not shift. 9.4 Cursor/display shift Display on/off control N, M Sets number of display lines. D (1) In a 4-bit application DB3 to DB0 are left open (internal pull-ups). Hence in the first function set instruction after power-on G and H are set to 1. A second function set must then be sent (2 nibbles) to set G and H to their required values. The display is on when D = logic 1 and off when D = logic 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D to logic 1. 1997 Dec 16 22 Philips Semiconductors Product specification LCD controller/driver 9.7 PCF2104x Set CGRAM address 9.11 ‘Set CGRAM address’ sets bits 0 to 5 of the CGRAM address (ACG in Table 3) into the Address Counter (binary A[5] to A[0]). Data can then be written to or read from the CGRAM. Reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM. The most recent ‘Set address’ instruction determines whether the CGRAM or DDRAM is to be read. Only bits 0 to 5 of the CGRAM address are set by the ‘Set CGRAM address’ instruction. Bit 6 can be set using the ‘Set DDRAM address’ instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘Read busy flag and address’ instruction. 9.8 The ‘Read data’ instruction gates the content of the data register (DR) to the bus while E = HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. Remark: the only three instructions that update the data register (DR) are: Set DDRAM address • ‘Set CGRAM address’ Set DDRAM address sets the DDRAM address (ADD in Table 3) into the Address Counter (binary A[6] to A[0). Data can then be written to or read from the DDRAM. Table 5 • ‘Set DDRAM address’ • ‘Read data’ from CGRAM or DDRAM. Other instructions (e.g. ‘Write data, ‘Cursor/display shift’, ‘Clear display’, ‘Return home’) will not modify the data register content. Hexadecimal address ranges ADDRESS FUNCTION 00 to 4F 1-line by 24 00 to 0B and 0C to 4F 2-line by 12 00 to 27 and 40 to 67 2-line by 24 10 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) 00 to 13, 20 to 33, 40 to 53 4-line by 12 and 60 to 73 9.9 The PCF2104x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. Read busy flag and address In the 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB0 to DB7. Three further control lines E, RS, and R/W are required. ‘Read busy flag and address’ reads the Busy Flag (BF). When BF = logic 1 it indicates that an internal operation is in progress. The next instruction will not be executed until BF = logic 0, so BF should be checked before sending another instruction. In the 4-bit mode data is transferred in two cycles of 4-bits each. The higher order bits (corresponding to DB4 to DB7 in 8-bit mode) are sent in the first cycle and the lower order bits (DB0 to DB3 in 8-bit mode) in the second cycle. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the Busy Flag check. 4-bit operation is selected by instruction. See Figs 15, 16 and 17 for examples of bus protocol. At the same time, the value of the Address Counter expressed in binary A[6] to A[0] is read out. The Address Counter is used by both CGRAM and DDRAM and its value is determined by the previous instruction. 9.10 Write data to CGRAM or DDRAM In the 4-bit mode pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally. Writes binary 8-bit data D[7] to D[0] to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written to is determined by the previous specification of CGRAM or DDRAM address setting. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D0 to D4 of CGRAM data are valid, bits D5 to D7 are ‘don't care’. 1997 Dec 16 Read data from CGRAM or DDRAM 23 Philips Semiconductors Product specification LCD controller/driver PCF2104x 11.5 11 INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 Characteristics of the The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 11.2 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 11.3 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). 11.4 Acknowledge 11.6 I2C-bus protocol Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2104x READ and WRITE cycles is illustrated in Figs 22, 23 and 24. System configuration A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed Fig.18 Bit transfer. 1997 Dec 16 24 MBC621 Philips Semiconductors Product specification LCD controller/driver PCF2104x handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig.19 Definition of START and STOP conditions. MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL MGA807 Fig.20 System configuration. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.21 Acknowledgement on the 1997 Dec 16 25 I2C-bus. Philips Semiconductors LCD controller/driver 1997 Dec 16 acknowledgement from PCF2104x S S 0 1 1 1 0 1 A 0 A 1 CONTROL BYTE A A 0 DATA CONTROL BYTE A DATA 0 slave address 2n 0 bytes 1 byte Co Co n 0 bytes update data pointer S 0 1 1 1 0 1 A 0 0 MGC617 PCF2104x slave address R/W Product specification Fig.22 Master transmits to slave receiver; WRITE mode. PCF2104x handbook, full pagewidth 26 R/W A P S S 0 1 1 1 0 1 A 0 A 1 CONTROL BYTE A DATA A 0 1 1 CONTROL DATA A (1) Philips Semiconductors LCD controller/driver 1997 Dec 16 acknowledgement from PCF2104x A 0 slave address 2n R/W 0 bytes 2 bytes Co Co 27 acknowledgement from PCF2104x S SLAVE ADDRESS S A 1 A 0 no acknowledgement from master DATA n bytes A DATA 1 P last byte R/W MGC618 Product specification Fig.23 Master reads after setting word address; write word address, set RS/RW; READ data. PCF2104x (1) Last data byte is a dummy byte (may be omitted). handbook, full pagewidth update data pointer Philips Semiconductors Product specification LCD controller/driver PCF2104x acknowledgement from PCF2104x handbook, full pagewidth S SLAVE ADDRESS S A 1 A 0 acknowledgement from master DATA n bytes A no acknowledgement from master DATA 1 P last byte R/W update data pointer MGC619 Fig.24 Master reads slave immediately after first byte; READ mode (RS previously defined). 1997 Dec 16 28 START CONDITION (S) BIT 7 MSB (A7) BIT 6 (A6) BIT 0 LSB R/W ACKNOWLEDGE (A) Philips Semiconductors LCD controller/driver 1997 Dec 16 PROTOCOL STOP CONDITION (P) SDA 29 t BUF t LOW tr SCL t HD;STA tf t SU;STO t/fSCL Product specification Fig.25 I2C-bus timing diagram; rise and fall times refer to VIL and VIH. MGA811 - 1 PCF2104x handbook, full pagewidth t HIGH Philips Semiconductors Product specification LCD controller/driver PCF2104x 12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +8.0 V VLCD LCD supply voltage VDD − 11 VDD V VI input voltage OSC, RS, R/W, E and DB0 to DB7 VSS − 0.5 VDD + 0.5 V VO output voltage R1 to R32, C1 to C60 and VLCD VLCD − 0.5 VDD + 0.5 V II DC input current −10 +10 mA IO DC output current −10 +10 mA IDD, ISS, ILCD VDD, VSS or VLCD current −50 +50 mA Ptot total power dissipation − 400 mW PO power dissipation per output − 100 mW Tstg storage temperature −65 +150 °C 13 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ). 14 DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD − 3.5 to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD supply voltage 2.5 − 6.0 V VLCD LCD supply voltage VDD − 9 − VDD − 3.5 V IDD supply current external VLCD note 1 − − − IDD1 supply current 1 − 200 500 µA IDD2 supply current 2 VDD = 5 V; VOP = 9 V; fosc = 150 kHz; Tamb = 25 °C − 200 300 µA IDD3 supply current 3 VDD = 3 V; VOP = 5 V; fosc = 150 kHz; Tamb = 25 °C − 150 200 µA ILCD VLCD input current notes 1 and 6 − 50 100 µA VPOR Power-on reset voltage level note 2 − 1.3 1.8 V 1997 Dec 16 30 Philips Semiconductors Product specification LCD controller/driver SYMBOL PARAMETER PCF2104x CONDITIONS MIN. TYP. MAX. UNIT Logic VIL1 LOW level input voltage pins E, RS, R/W, DB0 to DB7 and SA0 VSS − 0.3VDD V VIH1 HIGH level input voltage pins E, RS, R/W, DB0 to DB7 and SA0 0.7VDD − VDD V VIL(osc) LOW level input voltage pin OSC VSS − VDD − 1.5 V VIH(osc) HIGH level input voltage pin OSC VDD − 0.1 − VDD V Ipu pull-up current at pins DB0 to DB7, RS and R/W VI = VSS 0.04 0.15 1.00 µA IOL(DB) LOW level output current pins DB0 to DB7 VOL = 0.4 V; VDD = 5 V 1.6 − − mA IOH(DB) HIGH level output current pins DB0 to DB7 VOH = 4 V; VDD = 5 V −1.0 − − mA IL1 leakage current pins OSC, E, RS, R/W, DB0 to DB7 and SA0 VI = VDD or VSS −1 − +1 µA VIL2 LOW level input voltage note 3 VSS − 0.3VDD V VIH2 HIGH level input voltage note 3 0.7VDD − VDD V I2C-bus SDA, SCL IL2 leakage current VI = VDD or VSS −1 − +1 µA Ci input capacitance note 4 − − 7 pF IOL(SDA) LOW level output current (SDA) VOL = 0.4 V; VDD = 5 V 3 − − mA RROW row output resistance pins R1 to R32 note 5 − 1.5 3 kΩ RCOL column output resistance pins C1 to C60 note 5 − 3 6 kΩ Vtol1 bias voltage tolerance pins R1 to R32 and C1 to C60 note 6 − ±20 ±130 mV LCD outputs Notes 1. LCD outputs are open-circuit; inputs at VDD or VSS; V0 = VDD; bus inactive; internal or external clock with duty cycle 50% (IDD1 only). 2. Resets all logic when VDD < VPOR. 3. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current must not exceed ±0.5 mA. 4. Tested on sample basis. 5. Resistance of output terminals (R1 to R32 and C1 to C60) with load current Iload = 150 µA; VOP = VDD − VLCD = 9 V; outputs measured one at a time. 6. LCD outputs open-circuit. 1997 Dec 16 31 Philips Semiconductors Product specification LCD controller/driver PCF2104x 15 AC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 °C to + 85 °C; unless otherwise specified. SYMBOL PARAMETER fFR LCD frame frequency (internal clock) fosc external clock frequency CONDITIONS note 1 MIN. TYP. MAX. UNIT 40 65 100 Hz 90 150 225 kHz Bus timing characteristics: Parallel Interface; notes 1 and 2 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2104X) Tcy enable cycle time 500 − − ns PWEH enable pulse width 220 − − ns tASU address set-up time 50 − − ns tAH address hold time 25 − − ns tDSW data set-up time 60 − − ns tHD data hold time 25 − − ns READ OPERATION (READING DATA FROM PCF2104X TO MICROCONTROLLER) Tcy enable cycle time 500 − − ns PWEH enable pulse width 220 − − ns tASU address set-up time 50 − − ns tAH address hold time 25 − − ns tDHD data delay time − − 150 ns tHD data hold time 20 − 100 ns − 100 kHz Timing characteristics: I2C-bus interface; note 2 fSCL SCL clock frequency − tSW tolerable spike width on bus − − 100 ns tBUF bus free time 4.7 − − µs tSU;STA set-up time for a repeated START condition 4.7 − − µs tHD;STA start condition hold time 4 − − µs tLOW SCL LOW time 4.7 − − µs tHIGH SCL HIGH time 4 − − µs tr SCL and SDA rise time − − 1 µs tf SCL and SDA fall time − − 0.3 µs tSU;DAT data set-up time 250 − − ns tHD;DAT data hold time 0 − − ns tSU;STO set-up time for STOP condition 4 − − µs Notes 1. VDD = 5.0 V. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 1997 Dec 16 32 Philips Semiconductors Product specification LCD controller/driver PCF2104x 16 TIMING DIAGRAMS handbook, full pagewidth RS VIH1 V IL1 VIH1 VIL1 t AS R/W t AH V IL1 VIL1 t AH PW EH VIH1 VIL1 VIH1 VIL1 E VIL1 tH t DSW VIH1 Valid Data VIL1 DB0 to DB7 VIH1 VIL1 MLA798 - 1 Tcy Fig.26 Parallel bus write operation sequence; writing data from microcontroller to PCF2104x. handbook, full pagewidth RS VIH1 V IL1 VIH1 VIL1 t AS R/W t AH VIH1 VIH1 t AH PW EH E VIL1 VIH1 VIH1 VIL1 t DHR t DDR DB0 to DB7 VIL1 VOH1 VOL1 VOH1 VOL1 Tcy MLA799 - 1 Fig.27 Parallel bus read operation sequence; reading data from PCF2104x to microcontroller. 1997 Dec 16 33 Philips Semiconductors Product specification LCD controller/driver PCF2104x 17 APPLICATION INFORMATION handbook, 4 columns P20 RS P21 R/W P22 E 32 P80CL51 R1 to R32 to LCD PCF2104x 60 P10 to P17 C1 to C60 DB0 to DB7 8 MGC620 Fig.28 Direct connection to 8-bit microcontroller; 8-bit bus. handbook, 4 columns P10 RS P11 R/W P12 E 32 P80CL51 R1 to R32 to LCD PCF2104x 60 P14 to P17 C1 to C60 DB4 to DB7 4 MGC621 Fig.29 Direct connection to 8-bit microcontroller; 4-bit bus. handbook, full pagewidth VLCD R7 to R16 R25 to R32 VLCD 16 100 nF VDD 100 nF VSS VDD R1 to R8 R17 to R24 OSC 16 PCF2104x C1 to C60 V SS DB0 to DB7 E 2 x 24 CHARACTER LCD DISPLAY (SPLIT SCREEN) 60 60 MGC624 RS R/W Fig.30 Typical application using parallel interface. 1997 Dec 16 34 Philips Semiconductors Product specification LCD controller/driver handbook, full pagewidth PCF2104x VLCD VLCD R1 to R16 16 R17 to R24 2 x 24 CHARACTER LCD DISPLAY (SPLIT SCREEN) 100 nF VDD VDD OSC 100 nF 16 PCF2104x VDD VDD C1 to C60 V SS V SS 60 60 SA0 VDD VLCD VLCD 100 nF VDD VDD 100 nF V SS R1 to R16 OSC 16 PCF2104x SA0 MASTER TRANSMITTER PCF84C81 Fig.31 Application using I2C-bus interface. 1997 Dec 16 60 C1 to C60 V SS VSS SCL SDA 2 x 12 CHARACTER LCD DISPLAY 35 MGC625 Philips Semiconductors Product specification LCD controller/driver 17.1 PCF2104x 8-bit operation, 2 × 12 display using internal reset 17.3 For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the eighth character is completed (see Table 8). It should be noted that both lines of the display are always shifted together, data does not shift from one line to the other. Table 7 shows an example of a 1-line display in 8-bit operation. The PCF2104x functions must be set by the function set instruction prior to display. Since the display data RAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes the display position only and DDRAM contents remain unchanged. Display data entered first can be displayed when the ‘Return home’ instruction is performed. 17.2 17.4 I2C operation, 2 × 12 display A control byte is required with most instructions (see Table 9). 4-bit operation, 2 × 12 display using internal reset 17.5 Initializing by instruction If the power supply conditions for correctly operating the internal reset circuit are not met, the PCF2104x must be initialized by instruction. Tables 10 and 11 show how this may be performed for 8-bit and 4-bit operation. The program must set functions prior to 4-bit operation. Table 6 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2104x attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 6 step 3). Thus, DB4 to DB7 of the function set are written twice. 1997 Dec 16 8-bit operation, 2 × 24 display 36 Philips Semiconductors Product specification LCD controller/driver Table 6 PCF2104x 4-bit operation, 1-line display example; using internal reset STEP INSTRUCTION 1 Power supply on (PCF2104x is initialized by the internal reset circuit). 2 Function set: DISPLAY Initialized. No display appears. RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0 3 4 5 Sets to 4-bit operation. In this instance operation is handled as 8-bits by initialization and only this instruction completes with one write. Function set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0 Sets to 4-bit operation, selects 2 × 12 display. RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 4-bit operation starts from this point and resetting is needed. Display on/off control: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 Turns on display and cursor. RS = 0; R/W = 0; DB7 = 1; DB6 = 1; DB5 = 1; DB4 = 0 Entire display is blank after initialization. Entry mode set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 _ Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM. RS = 0; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 1; DB4 = 0 6 OPERATION Display is not shifted. Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1 P_ Writes ‘P’. The DDRAM has already been selected by initialization at power-on. RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 1; DB4 = 0 1997 Dec 16 The cursor is incremented by 1 and shifted to the right. 37 INSTRUCTION DISPLAY OPERATION Power supply on (PCF2104x is initialized by the internal reset function). Initialized. No display appears. 2 Function set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 Sets to 8-bit operation, selects 2 × 12 display. 3 Display mode on/off control: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 0 _ Turns on display and cursor. Entire display is blank after initialization. 4 Entry mode set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 0 _ Sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM. Display is not shifted. 5 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 P_ Writes ‘P’. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. 6 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 1; DB4 = 1; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0 PH_ Writes ‘H’. 38 1 | | | 7 PHILIPS_ Writes ‘S’. 9 Entry mode set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 1 PHILIPS_ Sets mode for display shift at the time of write. 10 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 HILIPS _ Writes space. 11 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1 ILIPS Writes ‘M’. M_ | | | Product specification Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1 PCF2104x 8 12 Philips Semiconductors STEP 8-bit operation, 1-line display example; using internal reset (character set ‘A’) LCD controller/driver 1997 Dec 16 Table 7 DISPLAY OPERATION 39 13 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 1 MICROKO Writes ‘O’. 14 Cursor or display shift: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 MICROKO Shifts only the cursor position to the left. 15 Cursor or display shift: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 MICROKO Shifts only the cursor position to the left. 16 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1 ICROCO Writes ‘C’ correction. The display moves to the left. 17 Cursor or display shift: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 0 MICROCO Shifts the display and cursor to the right. 18 Cursor or display shift: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 1; DB1 = 0; DB0 = 0 MICROCO_ Shifts only the cursor to the right. 19 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1 ICROCOM_ Writes ‘M’. | | | 20 21 Philips Semiconductors INSTRUCTION LCD controller/driver 1997 Dec 16 STEP Return home: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 0 PHILIPS M Returns both display and cursor to the original position (address 0). Product specification PCF2104x INSTRUCTION DISPLAY OPERATION 1 Power supply on (PCF2104x is initialized by the internal reset function). Initialized. No display appears. 2 Function set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0 Sets to 8-bit operation, selects 2 × 24 display 3 Display on/off control: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 0 _ Turns on display and cursor. Entire display is blank after initialization. 4 Entry mode set: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 0 _ Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM. Display is not shifted. 5 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 P_ Writes ‘P’. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. | | | 6 40 7 Write data to CGRAM/DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1 PHILIPS_ Writes ‘S’. 8 Set DDRAM address: RS = 0; R/W = 0; DB7 = 1; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0 PHILIPS _ Sets DDRAM address to position the cursor at the head of the 2nd line. Write data to CGRAM/ DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1 PHILIPS Writes ‘M’. 9 PHILIPS Write data to CGRAM/ DDRAM: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 1 PHILIPS Writes ‘O’. MICROCO_ MICROCO_ Sets mode for display shift at the time of write. Product specification Write data to CGRAM/ DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 1 PCF2104x 12 M_ | | | 10 11 Philips Semiconductors STEP 8-bit operation, 2-line display example; using internal reset LCD controller/driver 1997 Dec 16 Table 8 Write data to CGRAM/ DDRAM: RS = 1; R/W = 0; DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 0; DB0 = 1 HILIPS ICROCOM_ OPERATION Writes ‘M’. Display is shifted to the left. The first and second lines shift together. | | | 14 15 DISPLAY Return home: RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 0 PHILIPS MICROCOM Returns both display and cursor to the original position (address 0). Philips Semiconductors 13 INSTRUCTION LCD controller/driver 1997 Dec 16 STEP 41 Product specification PCF2104x I2C-BUS BYTE STEP DISPLAY OPERATION 1 I2C-bus 2 Slave address for write: SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1; SA0 = 0; R/W = 0; Ack = 1 During the acknowledge cycle SDA will be pulled-down by the PCF2104x. 3 Send a control byte for function set: Co = 0; RS = 0; R/W = 0; Ack = 1 Control byte sets RS and R/W for following data bytes. 4 Function set: DB7 = 0; DB6 = 0; DB5 = 1; DB4 = X; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0; Ack = 1 Selects 1-line display; SCL pulse during acknowledge cycle starts execution of instruction. 5 Display on/off control: DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 1; DB1 = 1; DB0 = 0; Ack = 1 _ Turns on display and cursor. Entire display shows character Hex 20 (blank in ASCII-like character sets). 6 Entry mode set: DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = 1; DB0 = 0; Ack = 1 _ Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM. Display is not shifted. 7 I2C-bus start _ For writing data to DDRAM, RS must be set to 1. Therefore a control byte is needed. 8 Slave address for write: SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1; SA0 = 0; R/W = 0; Ack = 1 _ 9 Send a control byte for write data: Co = 0; RS = 1; R/W = 0; Ack = 1 _ 10 Write data to DDRAM: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 0; Ack = 1 P_ Writes ‘P’. The DDRAM has been selected at power-up. The cursor is incremented by 1 and shifted to the right. 11 Write data to DDRAM: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0; Ack = 1 PH_ Writes ‘H’. start Initialized. No display appears. 42 Write data to DDRAM: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 1; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 1; Ack = 1 PHILIPS_ Writes ‘S’. Product specification 16 PCF2104x | | | | 12 to 15 Philips Semiconductors Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1) LCD controller/driver 1997 Dec 16 Table 9 I2C-bus DISPLAY OPERATION 43 17 (optional (as step 8) 18 Control byte: Co = 1; RS = 0; R/W = 0; Ack = 1 PHILIPS_ 19 Return home: DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 1; DB0 = 0; Ack = 1 PHILIPS Sets DDRAM address 0 in Address Counter. (Also returns shifted display to original position. DDRAM contents unchanged). This instruction does not update the Data Register (DR). 20 Control byte for read: Co = 0; RS = 1; R/W = 1; Ack = 1 PHILIPS DDRAM content will be read from following instructions. The R/W has to be set to 1 while still in I2C-bus write mode. 21 I2C-bus start PHILIPS 22 Slave address for read: SA6 = 0; SA5 = 1; SA4 = 1; SA3 = 1; SA2 = 0; SA1 = 1; SA0 = 0; R/W = 1; Ack = 1 PHILIPS During the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface to be shifted out. In the previous instruction neither a ‘Set address’ nor a ‘Read data’ has been performed. Therefore the content of the DR was unknown. 23 Read data: 8 × SCL + master acknowledge; note 2: DB7 = X; DB6 = X; DB5 = X; DB4 = X; DB3 = X; DB2 = X; DB1 = X; DB0 = X; Ack = 1 PHILIPS 8 × SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA. MSB is DB7. During master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface. 24 Read data: 8 × SCL + master acknowledge; note 2: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0; Ack = 0 PHILIPS 8 × SCL; code of letter ‘H’ is read first. During master acknowledge code of ‘I’ is loaded into the I2C-bus interface. 25 Read data: 8 × SCL + no master acknowledge; note 2: DB7 = 0; DB6 = 1; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 1; Ack = 1 PHILIPS No master acknowledge; After the content of the I2C-bus interface register is shifted out no internal action is performed. No new data is loaded to the interface register, Data Register (DR) is not updated, Address Counter (AC) is not incremented and cursor is not shifted. 26 I2C stop PHILIPS stop) start + slave address for write PHILIPS_ 2. SDA is left at high-impedance by the microcontroller during the READ acknowledge. PCF2104x 1. X = don’t care. Product specification Notes Philips Semiconductors I2C-bus LCD controller/driver 1997 Dec 16 I2C-BUS BYTE STEP DESCRIPTION Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = X; DB2 = X; DB1 = X; DB0 = X BF cannot be checked before this instruction. ‘Function set’ (interface is 8-bits long). | Wait 2 ms Philips Semiconductors STEP LCD controller/driver 1997 Dec 16 Table 10 Initialization by instruction, 8-bit interface (note 1) | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = X; DB2 = X; DB1 = X; DB0 = X BF cannot be checked before this instruction.‘Function set’ (interface is 8-bits long). | Wait more than 40 µs | 44 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = X; DB2 = X; DB1 = X; DB0 = X | | BF cannot be checked before this instruction. ‘Function set’ (interface is 8-bits long). BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3). RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1; DB3 = N; DB2 = M; DB1 = X; DB0 = 0 ‘Function set’ (interface is 8-bits long). Specify the number of display lines. RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 1; DB2 = 0; DB1 = 0; DB0 = 0 ‘Display off’. RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 0; DB1 = 0; DB0 = 1 ‘Clear display’. RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0; DB3 = 0; DB2 = 1; DB1 = I/D; DB0 = S ‘Entry mode set’. | 1. X = don’t care. Product specification Note PCF2104x Initialization ends DESCRIPTION Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1 BF cannot be checked before this instruction. ‘Function set’ (interface is 8-bits long). | Wait 2 ms Philips Semiconductors STEP LCD controller/driver 1997 Dec 16 Table 11 Initialization by instruction, 4-bit interface. Not applicable for I2C-bus operation | RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1 BF cannot be checked before this instruction. ‘Function set’ (interface is 8-bits long). | Wait 40 µs | 45 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 1 | | BF cannot be checked before this instruction. ‘Function set’ (interface is 8-bits long). BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3). RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0 ‘Function set’ (set interface to 4-bits long). Interface is 8-bits long. RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 1; DB4 = 0 ‘Function set’ (interface is 4-bits long). RS = 0; R/W = 0; DB7 = N; DB6 = M; DB5 = 0; DB4 = 0 Specify number of display lines and voltage generator characteristic. RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 1; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 1; DB6 = 0; DB5 = 0; DB4 = 0 RS = 0; R/W = 0; DB7 = 0; DB6 = 0; DB5 = 0; DB4 = 0 Initialization ends ‘Entry mode set’. PCF2104x | ‘Clear display’. Product specification RS = 0; R/W = 0; DB7 = 0; DB6 = 1; DB5 = I/D; DB4 = S ‘Display off’. Philips Semiconductors Product specification LCD controller/driver PCF2104x DISPLAY LAYOUT: COLUMNS handbook, full pagewidth C1 15 46 1 31 PCF2104x column output numbers 60 LCD column numbers 60 DOT MATRIX LCD C16 PCF2104x column output numbers 45 DISPLAY LAYOUT: ROWS R8 to R1 R9 to R16 R17 to R24 R32 to R25 MGC623 Fig.32 Example of 4 × 12 display layout (PCF2104x). 1997 Dec 16 46 Philips Semiconductors Product specification LCD controller/driver PCF2104x handbook, full pagewidth display glass dot matrix COLUMN LAYOUT 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ROW LAYOUT 1 to 8 16 to 9 MLB898 2 lines by 12 characters display Fig.33 Display example (PCF2104x); 2 lines by 12 characters. 1997 Dec 16 47 Philips Semiconductors Product specification LCD controller/driver PCF2104x handbook, full pagewidth R1 R8 PCF2104x CHIP-ON-GLASS R17 R24 R9 R16 4 LINE BY 12 CHARACTER R25 R32 C1 2104 R9 C60 MGC626 SCL SDA VSS VDD VLCD Fig.34 Chip-on-glass application. 1997 Dec 16 48 Philips Semiconductors Product specification LCD controller/driver PCF2104x 86 85 84 83 82 81 R15 88 R25 89 R26 90 R28 ≈ 5.63 mm C22 C21 C20 C18 C19 C17 C15 C16 C14 C13 C11 C12 C10 C8 C9 C7 C5 C6 C3 C4 C2 91 92 R1 93 R2 94 R3 95 R4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 87 R16 R27 C1 R9 R10 R11 R13 handbook, full pagewidth R12 R14 18 BONDING PAD LOCATIONS 96 C23 57 C24 56 C25 55 C26 54 C27 53 C28 52 C29 51 C30 50 C31 49 C32 48 C33 SCL 97 47 C34 E RS 98 46 C35 99 45 C36 R/W 100 44 C37 43 C38 42 C39 41 C40 40 C41 39 C42 38 C43 37 C44 36 C45 35 C46 DB1 108 34 C47 DB0 109 33 C48 32 C49 31 C50 30 C51 29 C52 28 C53 x T1 101 0 0 DB7 102 DB6 103 y DB5 104 DB4 105 PCF2104x DB3 106 DB2 107 SDA 110 R31 C54 R32 C55 R5 C56 R7 R6 C57 R8 49 C58 VSS Fig.35 Bonding pad locations. C59 SA0 Chip dimensions: approximately 5.10 × 5.63 mm. Gold bump dimensions: approximately 89 × 89 × 25 µm. C60 VDD ≈ 5.10 mm R17 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 R18 9 R19 8 R20 7 R21 6 R22 5 R23 4 R24 3 R29 2 R30 1 OSC VLCD 111 1997 Dec 16 58 MGC628 Philips Semiconductors Product specification LCD controller/driver PCF2104x Table 12 Bonding pad locations (dimensions in µm). All x/y coordinates are referenced to centre of chip, see Fig.35 PAD x y C42 39 2350 −685 C41 40 2350 −525 −2637 C40 41 2350 −365 −1704.5 −2637 C39 42 2350 −205 5 −1339 −2637 C38 43 2350 −45 6 −1179 −2637 C37 44 2350 115 R6 7 −1019 −2637 C36 45 2350 275 R5 8 −859 −2637 C35 46 2350 435 R32 9 −699 −2637 C34 47 2350 595 R31 10 −539 −2637 C33 48 2350 755 R30 11 −379 −2637 C32 49 2350 915 R29 12 −219 −2637 C31 50 2350 1075 R24 13 −59 −2637 C30 51 2350 1235 R23 14 101 −2637 C29 52 2350 1395 R22 15 261 −2637 C28 53 2350 1555 R21 16 421 −2637 C27 54 2350 1715 R20 17 581 −2637 C26 55 2350 1875 R19 18 741 −2637 C25 56 2350 2035 R18 19 901 −2637 C24 57 2350 2195 R17 20 1061 −2637 C23 58 2350 2355 C60 21 1221 −2637 C22 59 2185 2637.5 C59 22 1381 −2637 C21 60 2025 2637.5 C58 23 1541 −2637 C20 61 1865 2637.5 C57 24 1701 −2637 C19 62 1705 2637.5 C56 25 1861 −2637 C18 63 1545 2637.5 C55 26 2021 −2637 C17 64 1385 2637.5 C54 27 2181 −2637 C16 65 1225 2637.5 C53 28 2350 −2445 C15 66 1065 2637.5 C52 29 2350 −2285 C14 67 905 2637.5 C51 30 2350 −2125 C13 68 745 2637.5 C50 31 2350 −1965 C12 69 585 2637.5 C49 32 2350 −1805 C11 70 425 2637.5 C48 33 2350 −1645 C10 71 265 2637.5 C47 34 2350 −1485 C9 72 105 2637.5 C46 35 2350 −1325 C8 73 −55 2637.5 C45 36 2350 −1165 C7 74 −215 2637.5 C44 37 2350 −1005 C6 75 −375 2637.5 C43 38 2350 −845 C5 76 −535 2637.5 SYMBOL PAD x OSC 1 −2184.5 −2637 VDD 2 −2024.5 −2637 SA0 3 −1864.5 VSS 4 R8 R7 1997 Dec 16 SYMBOL y 50 Philips Semiconductors Product specification LCD controller/driver SYMBOL PCF2104x PAD x y C4 77 −695 2637.5 C3 78 −855 2637.5 C2 79 −1015 2637.5 C1 80 −1175 2637.5 R9 81 −1385 2637.5 R10 82 −1545 2637.5 R11 83 −1705 2637.5 R12 84 −1865 2637.5 R13 85 −2025 2637.5 R14 86 −2185 2637.5 R15 87 −2349 2308 R16 88 −2349 2148 R25 89 −2349 1988 R26 90 −2349 1828 R27 91 −2349 1668 R28 92 −2349 1508 R1 93 −2349 1348 R2 94 −2349 1188 R3 95 −2349 1028 R4 96 −2349 868 SCL 97 −2349 632 E 98 −2349 472 RS 99 −2349 312 R/W 100 −2349 142 T1 101 −2349 −34 DB7 102 −2349 −233 DB6 103 −2349 −393 DB5 104 −2349 −668 DB4 105 −2349 −828 DB3 106 −2349 −1103 DB2 107 −2349 −1263 DB1 108 −2349 −1538 DB0 109 −2349 −1698 SDA 110 −2349 −1933 VLCD 111 −2349 −2453 RECPAT ‘F’ −2327.5 2427.5 RECPAT ‘C’ −2027.5 −2512.5 RECPAT ‘C’ 1982.5 2297.5 1997 Dec 16 51 Philips Semiconductors Product specification LCD controller/driver PCF2104x 19 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 21 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Dec 16 52 Philips Semiconductors Product specification LCD controller/driver PCF2104x NOTES 1997 Dec 16 53 Philips Semiconductors Product specification LCD controller/driver PCF2104x NOTES 1997 Dec 16 54 Philips Semiconductors Product specification LCD controller/driver PCF2104x NOTES 1997 Dec 16 55 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA53 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 417067/1200/04/pp56 Date of release: 1997 Dec 16 Document order number: 9397 750 02924