TDA8933 Class-D audio amplifier Rev. 01 — 15 May 2007 Preliminary data sheet 1. General description The TDA8933 is a high efficiency class-D amplifier with low power dissipation. The continuous time output power is 2 × 10 W in a stereo half bridge application (RL = 8 Ω) or 1 × 20 W in a mono full bridge application (RL =16 Ω). Due to the low power dissipation the device can be used without any external heat sink when playing music. Due to the implementation of Thermal Foldback (TF), even for high supply voltages and/or lower load impedances, the device will continue to operate with considerable music output power without the need for an external heat sink. The device has two full differential inputs driving two independent outputs. It can be used in a mono full bridge configuration (Bridge-Tied Load (BTL)) or a stereo half bridge configuration (Single-Ended (SE)). 2. Features n n n n n n n n n n n n High efficiency Application without heat sink using thermally enhanced small outline package Operating voltage from 10 V to 36 V asymmetrical or ± 5 V to ± 18 V symmetrical Thermally protected Thermal foldback Current limiting to avoid audio holes Full short circuit proof to supply lines (using advanced current protection) Switchable internal / external oscillator (master-slave setting) No pop noise Low power dissipation Mono bridge-tied load (full bridge) or stereo single-ended (half bridge) application Full differential inputs 3. Applications n n n n n n Flat panel television sets Flat panel monitor sets Multimedia systems Wireless speakers Mini/micro systems Home sound sets TDA8933 NXP Semiconductors Class-D audio amplifier 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit 25 36 V General; Vp = 25 V, fosc = 320 kHz, Tamb = 25 °C unless specified otherwise VP supply voltage asymmetrical supply 10 symmetrical supply 5 12.5 18 V IP supply current Sleep mode - 0.6 1.0 mA Iq(tot) total quiescent current Operating mode; no load, no snubbers or filter connected - 40 50 mA Stereo SE channel Po(RMS) RMS output power continuous time output power per channel [1] RL = 4 Ω; VP = 17 V THD+N = 0.5 %, fi = 1 kHz 5.9 6.5 - W THD+N = 0.5 %, fi = 100 Hz - 6.5 - W THD+N = 10 %, fi = 1 kHz 7.5 8.3 - W THD+N = 10 %, fi = 100 Hz - 8.3 - W THD+N = 0.5 %, fi = 1 kHz 7.3 8.1 - W THD+N = 0.5 %, fi = 100 Hz - 8.1 - W THD+N = 10 %, fi = 1 kHz 9.3 10.3 - W - 10.3 - W THD+N = 0.5 % 11.2 12.4 - W THD+N = 10 % 14.1 15.7 - W RL = 8 Ω; VP = 25 V THD+N = 10 %, fi = 100 Hz short time output power per channel; THD+N = 10 %, see Figure 23 for details [2] RL = 8 Ω; VP = 31 V TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 2 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit THD+N = 0.5 %, fi = 1 kHz 11.9 13.2 - W THD+N = 0.5 %, fi = 100 Hz - 13.2 - W THD+N = 10 %, fi = 1 kHz 15.4 17.1 - W THD+N = 10 %, fi = 100 Hz - 17.1 - W THD+N = 0.5 %, fi = 1 kHz 14.9 16.5 - W THD+N = 0.5 %, fi = 100 Hz - 16.5 - W THD+N = 10 %, fi = 1 kHz 18.9 21 - W - 21 - W THD+N = 0.5 % 22.8 25.3 - W THD+N = 10 % 28.8 32 - W Mono BTL channel Po(RMS) RMS output power continuous time output power [1] THD+N = 10 %; fi = 1 kHz RL = 8 Ω; VP = 17 V RL = 16 Ω; VP = 25 V THD+N = 10 %, fi = 100 Hz short time output power; THD+N = 10 %, see Figure 35 for details [2] RL = 16 Ω; VP = 31 V [1] Output power is measured indirectly, based on RDSon measurement. [2] 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection. 5. Ordering information Table 2. Ordering information Type number TDA8933T Package Name Description Version SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 3 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 6. Block diagram VDDA OSCREF OSCIO VDDP1 31 29 10 8 OSCILLATOR IN1P 28 2 VSSD DRIVER HIGH PWM MODULATOR 27 CTRL IN1N 3 DRIVER LOW 26 BOOT1 OUT1 VSSP1 VDDA STABI 11V 25 STAB1 12 INREF + VSSP1 VDDA VSSA MANAGER STABI 11V VSSP2 IN2P 24 21 15 20 DRIVER HIGH PWM MODULATOR 22 CTRL IN2N CGND DIAG 14 DRIVER LOW PROTECTIONS OVP, OCP, OTP UVP, TF, WP 7 REG5V 18 BOOT2 VDDP2 OUT2 VSSP2 DREF VSSD 4 VDDA POWERUP 23 STAB2 11 HVPREF 6 30 HVP1 MODE ENGAGE 19 5 VSSA HVP2 HALF SUPPLY VOLTAGE CGND 9 13 VSSA TEST 1, 16, 17, 32 010aaa113 VSSD(HW) Fig 1. Block diagram TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 4 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 7. Pinning information 7.1 Pinning VSSD(HW) 1 IN1P 2 32 VSSD(HW) 31 OSCIO IN1N 3 30 HVP1 DIAG 4 ENGAGE 5 29 VDDP1 28 BOOT1 POWER UP 6 27 OUT1 CGND 7 VDDA 8 26 VSSP1 25 STAB1 VSSA 9 TDA8933T SO32 24 STAB2 23 VSSP2 22 OUT2 OSCREF 10 HVPREF 11 INREF 12 21 BOOT2 TEST 13 IN2N 14 20 VDDP2 19 HVP2 IN2P 15 18 DREF 17 VSSD(HW) VSSD(HW) 16 010aaa114 Fig 2. Pin configuration diagram 7.2 Pin description Table 3. Pinning description Symbol Pin Description VSSD(HW) 1 negative digital supply voltage and handle wafer connection IN1P 2 positive audio input for channel 1 IN1N 3 negative audio input for channel 1 DIAG 4 diagnostic output; open-drain ENGAGE 5 engage input to switch between Mute mode and Operating mode POWERUP 6 power-up input to switch between Sleep mode and Mute mode CGND 7 control ground; reference for POWERUP, ENGAGE and DIAG VDDA 8 positive analog supply voltage VSSA 9 negative analog supply voltage OSCREF 10 input internal oscillator setting (only master setting) HVPREF 11 decoupling of internal half supply voltage reference INREF 12 decoupling for input reference voltage TEST 13 test signal input; for testing purpose only IN2N 14 negative audio input for channel 2 IN2P 15 positive audio input for channel 2 VSSD(HW) 16 negative digital supply voltage and handle wafer connection VSSD(HW) 17 negative digital supply voltage and handle wafer connection DREF 18 decoupling of internal (reference) 5 V regulator for logic supply TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 5 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier Table 3. Pinning description …continued Symbol Pin Description HVP2 19 half supply output voltage 2 for charging single-ended capacitor for channel 2 VDDP2 20 positive power supply voltage for channel 2 BOOT2 21 bootstrap high-side driver channel 2 OUT2 22 Pulse Width Modulated (PWM) output channel 2 VSSP2 23 negative power supply voltage for channel 2 STAB2 24 decoupling of internal 11 V regulator for channel 2 drivers STAB1 25 decoupling of internal 11 V regulator for channel 1 drivers VSSP1 26 negative power supply voltage for channel 1 OUT1 27 PWM output channel 1 BOOT1 28 bootstrap capacitor for channel 1 VDDP1 29 positive power supply voltage for channel 1 HVP1 30 half supply output voltage 1 for charging single-ended capacitor for channel 1 OSCIO 31 oscillator input in slave configuration or oscillator output in master configuration VSSD(HW) 32 negative digital supply voltage and handle wafer connection 8. Functional description 8.1 General The TDA8933 is a mono full bridge or stereo half bridge audio power amplifier using class-D technology. The audio input signal is converted into a Pulse Width Modulated (PWM) signal via an analog input stage and PWM modulator. To enable the output power Diffusion Metal Oxide Semiconductor (DMOS) transistors to be driven, this digital PWM signal is applied to control and handshake block and driver circuits for both the high side and low side. A 2nd-order-low-pass filter converts the PWM signal to an analog audio signal across the loudspeakers. The TDA8933 contains two independent half bridges with full differential input stages. The loudspeakers can be connected in the following configurations: • Mono full bridge: Bridge Tied Load (BTL) • Stereo half bridge: Single-Ended (SE) The TDA8933 contains circuits common to both channels, such as: the oscillator, all reference sources, the mode functionality and a digital timing manager. The following protections are built-in: thermal foldback, temperature, current and voltage. TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 6 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 8.2 Mode selection and interfacing The TDA8933 can be switched to one of four operating modes using pins POWERUP and ENGAGE: • Sleep mode: with low supply current • Mute mode: the amplifiers are switching idle (50 % duty cycle), but the audio signal at the output is suppressed by disabling the Vl-converter input stages. The capacitors on pins HVP1 and HVP2 have been charged to half the supply voltage (asymmetrical supply only) • Operating mode: the amplifiers are fully operational with an output signal • Fault mode Both pins POWERUP and ENGAGE refer to pin CGND. Table 4 shows the different modes as a function of the voltages on the POWERUP and ENGAGE pins. Table 4. Mode selection for the TDA8933 Mode Pin POWERUP[1] ENGAGE[1] DIAG Sleep < 0.8 V < 0.8 V undefined Mute 2 V to 6 V < 0.8 V >2V Operating 2 V to 6 V 3 V to 6 V >2V Fault 2 V to 6 V undefined < 0.8 V [1] When there are symmetrical supply conditions, the voltage applied to pins POWERUP and ENGAGE must never exceed the supply voltage (VDDA, VDDP1 or VDDP2). If the transition between Mute mode and Operating mode is controlled via a time constant, the start-up will be pop free since the DC output offset voltage is applied gradually to the output between Mute mode and Operating mode. The bias current setting of the VI-converters is related to the voltage on pin ENGAGE. • Mute mode: the bias current setting of the VI-converters is zero (VI-converters disabled). • Operating mode: the bias current is at maximum. The time constant required to apply the DC output offset voltage gradually between Mute mode and Operating mode can be generated by applying a decoupling capacitor on pin ENGAGE. The value of the capacitor on pin ENGAGE should be 470 nF. TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 7 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier VP POWERUP DREF HVPREF HVP1, HVP2 0.43VENGAGE ENGAGE 0.3VENGAGE 0.17VENGAGE AUDIO audio AUDIO AUDIO OUT1, OUT2 PWM PWM PWM DIAG OSCIO operating mute operating fault operating sleep 001aae788 Fig 3. Start-up sequence 8.3 Pulse width modulation frequency The output signal of the amplifier is a PWM signal with a carrier frequency of approximately 320 kHz. Using a 2nd-order-low-pass filter in the application results in an analog audio signal across the loudspeaker. The PWM switching frequency can be set by an external resistor Rosc connected between pin OSCREF and VSSD(HW). The carrier frequency can be set between 300 kHz and 500 kHz. Using an external resistor of 39 kΩ, the carrier frequency is set to an optimized value of 320 kHz (see Figure 4). If two or more TDA8933 devices are used in the same audio application, it is recommended to synchronize the switching frequency of all devices.This can be done by connecting all the OSCIO pins together and configuring one of the TDA8933 devices in the application as the clock master. Configure the other TDA8933 devices as slaves. Pin OSCIO is a 3-state input or output buffer. Pin OSCIO is configured in master mode as oscillator output, and in slave mode as oscillator input. Master mode is enabled by applying a resistor between pin OSCREF and VSSD(HW), while slave mode is enabled by connecting pin OSCREF directly to VSSD(HW) (without any resistor). The value of the resistor also sets the frequency of the carrier and can be calculated with Equation 1: TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 8 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 9 12.45x10 f osc = ------------------------R osc (1) Where: fosc = oscillator frequency (Hz) Rosc = oscillator resistor (Ω) (on pin OSCREF) 001aad758 550 fosc (kHz) 450 350 250 25 30 35 40 45 Rosc (kΩ) Fig 4. Oscillation frequency as a function of Rosc Table 5 summarizes how to configure the TDA8933 in master or slave configuration. Table 5. Master/slave configuration Configuration Pin OSCREF OSCIO Master Rosc > 25 kΩ to VSSD(HW) output Slave Rosc = 0 Ω; shorted to VSSD(HW) input 8.4 Protections The following protections are implemented in the TDA8933: • • • • • Thermal Foldback (TF) OverTemperature Protection (OTP) OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protections – UnderVoltage Protection (UVP) – OverVoltage Protection (OVP) – UnBalance Protection (UBP) • ElectroStatic Discharge (ESD) The behavior of the device under the different fault conditions differs according to the protection activated and is described in the following sections. TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 9 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 8.4.1 Thermal Foldback (TF) If the junction temperature of the TDA8933 exceeds the threshold level (Tj > 140 °C), the gain of the amplifier is decreased gradually to a level where the combination of dissipation (P) and the thermal resistance from junction to ambient (Rth(j-a)) results in a junction temperature around the threshold level. This means that the device will not switch off completely, but remains operational at lower output power levels. With music output signals, this feature enables high peak output powers while still operating without any external heat sink other than the printed-circuit board area. If the junction temperature still increases due to external causes, the OverTemperature Protection (OTP) shuts down the amplifier completely. 8.4.2 OverTemperature Protection (OTP) If the junction temperature Tj > 155 °C, the power stage will shut down immediately. 8.4.3 OverCurrent Protection (OCP) When the output current of the device exceeds 2 A due to a short-circuit across the load or an impedance drop, the cycle-by-cycle current limitation becomes active. This means the device will not switch off, but continue to operate while limiting the current without causing audio holes (interruptions). The maximum output current will not go beyond the absolute maximum current. If the current exceeds 2 A due to a low ohmic short from the demodulated output (after the inductor) to either VSS or VDD both power stages become floating. The DIAG is set low for 50 ms and the internal timer of 100 ms is started. The timer will keep both power stages disabled for 100 ms. As long as the short remains, this cycle will repeat. The average power dissipation in the TDA8933 will be low because the short-circuit current will flow only during a very small part of the timer cycle of 100 ms. 8.4.4 Window Protection (WP) WP checks the PWM output voltage before switching from Sleep mode to Mute mode (outputs switching) and is activated: • During the start-up sequence, when pin POWERUP is switched from Sleep mode to Mute mode. In the event of a short-circuit at one of the output terminals to VDDP1, VSSP1, VDDP2 or VSSP2 the start-up procedure is interrupted and the TDA8933 waits for open-circuit outputs. Because the check is done before enabling the power stages, no large currents will flow in the event of a short-circuit. • When the amplifier is shut down completely, due to activation of the OCP because a short to one of the supply lines is made, then during restart (after 100 ms) the window protection will be activated. As a result, the amplifier will not start up until the short to the supply lines is removed. 8.4.5 Supply voltage protections If the supply voltage drops below 10 V, the UVP circuit is activated and the system will shut down directly. This switch-off will be silent and without pop noise. When the supply voltage rises above the threshold level, the system is restarted again after 100 ms. TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 10 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier If the supply voltage exceeds 36 V, the OVP circuit is activated and the power stages will shut down. It is re-enabled as soon as the supply voltage drops below the threshold level. The system is restarted again after 100 ms. It should be noted that supply voltages > 40 V may damage the TDA8933. Two conditions should be distinguished: • If the supply voltage is pumped to higher values by the TDA8933 application itself (see also Section 14.8), the OVP is triggered and the TDA8933 is shut down. The supply voltage will decrease and the TDA8933 is protected against any overstress. • If a supply voltage > 40 V is caused by other or external causes, the TDA8933 will shut down, but the device can still be damaged since the supply voltage will remain > 40 V in this case. The OVP protection is not a supply clamp. An additional UBP circuit compares the positive analog supply voltage (VDDA) and the negative analog supply voltage (VSSA) and is triggered if the voltage difference between them exceeds a certain level. This level depends on the sum of both supply voltages. The unbalance threshold levels can be defined as follows: • LOW-level threshold: VP(th)(ubp)l < 8/5 × VHVPREF • HIGH-level threshold: VP(th)(ubp)h > 8/3 × VHVPREF In a symmetrical supply the UBP is released when the unbalance of the supply voltage is within 6 % of its starting value. Table 6 shows an overview of all protections and the effect on the output signal. Table 6. Protection Overview of protections for the TDA8933 Restart When fault is removed Every 100 ms OTP no yes OCP yes no WP yes no UVP no yes OVP no yes UBP no yes TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 11 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 8.5 Diagnostic input and output Whenever one of the protections is triggered, except for TF, pin DIAG is activated to LOW level (see Table 6). An internal reference supply will pull up the open-drain DIAG output to approximately 2.4 V. This internal reference supply can deliver approximately 50 µA. The DIAG pin refers to pin CGND.The diagnostic output signal during different short circuit conditions is illustrated in Figure 5. Using pin DIAG as input, a voltage < 0.8 V will put the device into Fault mode. Vo Vo 2.4 V 2.4 V amplifier restart 0V ≈ 50 ms ≈ 50 ms no restart 0V short to supply line shorted load 001aad759 Fig 5. Diagnostic output for different kinds of short circuit conditions 8.6 Differential inputs For a high common-mode rejection ratio and for maximum flexibility in the application, the audio inputs are fully differential. By connecting the inputs anti-parallel, the phase of one of the two channels can be inverted, so that the amplifier can operate as a mono BTL amplifier. The input configuration for a mono BTL application is illustrated in Figure 6. In the single-ended configuration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the power supply at low signal frequencies and minimizes supply pumping (see also Section 14.8). IN1P OUT1 IN1N audio input IN2P OUT2 IN2N 001aad760 Fig 6. Input configuration for a mono BTL application TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 12 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 8.7 Output voltage buffers When pin POWERUP is set HIGH, the half supply output voltage buffers are switched on in asymmetrical supply configuration. The start-up will be pop free because the device starts switching when the capacitor on pin HVPREF and the SE capacitors are completely charged. Output voltage buffers: • Pins HVP1 and HVP2: The time required for charging the SE capacitor depends on its value. The half supply voltage output is disabled when the TDA8933 is used in a symmetrical supply application. • Pin HVPREF: This output voltage reference buffer charges the capacitor on pin HVPREF. • Pin INREF: This output voltage reference buffer charges the input reference capacitor on pin INREF. Pin INREF applies the bias voltage for the inputs. TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 13 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 9. Internal circuitry Table 7. Pin Internal circuitry Symbol Equivalent circuit 1, 16, 17, 32 VSSD(HW) 1, 16, 17, 32 VDDA VSSA 001aad784 2 IN1P 3 IN1N 12 INREF 14 IN2N 15 IN2P VDDA 13 VSSA 001aad795 4 DIAG VDDA 2.5 V 50 µA 4 5 kΩ ± 20 % CGND VSSA 5 010aaa198 ENGAGE VDDA 4.6 V Iref = 20 µA 5 226 kΩ ± 20 % VSSA CGND TDA8933_1 Preliminary data sheet 001aad787 © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 14 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier Table 7. Internal circuitry …continued Pin Symbol 6 POWERUP Equivalent circuit VDDA 6 VSSA 7 CGND 001aad788 CGND VDDA 7 VSSA 001aad789 8 VDDA 8 VSSA VSSD 001aad790 9 VSSA VDDA 9 VSSD 001aad791 TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 15 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier Table 7. Internal circuitry …continued Pin Symbol 10 OSCREF Equivalent circuit VDDA Iref 10 VSSA 11 001aad792 HVPREF VDDA 11 VSSA 13 010aaa199 TEST VDDA 13 VSSA 001aad795 18 DREF VDD 18 VSSD 010aaa200 19 HVP2 30 HVP1 VDDA 19, 30 VSSA 20 VDDP2 23 VSSP2 26 VSSP1 29 VDDP1 010aaa201 20, 29 23, 26 001aad798 TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 16 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier Table 7. Internal circuitry …continued Pin Symbol 21 BOOT2 28 BOOT1 Equivalent circuit 21, 28 OUT1, OUT2 001aad799 22 OUT2 27 OUT1 VDDP1, VDDP2 22, 27 VSSP1, VSSP2 24 STAB2 25 STAB1 010aaa202 VDDA 24, 25 VSSP1, VSSP2 31 010aaa203 OSCIO DREF 31 VSSD 010aaa204 TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 17 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 10. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VP supply voltage asymmetrical supply −0.3 +40 V Vx voltage on pin x +5 V IN1P, IN1N, IN2P, IN2N [1] −5 OSCREF, OSCIO, TEST [2] VSSD(HW) - 0.3 5 V POWERUP, ENGAGE, DIAG [3] VCGND - 0.3 6 V all other pins [4] VSS - 0.3 VDD + 0.3 V IORM repetitive peak output current [5] 2.3 - A maximum output current limiting Tj junction temperature - 150 °C Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C P power dissipation - 5 W [1] Measured with respect to pin INREF; Vx < VDD + 0.3 V. [2] Measured with respect to pin VSSD(HW); Vx < VDD + 0.3 V. [3] Measured with respect to pin CGND; Vx < VDD + 0.3 V. [4] VSS = VSSP1 = VSSP2; VDD = VDDP1 = VDDP2. [5] Current limiting concept. 11. Thermal characteristics Table 9. Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient free air natural convection Ψj-lead thermal characterization parameter from junction to lead Ψj-top thermal characterization parameter from junction to top of package [1] Min Typ Max Unit - JEDEC test board [1] - 41 44 K/W 2 layer application board [2] - 44 - K/W - - 30 K/W - - 8 K/W [3] Measured in a JEDEC high K-factor test board (standard EIA/JESD 51-7) in free air with natural convection. [2] 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection. [3] Strongly dependent on where the measurement is taken on the package. TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 18 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 12. Static characteristics Table 10. Characteristics VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit Supply VP supply voltage asymmetrical supply 10 25 36 V symmetrical supply ±5 ±12.5 ±18 V IP supply current Sleep mode - 0.6 1.0 mA Iq(tot) total quiescent current Operating mode; no load, no snubbers or filter connected - 40 50 mA Tj = 25 °C - 350 - mΩ Tj = 125 °C - 545 - mΩ 0 - 6.0 V - 1 20 µA Series resistance output switches RDSon drain-source on-state resistance Power up input: pin POWERUP[1] VI input voltage II input current VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2 - 6.0 V 4.2 4.6 5.0 V 0 - 6.0 V - 20 40 µA Engage input: pin VI = 3 V ENGAGE[1] VO output voltage VI input voltage IO output current VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 3 - 6.0 V protection activated; see Table 6 - - 0.8 V Operating mode 2 2.5 3.3 V Reference to VSSA - 2.1 - V 0.5VP − 0.2 V 0.5VP 0.5VP + 0.2 V V Diagnostic output: pin VO VI = 3 V DIAG[1] output voltage Bias voltage for inputs: pin INREF VO(bias) bias output voltage Half supply voltage Pins HVP1 and HVP2 VO output voltage half supply voltage to charge SE capacitor IO output current VHVP1 = VHVP2 = VO − 1 V output voltage half supply reference voltage in Mute mode 50 mA Pin HVPREF VO 0.5VP − 0.2 V 0.5VP 0.5VP + 0.2 V V 4.5 4.8 5.1 V Reference voltage for internal logic: pin DREF VO output voltage TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 19 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier Table 10. Characteristics …continued VP = 25 V, fosc = 320 kHz and Tamb = 25 °C; unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit Mute mode - - 15 mV Operating mode - - 100 mV Mute mode - - 20 mV Operating mode - - 150 mV 10 11 12 V Amplifier outputs: pins OUT1 and OUT2 VO(offset) output offset voltage SE; with respect to HVPREF BTL Stabilizer output: pins STAB1, STAB2 output voltage VO Mute mode and Operating mode; with respect to pins VSSP1 and VSSP2 Voltage protections VP(uvp) undervoltage protection supply voltage 8.0 9.5 9.9 V VP(ovp) overvoltage protection supply voltage 36.1 38.5 40 V VP(th)(ubp)l low unbalance protection threshold supply voltage VHVPREF = 11 V - - 18 V VP(th)(ubp)h high unbalance protection threshold supply voltage VHVPREF = 11 V 29 - - V current limiting 2.0 2.3 - A Current protections IO(ocp) overcurrent protection output current Temperature protection Tact(th_prot) thermal protection activation temperature 155 - 160 °C Tact(th_fold) thermal foldback activation temperature 140 - 150 °C Oscillator reference: pin OSCIO[2] VIH HIGH-level input voltage 4.0 - 5.0 V VIL LOW-level input voltage 0 - 0.8 V VOH HIGH-level output voltage 4.0 - 5.0 V VOL LOW-level output voltage 0 - 0.8 V Nslave(max) maximum number of slaves 12 - - - [1] Measured with respect to pin CGND. [2] Measured with respect to pin VSSD(HW). driven by one master TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 20 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 13. Dynamic characteristics Table 11. Switching characteristics VP = 25 V; Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Internal oscillator fosc oscillator frequency Rosc = 39 kΩ - 320 - kHz range 300 - 500 kHz IO = 0 A - 10 - ns Timing PWM output: pins OUT1 and OUT2 tr rise time tf fall time IO = 0 A - 10 - ns tw(min) minimum pulse width IO = 0 A - 80 - ns Table 12. SE characteristics VP = 25 V, RL = 2 × 8 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [6] and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Po(RMS) RMS output power continuous time output power per channel Min Typ Max Unit [1] RL = 4 Ω; VP = 17 V THD+N = 0.5 %, fi = 1 kHz 5.9 6.5 - W THD+N = 0.5 %, fi = 100 Hz - 6.5 - W THD+N = 10 %, fi = 1 kHz 7.5 8.3 - W THD+N = 10 %, fi = 100 Hz - 8.3 - W THD+N = 0.5 %, fi = 1 kHz 7.3 8.1 - W THD+N = 0.5 %, fi = 100 Hz - 8.1 - W THD+N = 10 %, fi = 1 kHz 9.3 10.3 - W - 10.3 - W 11.2 12.4 - W 14.1 15.7 - W fi = 1 kHz - 0.011 0.1 % fi = 6 kHz - 0.06 0.1 % 29 30 31 dB - 0.5 1 dB 70 80 - dB fi = 100 Hz - 60 - dB fi = 1 kHz 40 50 - dB 70 100 - kΩ RL = 8 Ω; VP = 25 V THD+N = 10 %, fi = 100 Hz short time output power per channel; THD+N = 10 %, see Figure 23 for details [2] RL = 8 Ω; VP = 31 V THD+N = 0.5 % THD+N = 10 % THD+N total harmonic distortion-plus-noise Gv(cl) closed-loop voltage gain |∆GV| voltage gain difference Po = 1 W Vi =100 mV; no load αcs channel separation Po = 1 W; fi = 1 kHz SVRR supply voltage ripple rejection Operating mode |Zi| input impedance differential TDA8933_1 Preliminary data sheet [3] [4] © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 21 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier Table 12. SE characteristics …continued VP = 25 V, RL = 2 × 8 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [6] and Tamb = 25 °C; unless otherwise specified. Symbol Vn(o) Parameter Conditions Min Typ Max Unit Operating mode; Rs = 0 Ω [5] noise output voltage - 100 150 µV Mute mode [5] - 70 100 µV VO(mute) mute output voltage Mute mode; Vi = 1 V (RMS) and fi = 1 kHz - 100 - µV CMRR common mode rejection ratio Vi(cm) = 1 V (RMS) - 75 - dB ηpo output power efficiency Po = 10 W VP = 17 V; RL = 4 Ω 86 87 - % VP = 25 V; RL = 8 Ω 89 90 - % [1] Output power is measured indirectly; based on RDSon measurement. [2] 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection. [3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. [4] Maximum Vripple = 2 V (p-p); RS = 0 Ω. [5] B = 20 Hz to 20 kHz, AES17 brick wall. [6] RS is the series resistance of inductor and capacitor of low-pass LC filter in the application. Table 13. BTL characteristics VP = 25 V, RL = 16 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [5] and Tamb = 25 °C; unless otherwise specified. Symbol Po(RMS) Parameter RMS output power Conditions Min Typ Max Unit THD+N = 0.5 %, fi = 1 kHz 11.9 13.2 - W THD+N = 0.5 %, fi = 100 Hz - 13.2 - W THD+N = 10 %, fi = 1 kHz 15.4 17.1 - W THD+N = 10 %, fi = 100 Hz - 17.1 - W THD+N = 0.5 %, fi = 1 kHz 14.9 16.5 - W THD+N = 0.5 %, fi = 100 Hz - 16.5 - W THD+N = 10 %, fi = 1 kHz 18.9 21 - W THD+N = 10 %, fi = 100 Hz - 21 - W 22.8 25.3 - W 28.8 32 - W continuous time output power: THD+N = 10 %; fi = 1 kHz [1] RL = 8 Ω; VP = 17 V RL = 16 Ω; VP = 25 V short time output power; THD+N = 10 %, see Figure 35 for details [2] RL = 16 Ω; VP = 31 V THD+N = 0.5 % THD+N = 10 % THD+N total harmonic distortion-plus-noise Gv(cl) closed-loop voltage gain |Zi| input impedance Po = 1 W fi = 1 kHz - 0.04 0.1 % fi = 10 kHz - 0.18 0.24 % 35 36 37 dB 35 50 - kΩ differential TDA8933_1 Preliminary data sheet [3] © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 22 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier Table 13. BTL characteristics …continued VP = 25 V, RL = 16 Ω, fi = 1 kHz, fosc = 320 kHz, RS < 0.1 Ω [5] and Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Vn(o) noise output voltage Rs = 0 Ω Operating mode [4] Mute mode [4] Min Typ Max Unit - 100 150 µV - 70 100 µV VO(mute) mute output voltage Mute mode; Vi = 1 V (RMS) and fi = 1 kHz - 100 - µV CMRR common mode rejection ratio Vi(cm) = 1 V (RMS) - 75 - dB ηpo output power efficiency Po = 17 W; VP = 17 V; RL = 8 Ω 87 89 - % Po = 21 W; VP = 25 V; RL = 16 Ω 90 92 - % [1] Output power is measured indirectly; based on RDSon measurement. [2] 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection. [3] THD+N is measured in a bandwidth of 20 Hz to 20 kHz, AES17 brick wall. [4] B = 22 Hz to 20 kHz, AES17 brick wall. [5] RS is the series resistance of inductor and capacitor of low-pass LC filter in the application. TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 23 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 14. Application information 14.1 Output power estimation The output power Po at THD+N = 0.5 %, just before clipping, for the SE and BTL configurations can be estimated using Equation 2 and Equation 3. SE configuration: P o ( 0.5 %) 2 RL --------------------------------------------------------- × (1 – t × f ) × V w ( min ) osc P R L + R DSon + R s + R ESR = -----------------------------------------------------------------------------------------------------------------------------------------8 × RL (2) BTL configuration: P o ( 0.5 %) 2 RL ----------------------------------------------------- × (1 – t w ( min ) × f osc ) × V P R L + 2 × ( R DSon + R s )- = --------------------------------------------------------------------------------------------------------------------------------------2 × RL (3) Where: VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V) RL = load resistance (Ω) RDSon = drain-source on-state resistance (Ω) Rs = series resistance output inductor (Ω) RESR = equivalent series resistance SE capacitance (Ω) tw(min) = minimum pulse width (s); 80 ns typical fosc = oscillator frequency (Hz); 320 kHz typical with Rosc = 39 kΩ The output power Po at THD+N = 10 % can be estimated by: P o ( 10 %) = 1.25 × P o ( 0.5 (4) %) Figure 7 and Figure 8 show the estimated output power at THD+N = 0.5 % and THD+N = 10 % as a function of the supply voltage for SE and BTL configurations at different load impedances. The output power is calculated with: RDSon = 0.35 Ω (at Tj = 25 °C), Rs = 0.05 Ω, RESR = 0.05 Ω and IO(ocp) = 2 A (minimum). TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 24 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa143 20 Po (W) RL = 8 Ω Po (W) RL = 8 Ω 16 010aaa147 20 15 RL = 6 Ω RL = 6 Ω 12 10 RL = 4 Ω RL = 4 Ω 8 5 4 0 0 10 16 22 28 10 34 20 30 36 VP (V) VP (V) a. THD+N = 0.5 % b. THD+N = 10 % (1) When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP details. Fig 7. SE output power as a function of supply voltage 010aaa144 40 Po (W) 010aaa145 40 RL = 16 Ω Po (W) RL = 16 Ω 30 30 20 20 RL = 8 Ω RL = 8 Ω RL = 6 Ω RL = 6 Ω 10 10 0 0 10 20 30 40 10 20 VP (V) 30 40 VP (V) a. THD+N = 0.5 % b. THD+N = 10 % (1) When the maximum current of 2 A is reached, the current limitation feature becomes active. See also Section 8.4.3 for OCP details. Fig 8. BTL output power as a function of supply voltage TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 25 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 14.2 Output current limiting The peak output current IOM is internally limited to 2 A (minimum). During normal operation the output current should not exceed this threshold level, otherwise the signal is distorted. The peak output current in SE or BTL configurations can be calculated using Equation 5 and Equation 6. SE configuration: 0.5 × V P I O ( max ) ≤ ---------------------------------------------------------- ≤ 2 A R L + R DSon + R s + R ESR (5) BTL configuration: VP I O ( max ) ≤ ------------------------------------------------------ ≤ 2 A R L + 2 × ( R DSon + R s ) (6) Where: VP = supply voltage VDDP1 - VSSP1 (V) or VDDP2 - VSSP2 (V) RL = load resistance (Ω) RDSon = drain-source on-state resistance (Ω) Rs = series resistance (Ω) RESR = equivalent series resistance SE capacitance (Ω) Example: An 8 Ω speaker in the BTL configuration can be used up to a supply voltage of 18 V without running into current limiting. Current limiting (clipping) will avoid audio holes but produces a similar distortion to voltage clipping. 14.3 Speaker configuration and impedance For a flat frequency response (second order Butterworth filter) it is necessary to change the low-pass filter components LLC and CLC according to the speaker configuration and impedance. Table 14 shows the required values in practice. Table 14. Filter component values Configuration RL (Ω) LLC (µH) CLC (nF) SE 4 22 680 6 33 470 8 47 330 8 22 680 16 47 330 BTL TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 26 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 14.4 Single-ended capacitor The SE capacitor forms a high-pass filter with the speaker impedance. So the frequency response will roll off with 20 dB per decade below f−3dB (3 dB cut-off frequency). The 3 dB cut-off frequency is equal to: 1 f –3dB = ----------------------------------2π × R L × C SE (7) Where: f−3dB = 3 dB cut-off frequency (Hz) RL = load resistance (Ω) CSE = single-ended capacitance (F); see Figure 37. Table 15 shows an overview of the required SE capacitor values in the case of 60 Hz, 40 Hz or 20 Hz 3 dB cut-off frequency. Table 15. SE capacitor values Impedance (Ω) CSE (µF) f−3dB = 60 Hz f−3dB = 40 Hz f−3dB = 20 Hz 4 680 1000 2200 6 470 680 1500 8 330 470 1000 14.5 Gain reduction The gain of the TDA8933 is internally fixed at 30 dB for SE, and 36 dB for BTL. The gain can be reduced by a resistive voltage divider at the input (see Figure 9). R1 audio in 470 nF R3 R2 100 kΩ 470 nF 010aaa137 Fig 9. Input configuration for reducing gain When applying a resistive divider, the total voltage gain Gv(tot) can be calculated using Equation 8 and Equation 9: R EQ G v ( tot ) = G v ( cl ) + 20 log -----------------------------------------R EQ + ( R1 + R2 ) (8) Where: Gv(tot) = total voltage gain (dB) Gv(cl) = closed-loop voltage gain, fixed at 30 dB for SE (dB) REQ = equivalent resistance, R3 and Zi (Ω) TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 27 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier R1 = series resistors (Ω) R2 = series resistors (Ω) R3 × Z R EQ = ------------------i R3 + Z i (9) Where: REQ = equivalent resistance (Ω) R3 = parallel resistor (Ω) Zi = internal input impedance (Ω) Example: Substituting R1 = R2 = 4.7 kΩ, Zi = 100 kΩ and R3 = 22 kΩ in Equation 8 and Equation 9 results in a gain of Gv(tot) = 26.3 dB. 14.6 Device synchronization If two or more TDA8933 devices are used in one application it is recommended that all devices are synchronized at the same switching frequency to avoid beat tones. Synchronization can be realized by connecting all OSCIO pins together and configuring one of the TDA8933 devices as master, while the other TDA8933 devices are configured as slaves (see Figure 10). A device is configured as master when a resistor Rosc is connected between pin OSCREF and pin VSSD(HW), setting the carrier frequency. Pin OSCIO of the master is then configured as an oscillator output for synchronization. The OSCREF pins of the slave devices should be shorted to pin VSSD(HW), configuring pin OSCIO as an input. master slave IC1 IC2 TDA8933 TDA8933 OSCREF VSSD(HW) OSCIO Cosc 100 nF OSCIO VSSD(HW) OSCREF Rosc 39 kΩ 010aaa138 Fig 10. Master/slave concept in two-chip application TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 28 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 14.7 Thermal behavior (printed-circuit board considerations) The heat sink in an application with a TDA8933 is made using the copper on the printed-circuit board. The TDA8933 uses the four corner leads (pins 1, 16, 17 and 32) for heat transfer from the die to the PCB. The thermal foldback will limit the maximum junction temperature to 140 °C. Equation 10 shows the relation between the maximum allowable power dissipation P and the thermal resistance from junction to ambient. T j ( max ) – T amb R th ( j – a ) = ----------------------------------P (10) Where: Rth(j-a) = thermal resistance from junction to ambient (K/W) Tj(max) = maximum junction temperature (°C) Tamb = ambient temperature (°C) P = power dissipation (W), which is determined by the efficiency of the TDA8933 The power dissipation is shown in Figure 21 (SE) and Figure 33 (BTL). The thermal resistance, Rth(j-a), of a 2 layer application board (55 mm × 45 mm), 35 µm copper, FR4 base material in free air with natural convection, is 44 K/W (typ.). 14.8 Pumping effects When the amplifier is used in an SE configuration, a so-called ‘pumping effect’ can occur. During one switching interval, energy is taken from one supply (e.g. VDDP1), while a part of that energy is delivered back to the other supply line (e.g. VSSP1), and vice versa. When the power supply cannot sink energy, the voltage across the output capacitors of that power supply will increase. The voltage increase caused by the pumping effect depends on: • • • • • Speaker impedance Supply voltage Audio signal frequency Value of decoupling capacitors on supply lines Source and sink currents of other channels The pumping effect should not cause a malfunction of either the audio amplifier or the power supply. For instance, this malfunction can be caused by triggering of the undervoltage or overvoltage protection of the amplifier. Pumping effects in an SE configuration can be minimized by connecting audio inputs in anti-phase and changing the polarity of one speaker, as shown in Figure 11. TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 29 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier IN1P OUT1 audio in1 IN1N IN2N OUT2 audio in2 IN2P 010aaa140 Fig 11. SE application for reducing pumping effect 14.9 SE curves measured in the reference design 010aaa158 102 THD+N (%) 10 1 10−1 (1) (3) 10−2 (2) 10−3 10−2 10−1 1 102 10 Po (W/channel) (1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz a. VP = 25 V; RL = 2 × 8 Ω Fig 12. Total harmonic distortion-plus-noise as a function of output power TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 30 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa156 102 THD+N (%) 10 1 10−1 (1) (3) (2) 10−2 10−3 10−2 10−1 1 102 10 Po (W/channel) (1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz a. VP = 17 V; RL = 2 × 4 Ω Fig 13. Total harmonic distortion-plus-noise as a function of output power 010aaa159 102 THD+N (%) 10 1 (1) (2) 10−1 10−2 10−3 10 102 103 104 105 fi (Hz) (1) Po = 7 W (2) Po = 1 W a. VP = 25 V; RL = 2 × 8 Ω Fig 14. Total harmonic distortion-plus-noise as a function of frequency TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 31 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa160 102 THD+N (%) 10 1 (1) (2) 10−1 10−2 10−3 102 10 103 104 105 fi (Hz) (1) Po = 5 W (2) Po = 1 W a. VP = 17 V; RL = 2 × 4 Ω Fig 15. Total harmonic distortion-plus-noise as a function of frequency 010aaa146 35 010aaa155 0 Gv (dB) SVRR (dB) 30 −20 (2) 25 −40 (1) 20 (2) −60 (1) 15 10 10 102 103 104 105 −80 10 102 103 fi (Hz) Po = 1 W (RMS) (1) VP = 17 V; RL = 2 × 4 Ω; CSE = 1000 µF (2) VP = 25 V; RL = 2 × 8 Ω; CSE = 1000 µF Fig 16. Gain as a function of frequency 105 fi (Hz) Vripple = 500 mV (RMS) referenced to ground; Ri = 0 Ω (shorted input) (1) VP = 17 V; RL = 2 × 4 Ω (2) VP = 25 V; RL = 2 × 8 Ω Fig 17. Supply voltage ripple rejection as a function of frequency TDA8933_1 Preliminary data sheet 104 © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 32 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa148 120 010aaa153 −20 αcs (dB) S/N (dB) −40 80 −60 (1) 40 (2) −80 0 10−2 10−1 10 102 Po (W/channel) 1 −100 10 102 103 Po = 1 W; CHVPREF = 47 µF (1) RL = 2 × 4 Ω; VP = 17 V (1) VP = 17 V; RL = 2 × 4 Ω (2) RL = 2 × 8 Ω; VP = 25 V (2) VP = 25 V; RL = 2 × 8 Ω Fig 18. Signal-to-noise ratio as a function of output power 010aaa149 Fig 19. Channel separation as a function of frequency 010aaa152 3.0 (2) ηpo (%) 105 fi (Hz) Ri = 0 Ω; 20 kHz brick wall filter AES17 100 104 (1) P (W) (1) (2) 75 2.0 50 1.0 25 0.0 10−2 10−1 1 10 102 Po (W/channel) 0 0 5 10 15 Po (W/channel) ηpo = (2 × Po) / (2 × Po + P) Power dissipation in junction only. (1) VP = 17 V; RL = 2 × 4 Ω; fi = 1 kHz (1) VP = 17 V; RL = 2 × 4 Ω; fi = 1 kHz (2) VP = 25 V; RL = 2 × 8 Ω; fi = 1 kHz (2) VP = 25 V; RL = 2 × 8 Ω; fi = 1 kHz Fig 20. Output power efficiency as a function of output power Fig 21. Power dissipation as a function of output power per channel (two channels driven) TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 33 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa206 20 010aaa207 5.0 P (W) Po (W) (2) 4.0 15 (1) (1) 3.0 (2) (3) 10 (4) 2.0 5 1.0 0.0 0 10 20 30 10 40 18 26 34 42 VP (V) VP (V) fi = 1 kHz fi = 1 kHz; power dissipation in junction only; short time PO at THD+N = 10 % (1) RL = 2 × 8 Ω SE; THD = 10 % (1) RL = 2 × 4 Ω SE (2) RL = 2 × 8 Ω SE; THD = 0.5 % (2) RL = 2 × 8 Ω SE (3) RL = 2 × 4 Ω SE; THD = 10 % (4) RL = 2 × 4 Ω SE; THD = 0.5 % Fig 22. Output power per channel as a function of supply voltage 010aaa205 20 010aaa229 10 Po (W/channel) 16 Fig 23. Power dissipation as a function of supply voltage Po (W/channel) (1) 8 (2) 12 6 (1) 8 4 4 2 0 0 0 150 300 450 600 0 150 300 time (s) 450 600 time (s) (1) VP = 25 V (1) VP = 17 V (2) VP = 31 V 2 layer application board (55 mm × 45 mm), 35 µ copper, FR4 base material in free air with natural convection. a. RL = 2 × 8 Ω SE; fi = 1 kHz b. RL = 2 × 4 Ω SE; fi = 1 kHz Fig 24. Output power as a function of time TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 34 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa227 4 Vo (V) OPERATING 3 2 1 SLEEP 0 0 0.5 1 1.5 2 2.5 3 VPOWERUP (V) fi = 1 kHz; Vi = 100 mV; VENGAGE > 3 V Fig 25. Output voltage as a function of voltage on pin POWERUP 010aaa228 4 Vo (V) OPERATING 3 2 1 MUTE 0 0 0.5 1 1.5 2 2.5 3 VENGAGE (V) fi = 1 kHz; Vi = 100 mV Fig 26. Output voltage as a function of voltage on pin ENGAGE TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 35 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 14.10 BTL curves measured in the reference design 010aaa157 102 THD+N (%) 10 1 10−1 (1) 10−2 (2) (3) 10−3 10−2 10−1 1 102 10 Po (W) (1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz a. VP = 17 V; RL = 8 Ω Fig 27. Total harmonic distortion-plus-noise as a function of output power 010aaa161 102 THD+N (%) 10 1 (1) 10−1 (2) 10−2 (3) 10−3 10−2 10−1 1 102 10 Po (W) (1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz a. VP = 25 V; RL = 16 Ω Fig 28. Total harmonic distortion-plus-noise as a function of output power TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 36 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa162 102 THD+N (%) 10 1 10−1 (1) 10−2 (2) 10−3 102 10 103 104 105 fi (Hz) (1) Po = 10 W (2) Po = 1 W a. VP = 17 V; RL = 8 Ω Fig 29. Total harmonic distortion-plus-noise as a function of frequency 010aaa163 102 THD+N (%) 10 1 10−1 (1) 10−2 (2) 10−3 10 102 103 104 105 fi (Hz) (1) Po = 10 W (2) Po = 1 W a. VP = 25 V; RL = 16 Ω Fig 30. Total harmonic distortion-plus-noise as a function of frequency TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 37 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa154 45 Gv (dB) (1) 35 (2) 25 15 102 10 103 104 105 fi (Hz) Po = 1 W (RMS) (1) VP = 17 V; RL = 8 Ω (2) VP = 25 V; RL = 16 Ω Fig 31. Gain as a function of frequency 010aaa150 100 ηpo (%) 010aaa151 3.0 (2) P (W) (1) (1) 75 2.0 (2) 50 1.0 25 0 0 10 20 30 0.0 10−2 10−1 1 Po (W) ηpo = Po / (Po + P) Power dissipation in junction only. (1) VP = 17 V; RL = 8 Ω; fi = 1 kHz (1) VP = 17 V; RL = 8 Ω; fi = 1 kHz (2) VP = 25 V; RL = 16 Ω; fi = 1 kHz (2) VP = 25 V; RL = 16 Ω; fi = 1 kHz Fig 32. Output power efficiency as a function of output power Fig 33. Power dissipation as a function of output power TDA8933_1 Preliminary data sheet 10 102 Po (W/channel) © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 38 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 010aaa208 40 010aaa210 5.0 P (W) Po (W) 4.0 30 (2) (1) 3.0 (2) 20 (1) (3) 2.0 (4) 10 1.0 0 0.0 10 15 20 25 30 35 10 18 26 34 VP (P) 42 VP (V) fi = 1 kHz fi = 1 kHz; power dissipation in junction only; short time PO at THD+N = 10 % (1) RL = 16 Ω BTL; THD = 10 % (1) RL = 8 Ω BTL (2) RL = 16 Ω BTL; THD = 0.5 % (2) RL = 16 Ω BTL (3) RL = 8 Ω BTL; THD = 10 % (4) RL = 8 Ω BTL; THD = 0.5 % Fig 34. Output power as a function of supply voltage 010aaa209 32 Fig 35. Power dissipation as a function of supply voltage 010aaa230 20 (2) Po (W) Po (W) (1) 16 24 (1) 12 16 8 8 4 0 0 0 120 240 360 480 600 time (s) (1) VP = 25 V 0 150 300 450 600 time (s) (1) VP = 17 V (2) VP = 31 V 2 layer application board (55 mm × 45 mm), 35 µ copper, FR4 base material in free air with natural convection. a. RL = 16 Ω BTL; fi = 1 kHz b. RL = 8 Ω BTL; fi = 1 kHz Fig 36. Output power as a function of time TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 39 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 14.11 Typical application schematics (simplified) VSSD(HW) VSSA Cin 470 nF IN1P + IN1N − Cin 470 nF DIAG ENGAGE MUTE CONTROL Cen 470 nF POWERUP SLEEP CONTROL CGND VDDA Cosc 100 nF VSSA Rosc VSSA VDDA VSSA OSCREF 39 Ω HVPREF INREF Cinref 100 nF Cin 470 nF TEST IN2N + IN2P − Cin 470 nF VSSA VSSD(HW) 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 U1 9 10 11 TDA8933 24 23 22 12 21 13 20 14 19 15 18 16 17 VSSD(HW) VSSA OSCIO HVP1 VDDP1 VDD VSS Rbo BOOT1 OUT1 Cvssp 100 nF Cvddp 100 nF Cbo 1 M 15 nF Csn 470 pF Rsn 10 Ω LIc VSSP1 + CIc − STAB1 STAB2 VSSP2 Cstab 100 nF VSS BOOT2 Cbo 15 nF Rbo Rsn 10 Ω CIc + 1M VDDP2 HVP2 − LIc OUT2 VDD Cvddp 100 nF VSS Cvssp 100 nF Csn 470 pF DREF VSSD(HW) Cdref 100 nF VSSA VDD Rvdda VDD 10 Ω VDDA Cvddp 220 µF/25 V Cvdda 100 nF GND Rvssa VSS 10 Ω Cvssa 100 nF VSSA Cvssp 220 µF/25 V VSS 010aaa142 Fig 37. Typical simplified application diagram for 2 × SE (symmetrical supply) TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 40 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier VSSA Cin 470 nF VSSD(HW) IN1P + IN1N − Cin 470 nF DIAG MUTE CONTROL ENGAGE Cen 470 nF POWERUP 32 2 31 3 30 4 29 5 28 6 27 7 26 CGND SLEEP CONTROL Cosc 100 nF VDDA VDDA VSSA VSSA Rosc VSSA 1 OSCREF 39 Ω HVPREF INREF Cinref 100 nF TEST IN2N IN2P VSSA VSSD(HW) 8 9 U1 TDA8933 10 25 24 23 11 22 12 21 13 20 14 19 15 18 16 17 VSSD(HW) VSSA OSCIO HVP1 VDDP1 Cvddp 100 nF VDD Csn 470 pF VSS Rbo BOOT1 OUT1 Cvssp 100 nF Rsn 10 Ω Cbo 1 M 15 nF LIc VSSP1 CIc STAB1 + STAB2 VSSP2 − Cstab 100 nF VSS BOOT2 VDDP2 HVP2 CIc LIc OUT2 Cbo 15 nF Rbo Rsn 10 Ω 1M VDD Cvddp 100 nF VSS Cvssp 100 nF Csn 470 pF DREF VSSD(HW) Cdref VSSA VDD Rvdda VDD 10 Ω VDDA Cvdda 100 nF Cvddp 220 µF/25 V GND Rvssa VSS 10 Ω Cvssa 100 nF VSSA Cvssp 220 µF/25 V 010aaa141 VSS Fig 38. Typical simplified application diagram for 1 × BTL (symmetrical supply) TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 41 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier VP Rvdda VP VPA 10 Ω Cvdda 100 nF Cvddp 220 µF/35 V GND VSSD(HW) Cin 470 nF IN1P + IN1N − Cin 470 nF MUTE CONTROL DIAG ENGAGE Cen 470 nF POWERUP SLEEP CONTROL CGND VPA Cosc 100 nF VSSA Rosc HVPREF Chvp 100 nF Cinref 100 nF Cin 470 nF + INREF TEST IN2N IN2P − Cin 470 nF 32 2 31 3 30 4 29 5 28 6 27 7 26 8 VSSD(HW) 25 U1 9 OSCREF 10 39 Ω Chvpref 47 µF/25 V VDDA 1 TDA8933 24 23 11 22 12 21 13 20 14 19 15 18 16 17 VSSD(HW) OSCIO HVP1 Chvp 100 nF HVP1 Cvddp 100 nF VDDP1 BOOT1 OUT1 VP Rbo Cbo 1 M 15 nF Csn 470pF Rsn 10 Ω LIc + − VSSP1 HVP1 CIc STAB1 Cse STAB2 VSSP2 Cstab 100 nF LIc OUT2 BOOT2 VDDP2 Cbo 15 nF Rbo + Rsn 10 Ω HVP2 1M CIc Cse VP Cvddp 100 nF HVP2 DREF VSSD(HW) − Csn 470 pF HVP2 Cdref 100 nF Chvp 100 nF 010aaa193 Fig 39. Typical simplified application diagram for 2 × SE (asymmetrical supply) TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 42 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier VP Rvdda VP VPA 10 Ω Cvdda 100 nF Cvddp 220 µF/35 V GND VSSD(HW) Cin 470 nF IN1P + IN1N − Cin 470 nF DIAG MUTE CONTROL ENGAGE Cen 470 nF POWERUP SLEEP CONTROL Cosc 100 nF CGND VPA VDDA VSSA Rosc OSCREF 39 Ω HVPREF HVPREF Chvp 100 nF INREF Cinref 100 nF TEST IN2N IN2P VSSD(HW) 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 VSSD(HW) OSCIO HVP1 VDDP1 BOOT1 OUT1 Chvp 100 nF HVPREF Rhvp Cvddp 100 nF 470 Ω VP Rbo Cbo 1 M 15 nF Csn 470 pF Rsn 10 Ω LIc VSSP1 Clc U1 9 TDA8933 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 STAB1 + − STAB2 VSSP2 Cstab 100 nF Clc LIc OUT2 BOOT2 VDDP2 Cbo 15 nF Rbo 1M VP Cvddp 100 nF HVP2 Csn 470 pF Rhvp DREF VSSD(HW) Rsn 10 Ω Cdref 100 nF Chvp 470 Ω 100 nF HVPREF 010aaa194 Fig 40. Typical simplified application diagram for 1 × BTL (asymmetrical supply) TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 43 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 15. Package outline SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.2 1.0 0.25 0.25 0.1 0.95 0.55 0.01 0.02 0.01 0.011 0.007 0.81 0.80 0.30 0.29 0.05 0.419 0.394 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.055 0.016 0.047 0.039 0.01 0.01 0.037 0.004 0.022 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-08-17 03-02-19 MO-119 Fig 41. Package outline SOT287-1 (SO32) TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 44 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 16. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA8933_1 20070515 Preliminary data sheet - - TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 45 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] TDA8933_1 Preliminary data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 15 May 2007 46 of 47 TDA8933 NXP Semiconductors Class-D audio amplifier 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.7 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 15 16 17 17.1 17.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mode selection and interfacing . . . . . . . . . . . . . 7 Pulse width modulation frequency . . . . . . . . . . 8 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal Foldback (TF) . . . . . . . . . . . . . . . . . . 10 OverTemperature Protection (OTP) . . . . . . . . 10 OverCurrent Protection (OCP) . . . . . . . . . . . . 10 Window Protection (WP). . . . . . . . . . . . . . . . . 10 Supply voltage protections . . . . . . . . . . . . . . . 10 Diagnostic input and output . . . . . . . . . . . . . . 12 Differential inputs . . . . . . . . . . . . . . . . . . . . . . 12 Output voltage buffers. . . . . . . . . . . . . . . . . . . 13 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 14 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal characteristics. . . . . . . . . . . . . . . . . . 18 Static characteristics. . . . . . . . . . . . . . . . . . . . 19 Dynamic characteristics . . . . . . . . . . . . . . . . . 21 Application information. . . . . . . . . . . . . . . . . . 24 Output power estimation. . . . . . . . . . . . . . . . . 24 Output current limiting. . . . . . . . . . . . . . . . . . . 26 Speaker configuration and impedance . . . . . . 26 Single-ended capacitor . . . . . . . . . . . . . . . . . . 27 Gain reduction . . . . . . . . . . . . . . . . . . . . . . . . 27 Device synchronization . . . . . . . . . . . . . . . . . . 28 Thermal behavior (printed-circuit board considerations) . . . . . . . . . . . . . . . . . . . . . . . . 29 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 29 SE curves measured in the reference design. 30 BTL curves measured in the reference design 36 Typical application schematics (simplified) . . . 40 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 44 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 45 Legal information. . . . . . . . . . . . . . . . . . . . . . . 46 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 17.3 17.4 18 19 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 46 46 47 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 May 2007 Document identifier: TDA8933_1