Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 The 74ABT853 is an octal transceiver with a parity generator/checker and is intended for bus–oriented applications. FEATURES • Low static and dynamic power dissipation with high speed and high output drive When Output Enable A (OEA) is High, it will place the A outputs in a high impedance state. Output Enable B (OEB) controls the B outputs in the same way. • Open-collector ERROR output • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 The parity generator creates an odd parity output (PARITY) when OEB is Low. When OEA is Low, the parity of the B port, including the PARITY input, is checked for odd parity. When an error is detected, the error data is sent to the input of a latch. The error data can then be passed, stored, cleared, or sampled depending on the ENABLE and CLEAR control signals. and 200 V per Machine Model • Power-up 3-State • Live insertion/extraction permitted If both OEA and OEB are Low, data will flow from the A bus to the B bus and the part is forced into an error condition which creates an inverted PARITY output. This error condition can be used by the designer for system diagnostics. DESCRIPTION The 74ABT853 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25°C; GND = 0V TYPICAL UNIT tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF; VCC = 5V 3.4 ns tPLH tPHL Propagation delay An to PARITY CL = 50pF; VCC = 5V 7.4 ns pF CIN Input capacitance CI/O I/O capacitance ICCZ Total supply current VI = 0V or VCC 4 Outputs disabled; VO = 0V or VCC 7 pF Outputs disabled; VCC =5.5V 50 µA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP PACKAGES –40°C to +85°C 74ABT853 N 74ABT853 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT853 D 74ABT853 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT853 DB 74ABT853 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT853 PW 74ABT853PW DH SOT355-1 PIN CONFIGURATION OEA 1 LOGIC SYMBOL 24 V CC A0 2 23 B0 A1 3 22 B1 A2 4 21 B2 A3 5 20 B3 A4 6 19 B4 A5 7 18 B5 A6 8 17 B6 2 A7 9 15 PARITY CLEAR 11 14 OEB GND 12 4 5 6 7 8 9 A0 A1 A2 A3 A4 A5 A6 A7 16 B7 ERROR 10 3 14 OEB 1 OEA PARITY 15 11 CLEAR ERROR 10 13 ENABLE B0 B1 B2 B3 B4 B5 B6 B7 23 22 21 20 19 18 17 16 13 ENABLE TOP VIEW SA00263 SA00262 1995 Sep 06 1 853-1672 15702 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 PIN DESCRIPTION SYMBOL PIN NUMBER A0 – A7 2, 3, 4, 5, 6, 7, 8, 9 A port 3–State inputs/outputs NAME AND FUNCTION B0 – B7 23, 22, 21, 20, 19, 18, 17, 16 B port 3–State inputs/outputs OEA 1 Enables the A outputs when Low OEB 14 Enables the B outputs when Low PARITY 15 Parity output/input ERROR 10 Error output (open collector) CLEAR 11 Clears the error flag register when Low ENABLE 13 Enable input (active-Low) GND 12 Ground (0V) VCC 24 Positive supply voltage FUNCTION TABLE INPUTS OUTPUTS OEB OEA An Σ OF HIGHS Bn + PARITY Σ OF HIGHS An Bn PARITY A data to B bus and generate odd parity output L H Odd Even (output) (input) An L H B data to A bus and check for parity error1 H L (output) X Bn (input) (input) H H X X Z Z Z L Odd Even An H L MODE A bus and B bus disabled2 A data to B bus and generate inverted parity output L (output) (input) NOTES: 1. Error checking is detailed in the Error Flag Function Table below. 2. When ENABLE is Low, ERROR is Low if the sum of A inputs is even or ERROR is High if the sum of A inputs is odd. ERROR FLAG FUNCTION TABLE INPUTS = = = = OUTPUT MODE ENABLE CLEAR Bn + PARITY Σ OF HIGHS POINT ”P” PRE–STATE ERRORn–1 ERROR OUTPUT Pass L L Odd Even H L X H L Sample L H Odd Even X H L X H X L H L L Clear H L X X X H X L H L H Store H L X Z INTERNAL NODE H H X High voltage level steady state Low voltage level steady state Don’t care High impedance ”off” state 1995 Sep 06 2 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 LOGIC DIAGRAM 8 8 A0 – A7 B0 – B7 8 OEB PARITY OEA 8 8 MUX } } B 9 9–bit Odd Parity Tree ”P” A Sel A/B ERROR ENABLE CLEAR SA00264 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1995 Sep 06 3 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT MIN MAX 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 5 ns/V –40 +85 °C 2.0 ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range V DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK Input clamp voltage VOH High–level output voltage All outputs except ERROR VOL II Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 3.5 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 4.0 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.6 2.0 V Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current3 VCC = 2.1V; VO = 0.5V; VI = GND or VCC; V OE = Don’t care ±5.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA IOFF IPU/PD IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –100 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC –50 0.5 250 –50 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 25 38 38 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 0.5 50 50 µA Outputs enabled, one input at 3.4V, other inputs at VCC or GND; VCC = 5.5V 0.5 1.5 1.5 mA Outputs 3-State, one data input at 3.4V, other inputs at VCC or GND; VCC = 5.5V 0.01 50 50 µA Outputs 3-State, one enable input at 3.4V, other inputs at VCC or GND; VCC = 5.5V 0.5 1.5 1.5 mA NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a transition time of up to 100µsec is permitted. The ERROR output pin 10 is not included in this spec due to the open collector design. 1995 Sep 06 4 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25oC VCC = +5.0V WAVEFORMS Tamb = –40 to +85oC VCC = +5.0V ±10% UNIT Min Typ Max Min Max 4 1.2 1.0 3.4 2.6 4.8 4.0 1.2 1.0 5.3 4.5 ns Propagation delay An to PARITY 1, 4 2.1 2.5 7.4 7.4 9.5 9.7 2.1 2.5 11.2 11.0 ns tPLH tPHL Propagation delay OEA to PARITY 1, 4 1.8 2.3 6.6 6.7 8.5 8.6 1.8 2.3 10.5 10.0 ns tPLH Propagation delay CLEAR to ERROR 3 1.0 3.6 5.5 1.0 6.2 ns tPLH tPHL Propagation delay ENABLE to ERROR 4 1.8 1.8 3.8 4.5 5.1 5.8 1.8 1.8 6.0 6.6 ns tPLH tPHL Propagation delay Bn or PARITY to ERROR 1, 4 2.0 3.0 7.9 9.0 10.1 11.5 2.0 3.0 11.7 12.8 ns tPZH tPZL Output enable time OEA to An or OEB to Bn, PARITY 2, 5 1.0 2.1 3.2 4.1 5.1 5.8 1.0 2.1 6.2 6.7 ns tPHZ tPLZ Output disable time OEA to An or OEB to Bn, PARITY 2, 5 3.1 3.2 5.1 5.6 7.3 7.2 3.1 3.2 7.9 8.1 ns tPLH tPHL Propagation delay An to Bn or Bn to An tPLH tPHL AC SETUP REQUIREMENTS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER WAVEFORMS +25oC Tamb = VCC = +5.0V Tamb = –40 to +85oC VCC = +5.0V ±10% MIN TYP MIN UNIT ts(H) ts(L) Setup time, High or Low Bn or PARITY to ENABLE 6 8.5 8.5 6.5 3.6 8.5 8.5 ns th(H) th(L) Hold time, High or Low Bn or PARITY to ENABLE 6 0.0 0.0 –3.4 –6.3 0.0 0.0 ns ts(H) Setup time, High CLEAR to ENABLE 6 2.0 –1.6 2.0 ns th(L) Hold time, Low CLEAR to ENABLE 6 3.0 1.8 3.0 ns tw(L) Pulse width, Low CLEAR 3 3.5 1.0 3.5 ns tw(L) Pulse width, Low ENABLE 6 4.0 2.5 4.0 ns 1995 Sep 06 5 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V INPUT VM INPUT VM tPHL VM VM tPLH tPLH VM OUTPUT tPHL VM VM VM OUTPUT SA00216 Waveform 1. Propagation Delay For Inverting Output SA00023 Waveform 4. Propagation Delay For Non-Inverting Output OEA, OEB VM VM tPHZ tPZH OEA, OEB VOH –0.3V tPZL VM OUTPUT VM VM tPLZ 0V VM OUTPUT SA00238 VOL +0.3V Waveform 2. 3-State Output Enable Time to High Level and Output Disable Time from High Level 0V SA00239 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level CLEAR VM ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉ VM CLEAR, Bn, PARITY tw(L) ERROR VM VM VM ts(H) VM th(H) VM ts(L) th(L) tw(L) tPLH ENABLE SA00265 VM VM VM Waveform 3. CLEAR Pulse Width and CLEAR to ERROR Delay NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00266 Waveform 6. Data Setup and Hold Times and ENABLE Pulse Width 1995 Sep 06 6 Philips Semiconductors Product specification 8-bit transceiver with 9-bit parity checker/ generator and flag latch (3-State) 74ABT853 TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS 18 16 14 Propagation delay (ns) 12 tPLH 10 8 6 4 tPHL 2 0 0 100 200 300 400 500 600 Load resistor (Ω) NOTE: When using Open-Collector parts, the value of the pull–up resistor greatly affects the value of the tPLH. For example, changing the specified pull-up resistor value from 500Ω to 100Ω will improve the tPLH over 300% with only a slight change in the tPHL. However, if the value of the pull-up resistor is changed, the user must make certain that the total IOL current through the resistor and the total IIL’s of the receivers does not exceed the IOL maximum specification. SA00241 TEST CIRCUIT AND WAVEFORM VCC VX VOUT VIN PULSE GENERATOR tW 90% 90% VM NEGATIVE PULSE VM 10% RX 10% 0V D.U.T tTLH (tR) tTHL (tF) RT tTLH (tR) RL CL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION LOAD VALUES TEST SWITCH OUTPUT RX tPLZ closed ERROR 100Ω VCC tPZL closed All other 500Ω 7.0V All other open AMP (V) 0V VM = 1.5V Input Pulse Definition VX INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns RT = Termination resistance should be equal to ZOUT of pulse generators. SA00242 1995 Sep 06 7