PHILIPS 74ABT834

Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
sent to the input of a storage register. If a
Low–to–High transition happens at the clock
input (CP), the error data is stored in the
register and the Open–collector error flag
(ERROR) will go Low. The error flag register
is cleared with a Low pulse on the CLEAR
input.
power dissipation with high speed and high
output drive.
FEATURES
• Low static and dynamic power dissipation
The 74ABT834 is an octal inverting
transceiver with a parity generator/checker
and is intended for bus–oriented applications.
with high speed and high output drive
• Open–collector ERROR output
• Output capability: +64mA/–32mA
• Latch–up protection exceeds 500mA per
When Output Enable A (OEA) is High, it will
place the A outputs in a high impedance
state. Output Enable B (OEB) controls the B
outputs in the same way.
Jedec JC40.2 Std 17
• ESD protection exceeds 2000 V per MIL
If both OEA and OEB are Low, data will flow
from the A bus to the B bus and the part is
forced into an error condition which creates
an inverted PARITY output. This error
condition can be used by the designer for
system diagnostics.
The parity generator creates an odd parity
output (PARITY) when OEB is Low. When
OEA is Low, the parity of the B port, including
the PARITY input, is checked for odd parity.
When an error is detected, the error data is
STD 883C Method 3015.6 and 200 V per
Machine Model
• Power up/down 3–State
DESCRIPTION
The 74ABT834 high–performance BiCMOS
device combines low static and dynamic
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
CL = 50pF; VCC = 5V
3.4
ns
tPLH
tPHL
Propagation delay
An to PARITY
CL = 50pF; VCC = 5V
7.4
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
COUT
Output capacitance
VI = 0V or VCC
7
pF
ICCZ
Total supply current
Outputs disabled; VCC =5.5V
50
µA
ORDERING INFORMATION
PACKAGES
CONDITIONS
Tamb = 25°C; GND = 0V
ORDER CODE
24–pin plastic DIP (300mil)
–40°C to +85°C
74ABT834N
24–pin plastic SOL (300mil)
–40°C to +85°C
74ABT834D
PIN CONFIGURATION
OEA
LOGIC SYMBOL
24 V
CC
1
A0 2
23 B0
A1 3
22 B1
A2 4
21 B2
A3 5
20 B3
A4 6
19 B4
A5 7
18 B5
A6 8
17 B6
A7 9
16 B7
ERROR 10
15 PARITY
CLEAR 11
14 OEB
GND 12
2
4
5
6
7
8
9
A0 A1 A2 A3 A4 A5 A6 A7
14
OEB
1
OEA
PARITY
15
11
CLEAR
ERROR
10
13
CP
B0 B1 B2 B3 B4 B5 B6 B7
23 22 21 20 19 18 17 16
13 CP
TOP VIEW
June 9, 1992
3
1
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
PIN DESCRIPTION
SYMBOL
PIN NUMBER
NAME AND FUNCTION
A0 – A7
2, 3, 4, 5,
6, 7, 8, 9
A port 3–State inputs/outputs
B0 – B7
23, 22, 21, 20,
19, 18, 17, 16
B port 3–State inputs/outputs
OEA
1
Enables the A outputs when Low
OEB
14
Enables the B outputs when Low
PARITY
15
Parity output
ERROR
10
Error output
CLEAR
11
Clears the error flag register when Low
CP
13
Clock input
GND
12
Ground (0V)
VCC
24
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
OEB
OEA
An
Σ of Highs
A data to B bus and generate odd parity
output
L
H
Odd
Even
NA
(output)
NA
(input)
An
H
L
B data to A bus and check for parity error1
H
L
NA
(output)
Odd
Even
Bn
NA
(input)
NA
(input)
A bus and B bus disabled2
H
H
X
X
Z
Z
Z
A data to B bus and generate inverted
parity output
L
L
Odd
Even
NA
(output)
NA
(input)
An
L
H
MODE
Bn + Parity
Σ of Lows
An
Bn
PARITY
NOTES:
1. Error checking is detailed in the Error Flag Function Table below.
2. When clocked, the error output is Low if the sum of A inputs is even or High if the sum of A inputs is odd.
ERROR FLAG FUNCTION TABLE
INPUTS
Internal node
Output
CLEAR
CP
Bn + Parity
Σ of Lows
Point ”P”
Pre–state
ERRORn–1
ERROR
OUTPUT
Sample
H
H
H
↑
↑
X
Odd
Even
X
H
L
X
H
X
L
H
L
L
Hold
H
↑
X
X
X
NC
Clear
L
X
X
X
X
H
MODE
H
L
X
NA
NC
Z
↑
↑
=
=
=
=
=
=
=
=
High voltage level steady state
Low voltage level steady state
Don’t care
Not applicable
No change
High impedance ”off” state
Low–to–High clock transition
Not a Low–to–High clock transition
June 9, 1992
2
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
LOGIC DIAGRAM
8
8
A0 – A7
B0 – B7
8
OEB
PARITY
OEA
8
8
MUX
}
}
B
9
9–bit
Odd
Parity
Tree
”P”
A
Sel A/B
D
ERROR
CP
CLEAR
R
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
SYMBOL
VCC
IIK
CONDITIONS
RATING
UNIT
–0.5 to +7.0
V
–18
mA
–1.2 to +7.0
V
VO < 0
–50
mA
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
VOUT
DC output voltage3
output in Off or High state
–0.5 to +5.5
V
IOUT
DC output current
output in Low state
128
mA
Tstg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
2. The performance capability of a high–performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
June 9, 1992
3
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
LIMITS
DC supply voltage
UNIT
Min
Max
4.5
5.5
V
0
VCC
V
VI
Input voltage
VIH
High–level input voltage
VIL
Input voltage
0.8
V
VOH
High–level output voltage, ERROR
5.5
V
IOH
High–level output current
–32
mA
IOL
Low–level output current
64
mA
0
5
ns/V
–40
+85
°C
2.0
∆t/∆v
Input transition rise or fall rate
Tamb
Operating free–air temperature range
V
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
VIK
Input clamp voltage
VCC = 4.5V; IIK = –18mA
IOH
High–level output current
ERROR ONLY
VCC = 5.5V; VOH = 5.5V; VI = VIL or VIH
VOH
VOL
II
High–level output voltage
Tamb = –40°C
to +85°C
Tamb = +25°C
Min
UNIT
Typ
Max
Max
–0.9
–1.2
–1.2
V
20
20
µA
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
2.5
3.5
2.5
V
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
3.0
4.0
3.0
V
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
2.0
2.6
2.0
V
Low–level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
0.42
Input leakage
Control pins
VCC = 5.5V; VI = GND or 5.5V
±0.01
current
Data pins
VCC = 5.5V; VI = GND or 5.5V
±5
0.55
0.55
V
±1.0
±1.0
µA
±100
±100
µA
IIH + IOZH
3–State output High current
VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
5.0
50
50
µA
IIL + IOZL
3–State output Low current
VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
–5.0
–50
–50
µA
Output current1
VCC = 5.5V; VO = 2.5V
–80
–180
–180
mA
VCC = 5.5V; Outputs High, VI = GND or VCC
50
250
250
µA
VCC = 5.5V; Outputs Low, VI = GND or VCC
20
30
30
mA
VCC = 5.5V; Outputs 3–State;
VI = GND or VCC
50
250
250
µA
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND
0.3
1.5
1.5
mA
IO
ICCH
ICCL
Quiescent supply current
ICCZ
∆ICC
Additional supply current per
input pin2
–50
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
June 9, 1992
4
–50
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25oC
VCC = +5.0V
WAVEFORMS
Min
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
tPLH
tPHL
Typ
Tamb = –40 to +85oC
VCC = +5.0V ±10%
Max
Min
UNIT
Max
2
ns
Propagation delay
An to PARITY
1, 2
ns
tPLH
tPHL
Propagation delay
OEA to PARITY
1, 2
ns
tPLH
Propagation delay
CLEAR to ERROR
5
ns
tPHL
Propagation delay
CP to ERROR
1
ns
tPZH
tPZL
Output enable time
OEA to An or OEB to Bn, PARITY
3, 4
ns
tPHZ
tPLZ
Output disable time
OEA to An or OEB to Bn, PARITY
3, 4
ns
AC SETUP REQUIREMENTS
GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = +25oC
VCC = +5.0V
WAVEFORMS
Min
Typ
Tamb = –40 to +85oC
VCC = +5.0V ±10%
Max
Min
UNIT
Max
ts(H)
ts(L)
Setup time, High or Low
Bn or PARITY to CP
6
ns
th(H)
th(L)
Hold time, High or Low
Bn or PARITY to CP
6
ns
tw(H)
tw(L)
Pulse width, High or Low
CP
6
ns
tw(L)
Pulse width, Low
CLEAR
5
ns
Recovery time
CLEAR to CP
5
ns
trec
June 9, 1992
5
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
INPUT
VM
INPUT
VM
tPHL
tPLH
OUTPUT
VM
VM
OUTPUT
tPHL
OUTPUT
VM
VM
VM
Waveform 2. Propagation Delay For Non–Inverting
Output
OEA, OEB
VM
VM
VM
tPHZ
tPZH
VM
tPLH
Waveform 1. Propagation Delay For Inverting Output
OEA, OEB
VM
tPZL
VOH –0.3V
VM
tPLZ
OUTPUT
VM
VOL +0.3V
0V
0V
Waveform 3. 3–State Output Enable Time to High Level
and Output Disable Time from High Level
CLEAR
VM
Waveform 4. 3–State Output Enable Time to Low Level
and Output Disable Time from Low Level
V
M
tw(L)
VM
CP
tPLH
ERROR
VM
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
tREC
Bn, PARITY
Waveform 5. CLEAR Pulse Width, CLEAR to ERROR
Delay and CLEAR to Clock Recovery Time
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
VM
ts(H)
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉ
VM
VM
th(H)
VM
6
th(L)
tw(L)
VM
VM
Waveform 6. Data Setup and Hold Times and
Clock Pulse Width
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
June 9, 1992
ts(L)
tw(H)
CP
VM
Philips Semiconductors Advanced BiCMOS Products
Objective specification
Octal inverting transceiver with parity
generator/checker (3–State)
74ABT834
TYPICAL PROPAGATION DELAYS VERSUS LOAD FOR OPEN COLLECTOR OUTPUTS
18
16
Propagation delay (ns)
14
12
tPLH
10
8
6
4
tPHL
2
0
0
100
200
300
400
500
600
Load resistor (Ω)
NOTE:
When using Open–Collector parts, the value of the pull–up resistor greatly affects the value of the tPLH. For example, changing the
specified pull–up resistor value from 500Ω to 100Ω will improve the tPLH over 300% with only a slight change in the tPHL. However,
if the value of the pull–up resistor is changed, the user must make certain that the total IOL current through the resistor and the total
IIL’s of the receivers does not exceed the IOL maximum specification.
TEST CIRCUIT AND WAVEFORM
VCC
VX
PULSE
GENERATOR
VIN
tW
90%
VM
NEGATIVE
PULSE
10%
0V
D.U.T
tTHL (tF)
RT
tTLH (tR)
tTLH (tR)
RL
CL
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3–State Outputs
AMP (V)
90%
VM
VM
10%
10%
tW
SWITCH POSITION
LOAD VALUES
TEST
SWITCH
OUTPUT
RX
tPLZ
closed
ERROR
100Ω VCC
tPZL
closed
All other
500Ω 7.0V
All other
open
0V
VM = 1.5V
Input Pulse Definition
VX
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
74ABT
RT = Termination resistance should be equal to ZOUT of
pulse generators.
June 9, 1992
AMP (V)
VM
10%
RX
VOUT
90%
7
Amplitude
Rep. Rate
tW
tR
tF
3.0V
1MHz
500ns
2.5ns
2.5ns