Revised March 2000 74F552 Octal Registered Transceiver with Parity and Flags General Description Features The 74F552 octal transceiver contains two 8-bit registers for temporary storage of data flowing in either direction. Each register has its own clock pulse and clock enable input as well as a flag flip-flop that is set automatically as the register is loaded. The flag output will be reset when the output enable returns to HIGH after reading the output port. Each register has a separate output enable control for its 3-STATE buffer. The separate Clocks, Flags, and Enables provide considerable flexibility as I/O ports for demand-response data transfer. When data is transferred from the A Port to the B Port, a parity bit is generated. On the other hand, when data is transferred from the B Port to the A Port, the parity of input data on B0–B7 is checked. ■ 8-Bit bidirectional I/O Port with handshake ■ Register status flag flip-flops ■ Separate clock enable and output enable ■ Parity generation and parity check ■ B-outputs sink 64 mA ■ 3-STATE outputs Ordering Code: Order Number Package Number Package Description 74F552SC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F552QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for SOIC © 2000 Fairchild Semiconductor Corporation Pin Assignments for PLCC DS009561 www.fairchildsemi.com 74F552 Octal Registered Transceiver with Parity and Flags April 1988 74F552 Logic Symbols IEEE/IEC Unit Loading/Fan Out Pin Names A0–A7 Description A-to-B Port Data Inputs or B-to-A 3-STATE B0–B7 B-to-A Transceiver Inputs or U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 3.5/1.083 70 µA/−0.65 mA 150/40 (33.3) −3 mA/24 mA (20 mA) 3.5/1.083 70 µA/−0.65 mA 600/106.6 (80) −12 mA/64 mA (48 mA) A-to-B 3-STATE Output −1 mA/20 mA FR B Port Flag Output 50/33.3 FS A Port Flag Output 50/33.3 −1 mA/20 mA PARITY Parity Bit Transceiver Input or Output 3.5/1.083 70 µA/−0.65 mA ERROR Parity Check Output (Active LOW) 50/33.3 −1 mA/20 mA CER R Registers Clock Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA 600/106.6 (50) −12 mA/64 mA (48 mA) CES S Registers Clock Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CPR R Registers Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA CPS S Registers Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA OEBR B Port and PARITY Output Enable (Active LOW) 1.0/2.0 20 µA/−1.2 mA 1.0/2.0 20 µA/−1.2 mA and Clear FR Input (Active Rising Edge) OEAS A Port Output Enable (Active LOW) and Clear FS Input (Active Rising Edge) www.fairchildsemi.com 2 Data applied to the A-inputs are entered and stored in the R register on the rising edge of the CPR Clock Pulse, provided that the Clock Enable (CER) is LOW; simultaneously, the status flip-flop is set and the flag (FR) output goes HIGH. As the Clock Enable (CER) returns to HIGH, the data will be held in the R register. These data entered from the A-inputs will appear at the B Port I/O pins after the Output Enable (OEBR) has gone LOW. When OEBR is LOW, a parity bit appears at the PARITY pin, which will be set HIGH when there is an even number of 1s or all 0s at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR by changing the signal at the OEBR pin from LOW-to-HIGH. Data flow from B-to-A proceeds in the same manner described for A-to-B flow. A LOW at the CES pin and a LOW-to-HIGH transition at CPS pin enters the B-input data and the parity-input data into the S registers and the parity register respectively and set the flag output FS to HIGH. A LOW signal at the OEAS pin enables the A Port I/O pins and a LOW-to-HIGH transition of the OEAS signal clears the FS flag. When OEAS is LOW, the parity check output ERROR will be HIGH if there is an odd number of 1s at the Q outputs of the S registers and the parity register. The flag FS can be cleared by a LOW-to-HIGH transition of the OEAS signal. Register Function Table Flag Flip-Flop Function Table (Applies to R or S Register) Inputs (Applies to R or S Flag Flip-Flop) Inputs Flag Internal Function D CP CE Q X H NC L L L H L NC X L H X † H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Function CE CP H Hold Data L Load Data X OE Output X X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Keep Old Data = LOW-to-HIGH Transition † = Not LOW-to-HIGH Transition NC = No Change Output Control † NC † H Hold Flag Set Flag L Clear Flag = LOW-to-HIGH Transition † = Not LOW-to-HIGH Transition NC = No Change Parity Generation Function Internal A or B Q Outputs H X Z Disable Output H X Z L L L Enable Output L 0, 2, 4, 6, 8 H L H H Enable Output L 1, 3, 5, 7 L OE H = HIGH Voltage Level L = LOW Voltage Level Function OEBR Number of HIGHs in the Q Outputs of the R Register H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Parity Output X = Immaterial Z = High Impedance Parity Check Function Number of HIGHs in Parity ERROR the Q Outputs of the S Register Input Output H X X H L 0, 2, 4, 6, 8 L L L 1, 3, 5, 7 L H L 0, 2, 4, 6, 8 H H L 1, 3, 5, 7 H L OEAS H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 3 www.fairchildsemi.com 74F552 Functional Description 74F552 Block Diagram www.fairchildsemi.com 4 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +175°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Min Typ Max 2.0 Voltage VOH VOL IIH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 10% VCC 2.0 5% VCC 2.7 5% VCC 2.7 −1.2 V 0.5 Voltage 10% VCC 0.5 10% VCC 0.55 Input HIGH IIN = −18 mA (CER, CES, CPR, CPS, OEBR, OEAS) Min IOH = −15 mA (Bn, PARITY) IOL = 20 mA (FR, FS, ERROR) V Min IOL = 24 mA (An) IOL = 64 mA (Bn, PARITY) VIN = 2.7V 5.0 µA Max 7.0 µA Max 0.5 mA Max 50 µA Max V 0.0 µA 0.0 mA Max 70 µA Max VOUT = 2.7V (An, B n, PARITY) −650 µA Max VOUT = 0.5V (An, B n, PARITY) mA Max 500 µA 0.0V VOUT = 5.25V (An, Bn, PARITY) VO = HIGH Input HIGH Current Input HIGH Current Output HIGH Input Leakage Min IOH = −3 mA (An, Bn, PARITY) 10% VCC 4.75 Output Leakage 3.75 Circuit Current IIL Recognized as a LOW Signal Output LOW Test IOD V IOH = −1 mA (FR, FS, ERROR, An) Leakage Current VID 0.8 IOH = −3 mA (An, Bn PARITY) Breakdown (I/O) ICEX Conditions Recognized as a HIGH Signal V Breakdown Test IBVIT VCC V IOH = −1 mA (FR, FS, ERROR, An) Current IBVI Units −0.6 Input LOW Current −1.2 IIH + IOZH Output Leakage Current IIL + IOZL Output Leakage Current IOS Output Short- −60 −175 Circuit Current −100 −250 (CER, CES, CPR, CPS, OEBR, OEAS) VIN = 7.0V (CER, CES, CPR, CPS, OEBR, OEAS) VIN = 5.5V (An, Bn, PARITY) VOUT = VCC (FR, FS, ERROR, An, Bn, PARITY) IID = 1.9 µA All other pins grounded VIOD = 150 mV All other pins grounded VIN = 0.5V (CER, CES, CPR, CPS) VIN = 0.5V (OEBR, OEAS) VOUT = 0V (FR, FS, ERROR, An) VOUT = 0V (Bn, PARITY) IZZ Bus Drainage Test ICCH Power Supply Current 100 150 mA Max ICCL Power Supply Current 100 150 mA Max VO = LOW ICCZ Power Supply Current 110 165 mA Max VO = HIGH Z 5 www.fairchildsemi.com 74F552 Absolute Maximum Ratings(Note 1) 74F552 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Units Min Typ Max Min tPLH Propagation Delay 3.5 6.0 8.0 3.0 9.0 tPHL CPS or CPR to An or Bn 4.0 7.0 9.5 3.5 10.5 tPLH Propagation Delay 3.0 5.5 7.5 2.5 8.5 ns 3.5 6.0 8.0 3.0 9.0 ns CPS or CPR to FS or FR tPHL Propagation Delay OEAS to FS Max tPLH Propagation Delay 8.0 14.0 18.0 7.0 20.0 tPHL CPR to Parity 8.5 14.5 18.5 7.5 20.5 tPLH Propagation Delay 8.0 13.5 17.5 7.0 19.5 tPHL CPS to ERROR 7.5 13.0 16.5 6.5 18.5 tPLH Propagation Delay 3.5 6.0 8.0 3.0 9.0 tPHL OEAS to ERROR 3.0 5.0 7.0 2.5 8.0 tPZH Enable Time OEAS 3.0 5.5 7.5 2.5 8.5 tPZL or OEBR to Bn or An 3.5 7.0 9.5 3.0 10.5 tPHZ Disable Time OEAS 3.0 6.5 8.5 2.5 9.5 tPLZ or OEBR to Bn or An 3.0 5.5 7.5 2.5 8.5 tPZH Enable Time 3.0 4.5 7.5 2.5 8.5 tPZL OEBR to Parity 3.5 6.0 9.5 3.0 10.5 tPHZ Disable Time 3.0 5.5 8.5 2.5 9.5 tPLZ OEBR to Parity 3.0 6.5 7.5 2.5 8.5 ns ns ns ns ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 7.5 8.5 tS(L) An or Bn or Parity 4.5 5.0 Hold Time, HIGH or LOW 0 0 An or Bn or Parity 0 0 to CPS or CPR tH(H) tH(L) Units Max ns to CPS or CPR tS(H) Setup, Time HIGH or LOW 6.0 7.0 tS(L) CES or CER to CPS or CPR 10.0 11.5 tH(H) Hold Time, HIGH or LOW 0 0 tH(L) CES or CER to CPS or CPR 0 0 tW(H) Pulse Width, HIGH or LOW 4.0 4.5 tW(L) CPS or CPR 6.0 7.0 www.fairchildsemi.com 6 ns ns 74F552 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M28B 7 www.fairchildsemi.com 74F552 Octal Registered Transceiver with Parity and Flags Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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