INTEGRATED CIRCUITS DATA SHEET PCD5043 DECT burst mode controller Objective specification File under Integrated Circuits, IC17 1996 Oct 31 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 CONTENTS FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.1.1 6.1.2 6.2 6.3 6.3.1 6.3.2 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.7 Internal bus and data memory Internal Bus Data Memory Clock generation and correction Programmable communication controller and program memory PCC PCC functions Speech interface 12-slot mode 32-slot mode Muting Local call RF interface Serial receiver Serial transmitter Seamless handover RF control signals Synthesizer programming RSSI measurement Local call switching Data synchronization Ciphering machine Microcontroller Interface Function of the microcontroller interface Microcontroller interrupts Watchdog Power-down Survey of registers 7 LIMITING VALUES 8 CHARACTERISTICS 9 PACKAGE OUTLINE 10 SOLDERING 10.1 10.2 10.3 10.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 11 DEFINITIONS 12 LIFE SUPPORT APPLICATIONS 1996 Oct 31 2 Philips Semiconductors Objective specification DECT burst mode controller 1 PCD5043 FEATURES 2 GENERAL DESCRIPTION • On-chip pre-programmed Communication Controller with embedded firmware for implementation of Traffic Bearer Control (TBC), MAC message handling, scanning, and control of the device’s other functional units. The PCD5043 DECT Burst Mode Controller (BMC) is a custom IC that performs the DECT Physical Layer and MAC Layer time-critical functions, for use in DECT remote radio transceiver (PABX) products which comply with the following standards: • Fixed Part (FP) modes • DECT CI part 2: Physical layer (DE/RES 3001-2) • TDMA frame (de)multiplexing • DECT CI part 3 : Medium Access Control layer (DE/RES 3001-3) • Encryption • DECT CI part 7: Security features for DECT (DE/RES 3001-7) • Scrambling • CRC generation and checking • DECT CI part 9: Public Access Profile (DE/RES 3001-9). • Beacon transmission control (by P00 packets) • Switches up to12 active speech channels from speech interface to 1152 kbits/s. radio interface, and vice versa The PCD5043 has interfaces to: • Up to 4 ADPCM CODECs in a simple base station (with up to 4 analogue lines) without glue logic • Dual channel speech/data capability • RSSI measurement, with on-chip 6-bits peak/hold detector • n x 64 kbits/s highway, where n = 1 to 32, for systems requiring more than 4 connections to the network • Local call switching for up to 6 internal calls on RF side/local call switching on speech side • A radio transceiver; the interface is fully decoded, and includes power-down signals • Quality control report • An external microcontroller. • Digital Phase Locked Loop (DPLL) The PCD5043 is designed to be connected to an ADPCM CODEC (Philips’ PCD5032, for example) and an 80C51-type microcontroller. Other microcontrollers (e.g. 68000) and CODECs can also be supported. • Synchronization (handset to active bearer, base station to cluster of RFPs) • Seamless handover procedure • Fast (hardware) and slow (software) mute function • 1 kbyte extended RAM memory • On-chip crystal oscillator (13.824 MHz) • Programmable microcontroller clock frequency • Programmable interrupts • Watchdog with two programmable time-outs • Low power consumption in standby mode • Low supply voltage (2.7 to 5.5 V) • SACMOS technology. 3 ORDERING INFORMATION TYPE NUMBER PCD5043H 1996 Oct 31 PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 3 VERSION SOT319-2 Philips Semiconductors Objective specification DECT burst mode controller 4 PCD5043 BLOCK DIAGRAM handbook, full pagewidth PCD5043 TIMING, CONTROL, CLOCK GENERATION DECT BURST MODE CONTROLLER to CODEC/ Highway 3-wire synthesizer interface SPEECH INTERFACE internal bus RF INTERFACE PROGRAMMABLE COMMUNICATION CONTROLLER (PCC) MICROCONTROLLER INTERFACE PCC PROGRAM MEMORY 4 kbyte ROM Rx/Tx data 8051/68000 interface DATA MEMORY 2 kbyte RAM MBH742 Fig.1 Block diagram. 5 PINNING (see Fig.2) SYMBOL AD0 to AD7 ALE CS PIN TYPE(1) 1 to 8 I/O 9 I address latch enable DESCRIPTION address/Data bus 10 I chip select (active LOW) 13 to 11 I address bus VDD1 14 P positive supply 1 PROC_CLK 15 O microcontroller clock; programmable from fCLK/64 to fCLK, where fCLK is the crystal oscillator frequency VSS1 16 P negative supply 1 XTAL1 17 I crystal oscillator input XTAL2 18 O crystal oscillator output VSS2 19 P negative supply RESET_OUT 20 O watchdog timer output; intended to reset the external microcontroller when expired RD 21 I read (active LOW) WR 22 I write (active LOW) RDY 23 O ready signal (active LOW), to initiate wait states in the microcontroller (open drain) INT 24 O interrupt (active LOW) CLK100 25 O 100 Hz frame timer A8 to A10 1996 Oct 31 4 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 PIN TYPE(1) VSS3 26 P negative supply 3 DO 27 O 3-state data output on the speech interface FS1 28 I/O 8 kHz framing signal to ADPCM CODEC 1 output, for simple base + handset, otherwise 8 kHz framing input FS2 29 O 8 kHz framing signal to ADPCM CODEC 2 in the base station mode DI 30 I data input on the speech interface DCK 31 O simple base + handset; 1152 kHz data clock (output), otherwise 2048 kHz data clock (input) signal CLK3 32 O 3.456 MHz clock (nominal value, used to adjust system timing) ANT_SW 33 O selects one of two antennas T_ENABLE 34 O Transmitter Enable (active LOW) T_POWER_RMP 35 O Transmitter Power Ramp control RMT_STAT 36 I serial 8-bit data can be read in for each slot; REMote radio SYMBOL DESCRIPTION SYNTH_LOCK 37 I lock indication from synthesizer VSS4 38 P negative supply 4 REF_CLK 39 O reference frequency for the synthesizer, i.e. the crystal oscillator clock fCLK VDD2 40 P positive supply 2 S_ENABLE 41 O synthesizer enable S_CLK 42 O clock signal, to be used with S_DATA S_DATA 43 O serial data to the synthesizer S_POWER_DWN 44 O synthesizer power-down control VCO_BND_SW 45 O VCO bandswitch control signal 1200 HZ 46 O control signal for dual synthesizer schemes T_DATA 47 O serial output data to transmitter SET_OFF_IN 48 I switches off the crystal oscillator, and prevents all RF signals from becoming active TEST1 49 I selects various test modes.; normal operation set to 0 RSSI_AN 50 I analog signal (for basic DECT systems), peak signal strength measured after a lowpass filter TEST2 51 I selects various test modes; normal operation set to 0 TEST3 52 I selects various test modes; normal operation set to 0 R_DATA 53 I receive data R_ENABLE 54 O receiver enable (active LOW) R_POWER_DWN 55 O receiver power-down SLICE_CTR 56 O slice time constant control VDD3 57 P positive supply 3 VSS5 58 P negative supply 5 VREF 59 I reference input for the A/D converter VDD(RAM) 60 P power supply for data RAM SYNCPORT 61 I/O 1996 Oct 31 in the base station the signal is the SYNCPORT 5 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 PIN TYPE(1) RESET 62 I BMC master reset signal MEM_SEL 63 I selects PCC program memory at microcontroller interface EN_WATCHDOG 64 I enable watchdog input; when HIGH, the watchdog timer of the BMC is enabled SYMBOL DESCRIPTION Note 1. All signals which are input or I/O, and which can be floating, need to be pulled up to VDD or down to VSS in order to protect the device against cross-currents. Exceptions are VREF and RSSI_AN, which do not have to be protected. 1996 Oct 31 6 Philips Semiconductors Objective specification 52 TEST3 53 R_DATA 54 R_ENABLE 55 R_POWER_DWN 56 SLICE_CTR 57 VDD3 58 VSS5 59 VREF 60 VDD(RAM) PCD5043 61 SYNCPORT 62 MEM_RESET handbook, full pagewidth 63 MEM_SEL 64 EN_WATCHDOG DECT burst mode controller AD0 1 51 TEST2 AD1 2 50 RSSI_AN AD2 3 49 TEST1 AD3 4 48 SET_OFF_IN AD4 5 47 T_DATA AD5 6 46 1200_Hz AD6 7 45 VCO_BND_SW AD7 8 44 S_POWER_DWN ALE 9 43 S_DATA PCD5043H CSN 10 42 S_CLK AD10 11 41 S_ENABLE AD9 12 40 VDD2 AD8 13 39 REF_CLK 38 VSS4 VDD1 14 PROC_CLK 15 37 SYNTH_LOCK VSS1 16 36 RMT_STAT XTAL1 17 35 T_POWER_RMP XTAL2 18 34 T_ENABLE VSS2 19 Fig.2 Pin configuration, PCD5043H. 1996 Oct 31 7 CLK3 32 DCK 31 DI 30 FS2 29 FS1 28 DO 27 VSS3 26 CLK100 25 INT 24 RDY 23 WR 22 RD 21 RESET_OUT 20 33 ANT_SW MBH744 Philips Semiconductors Objective specification DECT burst mode controller 6 PCD5043 Nominally, the frequency on pin CLK3 is 3.456 MHz. This frequency is obtained by dividing the crystal frequency by 4. Sometimes, the crystal frequency will be divided by 3 or by 5, to synchronize the combination of the ADPCM codec and the device to an external source. External synchronization for base station applications is achieved as follows: FUNCTIONAL DESCRIPTION (see Fig.1) The PCD5043 has dedicated hardware blocks containing logic for time-critical functions requiring bit or byte-time accuracy. Other functions requiring only slot-time accuracy are performed by software in the Preprogrammed Communication Controller (PCC). This approach offers maximum flexibility during prototyping. 6.1 6.1.1 • Master base station. The master base station provides a 100 Hz signal to slave base stations on pin SYNCPORT. If the PCD5043 is connected to a digital interface (32-slot mode speech interface), the external synchronization will be done on the incoming 8 kHz signal. If it is connected to an analog line (12-slot mode speech interface), it will use its own crystal oscillator as reference. Internal bus and data memory INTERNAL BUS The function of the internal bus is: • To provide access for all functional blocks to the common data memory • To provide access for the microcontroller-interface and the PCC to all other functional blocks. • Slave base station. The slave base station will use the incoming SYNCPORT signal as synchronization reference. All functional blocks (speech-interface, RF-interface, microcontroller-interface and PCC) can autonomously use the internal bus to communicate with the common data memory. 6.3 A bus controller is used to handle the bus priority mechanism. When several blocks request access simultaneously, the request with the highest priority is handled first. 6.1.2 6.3.1 DATA MEMORY 6.3.2 PCC FUNCTIONS The most important functions of the PCC are to: • Perform the appropriate actions on received messages: PMID and FMID checking, RFPI checking, TBC handling Clock generation and correction (see Fig.3) The device has an on-chip 13.824 MHz crystal oscillator. From this source, a few frequencies are derived for internal and external use. Frequencies generated for external use are: • Prepare A-field messages for transmission • Prepare the RF-interface for the coming slot • Perform the procedures for RSSI and set-up scan, maintain scan counters and timers, assemble the RSSI field in the common data memory • 13.824 MHz for the synthesizer reference (pin REF_CLK). This output is only provided if the synthesizer power-down control (output on pin S_POWER_DWN) is not selected. • Filter events and indicate them to the microcontroller by interrupt. • 0.144 to 13.824 MHz for the microcontroller clock (pin PROC_CLK) • 3.456 MHz for the ADPCM codec (pin CLK3) • 1200 Hz (pin 1200_HZ) for dual synthesizer switching • 100 Hz (pin CLK100) indicates start of frame. 1996 Oct 31 PCC The PCC is a RISC-type controller and is used to control functions which are slot-time accurate. It is well suited for bit manipulation, and runs at a clock frequency of 6.912 MHz (equivalent to 3.4 Mips). After finishing a task, it switches to a power saving state, from which it returns after a pre-programmed time. A large part of the data memory is used for the bit rate adaptation between the DECT radio interface and the speech interface. The data memory also acts as the main communication interface between the external microprocessor and the PCC. 6.2 Programmable communication controller and program memory 8 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 13.824 MHz system clock handbook, full pagewidth 2 6.912 MHz system clock 4 (±1) clock corrections in this level unless disabled PCD5041's mode register 3.456 MHz system clock for ADPCM codec 3 1152 kHz system/bit clock bit counter 480 slot counter 24 144 FSx signals (8 kHz) slot counter 100 Hz frame sync COMPARATOR 16 MBH708 'SYNC' event Fig.3 Internal clocking scheme of the PCD5043. 6.4 signals can be used (FS1 to FS4). When more codecs are to be connected, the FS5 to FS12 signals have to be generated externally. When using the framing signals FS1 to FS4, no interface logic is required when using the PCD5032 ADPCM codec. Speech interface The speech interface block performs the following functions: • Connection to a 1152 kbits/s interface in a handset and a simple base station in the so called ‘12 slot mode’ A speech-slot control table is used to determine where to store/fetch speech data for transmission and reception. The hardware speech-interface is capable of addressing the right speech buffer for the relevant speech slot, and will maintain a counter carrying the offset to the correct stored/fetched address. • Connection to a n x 64 kbits/s interface in base stations in the so called ‘32 slot mode’ • Autonomous storing/fetching of ADPCM speech data in/from the PCD5043’s common data memory, using internal addressing logic • Muting of speech data 6.4.2 • Local call. 6.4.1 The 32-slot mode is used to connect the PCD5043 to a digital interface with a data rate of n × 64 kbits/s; where n = 1 to 32 is the number of speech slots. This equates to data rates from 64 kbits/s to 2048 kbits/s. Up to 12 of the 32 speech slots can be used simultaneously. The same kind of speech-slot control table used in the 12-slot mode is used for the 32-slot mode. 12-SLOT MODE The 12-slot mode is selected if up to 4 ADPCM codecs are connected to the PCD5043, where the PCD5043 is the master of these codecs. In a handset, or in a simple base stations which is connected with up to 4 analog lines to the public network, the PCD5043 is master of the codecs. Each codec is connected with a separate framing reference signal (FS1 to FS4) to the PCD5043. In the QFP64 package, 2 framing signals FS1 and FS2 are available, whereas in the LQFP80 package 4 framing 1996 Oct 31 32-SLOT MODE 6.4.3 MUTING Due to various reasons the quality of the incoming speech data may be degraded significantly. By muting the speech 9 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 data, these disturbances are not audible (or are less audible) to the user. The PCD5043 performs two types of muting: 6.5.1 The serial receiver processes the data, which comes from the RF section, and which is already filtered by the synchronization part. The data is latched, using the recovered data clock. • Fast muting • Slow muting. The serial receiver will collect the complete A-field and B-field and store it in the common data memory. Before the A-field is received, the A-field start address is programmed by the PCC. Upon reception of A-field nibbles, the address is updated by the serial receiver. Meanwhile, the PCC will program the B-field start address. Fast muting, which is performed by the PCD5043 automatically, is nothing more than a repetition of the previously received frame (80 speech samples) to the ADPCM codec. It is issued if no Sync word was detected. Slow muting is issued by the microcontroller, after having detected a degradation of quality. A slow mute is implemented as a continuous ‘0000’ nibble transmission to the ADPCM codec, until slow mute is released. 6.4.4 In Fig.5 the data flow in the serial receiver is shown. Note that almost no decoding of messages is required. Only the header of the A-field needs to be decoded to check if a ciphered message is being received or transmitted, which requires the ciphering to be switched on in the A-field also. LOCAL CALL A local call option is implemented, in order to loopback data from one codec to another codec, and vice versa, see Fig.4. 6.5.2 0 1 0 1 0 1 DO 1 SERIAL TRANSMITTER The serial transmitter performs the reverse of the receiver functions. Several blocks used in the receiver are also used in the transmitter. Amongst these are the CRC-generators, the scrambler, and the address registers. Figure 6 shows the serial transmitter structure. handbook, halfpage 0 SERIAL RECEIVER By transmitting the X-CRC twice, the Z-field is transmitted. The handling of the address registers is the same for the transmitter. Transmission of the synchronization sequence (S-field) is done using the same method as the A-field and B-field. The S-field is stored in the common data memory and will be fetched by the transmitter, just before transmission. DI speech slots speech buffer pair Two additional functions are not shown in Fig.6: MBH710 • In the handset the data in the serial transmitter may be advanced by a programmable number of bit periods. This is done to compensate for the delay in the RF section Fig.4 Local call switching on speech interface. 6.5 • The transmitted data can be inverted (using a switch in the PCD5043 mode register), in order to connect the PCD5043 to VCOs requiring negative modulation. RF interface Most of the functions performed by the RF interface are under control of the PCC. Specifically, the processing of non-speech data and the programming of functions and registers is done via the PCC. 1996 Oct 31 10 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 handbook, full pagewidth DATA MEMORY DATA MEMORY READ CONTROL nibble-parallel bit-serial DE-CIPHER CIPHER CONTROL other ok DE-CIPHER R-CRC cs MUX MUX Cs-DEC. Bprotect UNSCRAMBLE ok ok R-CRC X-CRC A-MAP B-MAP D-MAP MBH737 D00 D32 Fig.5 Serial receiver structure. handbook, full pagewidth DATA MEMORY DATA MEMORY READ CONTROL nibble-parallel bit-serial CIPHER CIPHER CIPHER CONTROL other R-CRC cs MUX MUX Cs-DEC. Bprotect UNSCRAMBLE R-CRC X-CRC A-MAP B-MAP D-MAP MBH736 D00 D32 Fig.6 Serial transmitter structure. 1996 Oct 31 11 Philips Semiconductors Objective specification DECT burst mode controller 6.5.3 PCD5043 To program various types of synthesizers, a 3-byte shift register is present. Three data formats are supported: 8, 16 or 24 bit words can be selected. The transfer of data from a frequency table in the common data memory to the shift register is under control of the PCC. SEAMLESS HANDOVER Seamless handover guarantees that when speech information is switched from one slot to another, no speech samples are lost, added or displaced. Seamless handover is achieved in the RF interface by: • Using a look-up table containing the correct start addresses of the B-fields in the data memory 6.5.6 The RSSI measurement in the PCD5043 RF-interface block is done in 3 parts: a peak/hold detector, a 6-bit A/D converter, and an RSSI control unit, which controls the peak/hold detector and the A/D converter. Once per slot time, a sample is fetched by the PCC and saved in the appropriate area of the common data memory. • The RF receive and transmit blocks move data to/from the data memory block in 4-bit nibbles. 6.5.4 RF CONTROL SIGNALS The timing of the control signals to the RF section is fixed, but such that an RF delay between 1.5 and 7 µs can be tolerated. Only the transmitter ramp signal and the synthesizer enable are programmable within certain limits. 6.5.5 RSSI MEASUREMENT If the radio receiver is active in a particular time slot, the RSSI value will automatically be measured in that slot. Adjustment to the RSSI_AN input level can be made with VREF. SYNTHESIZER PROGRAMMING To program a synthesizer, a 3-wire serial interface is used. The signals on this interface are: • S_ENABLE (enable) • S_CLK (clock) • S_DATA (data). RF-INTERFACE handbook, full pagewidth VREF RSSI_AN RSSI value filtered width = 30 µs (τ =10 to 40 µs) PEAK HOLD RSSI_AN 6 6-BIT A/D RSSI CTRL (HW) RSSI PROCESSING (SW in PCC) start_AD write in memory RSSI_CTR MBH711 Fig.7 RSSI measurement path. 1996 Oct 31 internal bus 12 Philips Semiconductors Objective specification DECT burst mode controller 6.5.7 PCD5043 Bit synchronization is done using a Digital PLL (DPLL), with an oversampling factor of 12, i.e. the DPLL is running at 12 times the data rate. The output from the DPLL is a receive clock signal (RxC), which acts as the enable for a 20-bit shift register. LOCAL CALL SWITCHING (see Fig.8) The PCD5043 provides a local call switching function in the base station. It will store incoming speech nibbles in the common data memory, in the area reserved for that particular receive slot. Then, during the transmit phase, it passes the start pointer of the same data memory area to the transmit block. Thus, the speech data is echoed to the other user. To handle quality degradation for local calls, a mute can be performed at the RF side of the speech buffer. 6.5.8 Sync word detection is achieved by checking the incoming data pattern with the expected synchronization field pattern, using a correlator. The correlator has a programmable threshold, so it can accept bit errors in the sync field pattern up to the threshold level. Furthermore, the correlator window is programmable. This means that ‘SlotSync’, which indicates the slot synchronization event, can be detected only during a certain period (the time window). DATA SYNCHRONIZATION (see Fig.9) The data synchronization is done in 2 phases: • Bit synchronization • Sync word detection. handbook, full pagewidth RF slots Rx1 Rx2 Tx1 Tx2 MBH712 speech buffers in data memory Fig.8 Local call switching on the RF-side. 13.824 MHz handbook, full pagewidth R_DATA (1152 kbits/s) filtered data in FILTER R×C DPLL EN D XOR 20-BIT SHIFT REGISTER Q0 to Q15 Q16 to Q19 base/handset to serial receiver logic threshold correlator window MBH713 CORRELATOR (E98A) SYNC CHECK (1010) SlotSync DPLL_sync Fig.9 Schematic of the receiver synchronization part. 1996 Oct 31 13 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 The ‘DPLL_sync’ indication should only be used, when ‘SlotSync’ is active. It indicates that the last 4 bits of the pre-amble field (the training sequence) are received correctly, and thus indicates that the DPLL was in lock (synchronized) in time. If the ‘SlotSync’ is active, and the ‘DPLL_sync’ is not, then a sliding interferer might have been detected. responsibility of the PCC, and the external microprocessor. 6.6 6.6.1 FUNCTION OF THE MICROCONTROLLER INTERFACE The microcontroller Interface will provide the following services. If ‘SlotSync’ is not detected, effectively no data is received in that slot. This implies a ‘fast mute’ because speech data received in the previous frame is not destroyed. 6.5.9 Microcontroller Interface • Direct interface to processors which have an INTEL-8051 compatible interface • General interface to processors that can handle ‘wait states’ e.g. 68000-family; in this case glue logic is required CIPHERING MACHINE The description of the cipher machine is subject to confidentiality. The specification of its algorithms are delivered by ETSI under the terms of a Non-Disclosure Agreement. • Processor clock signal of which the frequency is programmable in order to adjust instantaneously processor performance to processor work load • A programmable interrupt register The cipher machine is under control of the TBC, which is implemented in the PCC. The cipher machine generates 2 fields of ciphering bits: • A watchdog timer with time-out periods of 1.25 or 82 seconds, depending on the programming. • A_cipher (40 bits) for A-field messages (ciphers tail only) The microcontroller can address the PCD5043 as any other RAM memory connected to the microcontroller bus. By writing the ‘Interface-Mode Register’, the microcontroller can select the interface mode and its own clock frequency. • B_cipher (320 bits) for speech in B-field. The transmitted ciphered bits are then: • A_ciphered: = A XOR A_cipher • B_ciphered: = B XOR B_cipher. 6.6.2 On reception by the peer end point, deciphering consists of the same operation thanks to the synchronous generation of A_cipher and B_cipher. The function of microcontroller Interrupts is to make optimal use of the microcontroller’s processing power, and to achieve optimal cooperation between time-critical tasks and less time-critical tasks both executed in software. Three registers are available to handle interrupts. These are: handbook, halfpage KEY 64 BITS • Interrupt Event Register A_cipher (40 bits) • Interrupt Enable Register CIPHER MACHINE KEY 64 BITS • Interrupt Reset Register. B_cipher (320 bits) These registers are to be regarded together. Corresponding bits in these registers relate to one and the same event. Bits in the Interrupt Event Register are set by the PCC and are to be reset by the external processor by writing ‘1’s in the corresponding bits in the Interrupt Reset Register. The mask in the Interrupt Enable Register enables the interrupt if corresponding events do occur. MBH714 Fig.10 Cipher machine and its sources. The cipher machine is time-multiplexed on a slot basis. Initially, the Initialisation Vector (IV) and the key must be loaded into the cipher machine. Transfer of the IV and key from the common data area to the cipher machine is done automatically by the cipher machine. The contents of the memory space where IV and key are found, are the 1996 Oct 31 MICROCONTROLLER INTERRUPTS 14 Philips Semiconductors Objective specification DECT burst mode controller 6.6.3 PCD5043 Table 1 Hardware register addresses WATCHDOG The PCD5043 is equipped with a watchdog timer, which generates a reset towards an external device (e.g. a µC) after time-out. Two (fixed) time-out periods can be programmed; 1.25 s and 82 s. The watchdog function can be disabled by using the EN_WATCHDOG input pin. ADDRESS WRITE READ 7E0 − − 7E1 S-DATA1 − 7E2 S-DATA2 − 7E3 S-DATA3 RMT-STAT 7E4 − RF-STATUS The PCC may switch off the 6.912 MHz internal clock, to enter a power saving mode. All blocks, running on this clock are then switched off (i.e. RF-interface, cipher block, speech interface, PCC). This is called the power-down state, and is only used in the handset mode. 7E5 B-field-shift − 7E6 B-field-loc. − 7E7 A-field-loc. − 7E8 window-wide-off − The 13.824 MHz clock is never switched off. The Timing Control, microcontroller interface, and Bus Controller keep running, in order to remain synchronous with a base station, and to keep the wake-up circuitry active. During power-down the external microcontroller has still access to the common data area. 7E9 window-wide-on − 7EA window-narrow-off − 7EB window-narrow-on − 7EC T-power-rmp-on − 7ED synth-off − 7EE RF-control-port sync-status 7EF slot-cnt-off slot-counter-copy 7F0 frame-cnt-ref RSSI 7F1 sync-ref-preset bit-counter-copy1 7F2 bit-counter-preset bit-counter-copy2 7F3 frame-counter frame-counter 7F4 slot-counter slot-counter 7F5 sync-control sync-control 7F6 BMC-mode BMC-mode 7F7 correlator-threshold measure 7F8 watchdog-1 − 7F9 watchdog-2 − 7FA − − 7FB − − 7FC interrupt-event interrupt-event 7FD interrupt-enable interrupt-enable 7FE interrupt-reset − 7FF controller mode controller mode 6.6.4 6.7 POWER-DOWN Survey of registers For a survey of all addresses occupied refer to Tables 1 and 2. Some of the address locations are used differently for read and write. The addresses 000 to 7DF are occupied by RAM memory, while the upper 32 bytes are assigned to the hardware registers. A part of the RAM memory is allocated for use by the RF block, cipher block, and the speech interface. 1996 Oct 31 15 Philips Semiconductors Objective specification DECT burst mode controller Table 2 PCD5043 Fixed RAM locations ADDRESS ENTRY 740 to 747 cipher key vector #0 748 to 74F cipher key vector #1 750 to 757 cipher key vector #2 758 to 75F cipher key vector #3 760 to 767 cipher key vector #4 768 to 76F cipher key vector #5 770 to 777 cipher key vector #6 778 to 77F cipher key vector #7 780 to 787 cipher key vector #8 788 to 78F cipher key vector #9 790 to 797 cipher key vector #10 798 to 79F cipher key vector #11 7A0 to 7A7 cipher init vector 7A8 to 7AA not used 7AB XZ field buffer 7AC to 7AF S-field buffer 7B0 to 7BB cipher-slot-control-table 7BC to 7BF not used 7C0 to 7DF speech-slot-control-table 7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 Vi all input voltages −0.5 VDD + 0.5 V II DC input current −10 +10 mA IO DC output current −10 +10 mA Ptot total power dissipation − +500 mW PO power dissipation per output − 30 mW V IDD supply current −100 +130 mA ISS ground current −100 +130 mA Tstg storage temperature range −55 +100 °C Tj operating junction temperature − 90 °C 1996 Oct 31 16 Philips Semiconductors Objective specification DECT burst mode controller 8 PCD5043 CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Tamb operating ambient temperature −25 − +70 °C VDD supply voltage 2.7 − 5.5 V VDD(ret) RAM retention voltage 1.0 − VDD V IDD operating supply current note 1 − 6 12 mA IDD(stb) standby supply current note 2 − 1 3 mA clock input duty cycle All inputs LOW except WRN; XTAL1 running at 14 MHz 45 − 55 % Digital I/O VIL LOW level input voltage 0 − 0.3VDD V VOL LOW level output voltage 0 − 0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD V VOH HIGH level output voltage 0.7VDD − ILI input leakage current IO(source) output source current VDD = 3.6 V; 0.4 V ≤VO ≤ VDD − 0.4 V 2.0 IO(sink) output sink current VDD = 3.6 V; 0.4 V ≤VO ≤ VDD − 0.4 V IRDYN(sink) RDYN output sink current fDCK DCK input frequency fFS1 FS1 input frequency VDD V 1.0 µA 5.0 − mA 2.0 5.0 − mA VDD = 3.6 V; VO = 0.4 V 2.0 5.0 − mA VDD = 5.0 V; VO = 0.4 V − 6.0 − mA − n × 64 − kHz − 8 − kHz VDD = 2.7 V 0.6 − − mS VDD = 3.6 V − 1.6 − mS 200 500 n = 1 to 32 Oscillator (inputs XTAL1 and XTAL2) gm RF transconductance feedback resistance kΩ RSSI Peak detector (6-bit linear A-D converter, for RSSI measurement on input RSSI_AN) input level 0 − VDD V Vconv(RSSI_AN) voltage conversion range 0 − VREF V Vi(RSSI_AN) Vi(VREF) VREF input voltage Zi(VREF) VREF input impedance tconv conversion time during power-down high impedance integral non-linearity differential non-linearity Zi(RSSI_AN) note 3 input impedance RSSI_AN 1.0 3.0 VDD V − 50 − kΩ 18.4 − − µs − − 4 LSB − 0.2 1.5 LSB − 1 − MΩ Notes to the characteristics 1. VDD = 3.0 V; fclk =13.824 MHz; no external load; one speech link active (under typical conditions). 2. VDD = 3.0 V; fclk =13.824 MHz; no external load; after reset. 3. Maximum differential non-linearity at supply voltage 5.5 V and VREF = 1 V. 1996 Oct 31 17 Philips Semiconductors Objective specification DECT burst mode controller 9 PCD5043 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height SOT319-1 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 θ wM Lp pin 1 index bp L 20 64 detail X 19 1 w M bp e ZD v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.3 0.36 0.10 2.87 2.57 0.25 0.50 0.35 0.25 0.13 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.43 1.23 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-1 1996 Oct 31 EUROPEAN PROJECTION 18 o 7 0o Philips Semiconductors Objective specification DECT burst mode controller PCD5043 10 SOLDERING 10.3 10.1 Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. If wave soldering cannot be avoided, the following conditions must be observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 10.2 • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Reflow soldering Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. 10.4 Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1996 Oct 31 Wave soldering 19 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 11 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 12 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Oct 31 20 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 NOTES 1996 Oct 31 21 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 NOTES 1996 Oct 31 22 Philips Semiconductors Objective specification DECT burst mode controller PCD5043 NOTES 1996 Oct 31 23 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 647021/00/01/pp24 Date of release: 1996 Oct 31 Document order number: 9397 750 01293