PHILIPS SAA4952WP

INTEGRATED CIRCUITS
DATA SHEET
SAA4952WP
Memory controller
Objective specification
File under Integrated Circuits, IC02
1997 Jun 10
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
• Capability of reading the length of incoming fields via
microcontroller port
FEATURES
• Support for acquisition, display and deflection PLL
• Golden SCART option (clock generation for TDA9151)
• 50/100 Hz (or 60/120 Hz) scan conversion
• Acquisition is able to operate with external sync and
clock of digital sources (slave mode)
• Progressive scan 50 Hz/1250 lines (60 Hz/1050 lines)
interlaced or 50 Hz/625 lines (60 Hz/525 lines)
non-interlaced in serial memory structure
• Generator mode for the display, stable still picture or
OSD in the event of no input source.
• 50 Hz/625 lines (60 Hz/525 lines) mode support for a
PALplus system and basic features
GENERAL DESCRIPTION
• Acquisition frequencies 12, 13.5, 16 and 18 MHz and
display frequencies of 27, 32 and 36 MHz (2fH) in every
combination, horizontal compression (support for 4 : 3
and 14 : 9 display on a 16 : 9 screen) and horizontal
zoom
The memory controller SAA4952WP is the improved
version of the SAA4951WP. The circuit has been designed
for high-end TV sets using 2fH technics. For basic feature
modules a 1fH mode can be activated. In this situation the
controller supplies the system with a line-locked clock.
The new device has been designed to be able to operate
in the hardware environment of the SAA4951WP.
• Configured as a three clock system with a fixed 27 MHz
deflection clock (deflection controlled by the TDA9151)
• Configured as a two-clock system (deflection controlled
by e.g. TDA9152)
The circuit provides all necessary write, read and clock
pulses to control different field memory concepts.
Furthermore the drive signals for the horizontal and
vertical deflection power stages are also generated.
• Single clock for 50 Hz vertical and 15.625 kHz
horizontal frequency
• Support of new IC generations [PAN-IC (SAA4995WP),
VERIC (SAA4997H), MACPACIC (SAA4996H) and
LIMERIC (SAA4945H)]
The device is connected to a microcontroller via an 8-bit
data bus. The microcontroller receives commands via the
I2C-bus. Due to this fact the START and STOP conditions
of the main output control signals are programmable and
the SAA4952WP can be set in different function modes
depending on the TV feature concept that is used.
• Support for two or one field memories
• Still picture
• Support for memory types such as TMS4C2970/71
• Internal simple Multi-PIP (3 × 3) or (4 × 4) conversion
• Multi-PIP support with an external PIP module/full
performance
• Programmable via microcontroller port
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
4.5
5
5.5
V
IDD
supply current
−
35
−
mA
fLLDFL,LLD
operating frequency of display and deflection part
−
−
33
MHz
facq
acquisition frequency
−
−
37
MHz
Tamb
operating ambient temperature
0
−
85
°C
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA4952WP
1997 Jun 10
PLCC44
DESCRIPTION
plastic leaded chip carrier; 44 leads
2
VERSION
SOT187-2
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
BLOCK DIAGRAM
ALE
handbook, full pagewidth
21
WRD
P0 P1 P2 P3 P4 P5 P6 P7
22
25 26 27 28 29 30 31 32
MICROCONTROLLER
INTERFACE
STROBE
SAA4952WP
IE
PROCESSING
9
7
14
3
÷2
LLA
(12, 13.5, 16, 18 MHz)
13
ACQUISITION
HORIZONTAL
TIMING
6
11
TEST
SDP
SSC
SWC1
SWC05
HRA/BLNA
CLV
VACQS
5
41
LOGIC
ACQUISITION
VERTICAL
TIMING
39
VACQ
(50/60 Hz)
LLDFL
(27, 32, 36 MHz)
IE2
HWE1
16
40
IE1
33
8
WE1
VWE1
42
DEFLECTION
TIMING
35
37
38
RSTW1
HRDFL
HDFL
VDFL
VWE2
DISPLAY
VERTICAL
TIMING
15
VRE1
WE2
VRE2
17
VD
HVCD
LOGIC
18
RE1
HWE2
HRE
LLD
DISPLAY
HORIZONTAL
TIMING
43
19
20
1
(32, 36 MHz)
LOGIC
4
2, 10, 23, 36
VDD1 to VDD4
Fig.1 Block diagram.
1997 Jun 10
3
RE2
HD
BLND
HRD
SRC
12, 24, 34, 44
VSS1 to VSS4
MHA724
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
HRD
1
O
VDD1
2
supply
SWC1
3
O
serial write clock output for memory 1
SRC
4
O
serial read clock output
SDP
5
I
select deflection processor input
SWC05
6
O
serial write clock output, SWC1 divided-by-2
IE1
7
O
input enable signal output (memory 1)
WE1
8
O
write enable signal output (memory 1)
STROBE
9
I
strobe signal input
VDD2
10
supply
HRA/BLNA
11
I/O
VSS1
12
−
ground 1
LLA
13
I
line-locked clock signal input (acquisition part)
IE2
14
O
input enable signal output (memory 2)
WE2
15
O
write enable signal output (memory 2)
CLV
16
O
horizontal signal output (acquisition part)
HVCD
17
O
horizontal, vertical or composite blanking signal output (display part)
RE1
18
O
read enable signal output (memory 1)
RE2
19
O
read enable signal output (memory 2)
BLND
20
O
horizontal blanking signal output (display part)
ALE
21
I
address latch enable signal input
WRD
22
I
write/read data signal input
VDD3
23
supply
VSS2
24
−
P0
25
I/O
data input/output signal bit 0
P1
26
I/O
data input/output signal bit 1
P2
27
I/O
data input/output signal bit 2
P3
28
I/O
data input/output signal bit 3
P4
29
I/O
data input/output signal bit 4
P5
30
I/O
data input/output signal bit 5
P6
31
I/O
data input/output signal bit 6
P7
32
I/O
data input/output signal bit 7 (MSB = Most Significant Bit)
LLDFL
33
I
line-locked clock signal input (deflection part)
VSS3
34
−
ground 3
HRDFL
35
O
horizontal reference signal output (deflection part)
VDD4
36
supply
HDFL
37
O
horizontal synchronization signal output (deflection part)
VDFL
38
O
vertical synchronization signal output (deflection part)
VACQ
39
I
vertical synchronization signal input (acquisition part)
1997 Jun 10
horizontal reference signal output (display PLL)
supply voltage 1
supply voltage 2
horizontal reference signal output (acquisition part)/horizontal blanking
signal input, reset for horizontal acquisition counters (acquisition part)
supply voltage 3
ground 2
supply voltage 4
4
Philips Semiconductors
Objective specification
Memory controller
SYMBOL
TEST
SAA4952WP
PIN
I/O
40
I
DESCRIPTION
test input
44
−
ground 4
1 HRD
3
handbook, full pagewidth
40 TEST
VSS4
41 SSC
line-locked clock signal input (display part)
42 RSTW1
I
43 LLD
43
44 VSS4
LLD
2 VDD1
reset write signal output (memory 1)
SWC1
select single clock system input
O
4 SRC
I
42
5 SDP
41
RSTW1
6 SWC05
SSC
IE1 7
39 VACQ
WE1 8
38 VDFL
STROBE 9
37 HDFL
VDD2 10
36 VDD4
HRA/BLNA 11
35 HRDFL
VSS1 12
34 VSS3
SAA4952WP
Fig.2 Pin configuration.
1997 Jun 10
5
P3 28
P2 27
P1 26
P0 25
29 P4
VSS2 24
30 P5
VDD3 23
CLV 16
HVCD 17
WRD 22
31 P6
ALE 21
WE2 15
BLND 20
32 P7
RE2 19
33 LLDFL
IE2 14
RE1 18
LLA 13
MHA723
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
enable signal with a horizontal and vertical part (WE1).
The START and STOP position of the pulses are
programmable, whereas the increment equals 2 (4) clock
cycles in the horizontal part and 1 line in the vertical part.
For HWE1 an additional 2-bit fine delay is available.
FUNCTIONAL DESCRIPTION
The SAA4952WP is a memory controller intended to be
used for scan conversion in TV receivers. This conversion
is performed from 50 to 100 Hz or from 60 to 120 Hz.
Besides the doubling of the field frequency a progressive
scan conversion can be activated (50 Hz/1250 lines or
60 Hz/1050 lines). For low cost PALplus receivers a
simple 50 Hz/1fH mode can be performed. The device
supports up to three separate PLL circuits. The acquisition
PLL can operate with frequencies of 12, 13.5, 16 or
18 MHz. In a three-clock system the deflection PLL
operates with 27 MHz (see Fig.11). An additional display
PLL generates 32 or 36 MHz. If a two-clock system is
chosen the deflection PLL can operate with all possible
display frequencies (27, 32 and 36 MHz) and the extra
PLL can be omitted (see Fig.12). In a system using the
deflection processor TDA9151, three PLLs are necessary
because the 27 MHz clock is needed for the deflection.
If other deflection processors are used (e.g. TDA9152) two
PLLs are sufficient. The 50 Hz/1fH mode operates with a
single clock.
Display related control signals are derived from the display
clock. The functions are similar to the acquisition part.
The clock frequency can be switched to 27, 32 or 36 MHz.
In the event of a three-clock system using the TDA9151
the 27 MHz clock frequency is generated by an additional
deflection PLL. In the horizontal part the pulses HWE2,
HR2, HD and BLND are programmable in increments of
2 (4) clock cycles, each one adjustable by an additional
2-bit fine delay. The vertical processing block generates
VDFL and enable signals for the horizontal part (VWE2,
VRE1, VRE2 and VD).
The 16 kHz PLL reference pulse HRDFL is generated from
the display clock frequencies (27, 32 or 36 MHz) and the
32 kHz deflection pulse HDFL. In the three-clock system
the deflection pulses are derived from an extra 27 MHz
clock, independent of the chosen mode of the scan
converter module.
Frequency doubling is possible for input data rates of
12, 13.5, 16 and 18 MHz. Displaying a 4 : 3 picture on a
16 : 9 screen is possible by using the clock configuration
12/32 MHz and 13.5/36 MHz. A 14 : 9 picture can be
displayed on a 16 : 9 screen by the frequency
combinations 16/36 MHz or 12/32 MHz. The VCO and
loop filter are peripheral parts of each PLL, the clock
divider and generation of the reference pulse for the phase
detector are internally provided.
The field length of two successive fields is measured in the
vertical acquisition part. The sampling of VACQ is
performed internally via the signal HVACQS, a pulse
which occurs every 32 µs. The position of this pulse is
programmable via the microcontroller interface to ensure
correct sampling of VACQ.
The measured length of the fields can be read by the
microcontroller. Depending on these values the
microcontroller selects an appropriate setting to achieve
an optimized display performance.
The device generates all write, read and clock pulses to
control a field memory in the desired mode. The required
signals are programmable via an 8-bit parallel
microcontroller port.
The 100 Hz vertical synchronizing signal VDFL is
generated in accordance with the measured length of the
incoming fields. The position towards the video data of this
pulse can also be selected by the microcontroller.
Furthermore two field identification signals for 50 Hz and
for 100 Hz are generated internally to mark the
corresponding display fields for the microcontroller.
Figure 1 shows the block diagram of the SAA4952WP.
The clock signal LLA from the VCO is input at pin 13, a
horizontal reference pulse HRA for the phase discriminator
is output at pin 11. By setting the clock divider to different
values the PLL can be forced to operate with different
clock frequencies. The acquisition part can also be
configured to operate with an external clock frequency
from a digital source. Pin 11 is used as an input pin.
The horizontal reference pulse BLNA is supplied externally
to reset the horizontal counters. This mode is intended to
be used together with, for example, a digital colour
decoder which provides the clock and reference pulses.
The SAA4952WP supports two different Multi
Picture-In-Picture (MPIP) modes. In addition to the
features of the SAA4951WP the new controller is able to
generate a 3 × 3 MPIP without an external PIP module.
The PIP is obtained in a simple way by storing each third
pixel and line of the source into the memory. The display
is able to run free and is not synchronized to the PIP
source in this mode. One of the nine MPIPs can show a
live picture while the others are frozen.
The signals HWE1, CLV and HVACQS are generated in
the horizontal acquisition processing part. The vertical
processing block supplies the signals RSTW1 as well as a
vertical enable signal (VWE1) for the combined write
1997 Jun 10
6
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
By changing the active MPIP in a sequence all PIPs are
sequentially updated.
Microcontroller interface
The SAA4952WP is connected to a microcontroller via
pins P0 to P7, ALE and WRD. This controller receives
commands from the I2C-bus and sets the register of the
SAA4952WP accordingly. Figure 3 shows the timing of
these signals. Address and data are transmitted
sequentially on the bus with the falling edge of ALE
denoting a valid address and the falling edge of WRD
denoting valid data. The individual registers, their address
and their function are listed in Tables 1 to 12. Various
START and STOP registers are 9 bits wide, in this
instance the MSB is combined with MSBs of other signals
or fine delay control bits in an extra control register which
has to be addressed and loaded separately.
The second Multi-PIP option needs an extra PIP module.
This module produces a PIP picture which is originally
displayed at the bottom right position of the screen.
The information of the PIP picture is stored at a desired
position in the field memories. Depending on the
compression mode of the PIP module, the MPIP display
can be configured via software control
(e.g. 4 × 3, 4 × 4, etc.).
For basic features and PALplus systems a 50 Hz/1fH
single clock mode is provided. Switching between a 2fH
and the 1fH mode is performed by the SAA4952WP
hardware pin SHF to avoid wrong HDFL frequencies
which might occur in the event of a software controlled
selection. For the same reason the deflection processor is
selected via pin SDP, whereas in the case of the TDA9152
or another deflection processor without the need of a
constant 27 MHz clock, only two PLLs are necessary.
In order to load the proper values to the vertical control
registers (VWE2, VRE1 and VRE2) in the event of e.g.
median filtering, information about the current 100 Hz field
is necessary. To obtain this data, the microcontroller
sends the address 80H (read mode) which puts the
SAA4952WP in output mode for the next address/data
cycle. For this one cycle the WRD pin works as a RDN pin.
ICs from the new IC generation such as PALplus,
LIMERIC and PAN-IC need to be supplied with two clocks.
The frequency of one clock equals the frequency of the
output data (13.5, 16 or 18 MHz). A second clock operates
with twice the frequency (27, 32 or 36 MHz).
The SAA4952WP generates the necessary signals,
whereas SWC05 is obtained by dividing LLA by a factor of
two.
The microcontroller is able to read the length of the
incoming fields. The length is measured in multiples of
32 µs. The result of the measurement is a 10-bit data
word. The first 8 bits can be accessed under read address
81H. Register 80H contains the MSB and the 9th bit.
The exact knowledge of the field length makes it possible
to decide in which standard the input signal was
transmitted. The microcontroller is able to detect
non-standard sources such as a VCR in trick modes. It is
also possible to decide whether the input is interlaced or
non-interlaced. The vertical control signals to the
memories are adapted to the source to obtain a stable
display.
The display section can be set into a fixed mode via the
microcontroller port. This allows a generator mode
function for displaying OSD without a stable input signal.
A still picture can be shown on the screen completely
decoupled from the input of the converter. The generator
mode can also be used if the MPIP function is activated.
handbook, full
pagewidth
ALE
WRD
DATA
ADDRESS
DATA
ADDRESS
DATA
ADDRESS
MGH133
Fig.3 Microcontroller interface timing.
1997 Jun 10
7
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
Internal registers
Table 1
Vertical display related pulses
ADDRESS
(HEX)
REGISTER
40
VDFLSTA(1)
start of VDFL pulse (only 8-bit)
41
VDFLSTO(1)
stop of VDFL pulse (only 8-bit)
42
VWE2STA(2)
start of vertical write enable 2 (lower 8 of 9 bits)
43
VWE2STO(2)
stop of vertical write enable 2 (lower 8 of 9 bits)
44
VRE2STA(2)
start of vertical read enable 2 (lower 8 of 9 bits)
45
VRE2STO(2)
stop of vertical read enable 2 (lower 8 of 9 bits)
46
VRE1STA(2)
start of vertical read enable 1 (lower 8 of 9 bits)
47
VRE1STO(2)
stop of vertical read enable 1 (lower 8 of 9 bits)
53
VDSTA(2)
start of vertical display signal (lower 8 of 9 bits)
54
VDSTO(2)
stop of vertical display signal (lower 8 of 9 bits)
55
VDMSB(2)
bit 0: MSB of VRE1STA
FUNCTION
bit 1: MSB of VRE1STO
bit 2: MSB of VWE2STA
bit 3: MSB of VWE2STO
bit 4: MSB of VRE2STA
bit 5: MSB of VRE2STO
bit 6: MSB of VDSTA
bit 7: MSB of VDSTO
62
SETFIELD1(1) field length to be set by the microcontroller in the generator mode (lower 8 of 10 bits);
bit 0 = LSB
63
SETFIELD2(1) field length to be set by the microcontroller in the generator mode;
bit 0: bit 8 of field length
bit 1: bit 9 of field length (MSB)
Notes
1. VDFLSTA, VDFLSTO, SETFIELD1 and SETFIELD2 are programmable in increments of half lines (16 µs/32 µs).
2. The memory control signals VWE2, VRE1 and VRE2 as well as VD can be changed in steps of one display line.
1997 Jun 10
8
Philips Semiconductors
Objective specification
Memory controller
Table 2
SAA4952WP
Horizontal display related pulses
ADDRESS
(HEX)
REGISTER
48
BLNDSTA
start of horizontal blanking pulse (lower 8 of 9 bits)
49
BLNDSTO
stop of horizontal blanking pulse (lower 8 of 9 bits)
FUNCTION
4A
HWE2STA
start of horizontal write enable 2 (lower 8 of 9 bits)
4B
HWE2STO
stop of horizontal write enable 2 (lower 8 of 9 bits)
4C
HRESTA
start of horizontal read enable (lower 8 of 9 bits)
4D
HRESTO
stop of horizontal read enable (lower 8 of 9 bits)
56
HDSTA
start of horizontal display signal HD (lower 8 of 9 bits)
57
HDSTO
stop of horizontal display signal HD (lower 8 of 9 bits)
4E
HDMSB
bit 0: MSB of BLNDSTA
bit 1: MSB of BLNDSTO
bit 2: MSB of HWE2STA
bit 3: MSB of HWE2STO
bit 4: MSB of HRESTA
bit 5: MSB of HRESTO
bit 6: MSB of HDSTA
bit 7: MSB of HDSTO
4F
HDDEL
bit 0: fine delay of BLND (LSB)
bit 1: fine delay of BLND (MSB)
bit 2: fine delay of HWE2 (LSB)
bit 3: fine delay of HWE2 (MSB)
bit 4: fine delay of HRE (LSB)
bit 5: fine delay of HRE (MSB)
bit 6: fine delay of HD (LSB)
bit 7: fine delay of HD (MSB)
64
HVSP1
horizontal pulse 1 for frame synchronization, 8-bit resolution
65
HVSP2
horizontal pulse 2 for frame synchronization, 8-bit resolution
66
HVSP3
horizontal pulse 3 for frame synchronization, 8-bit resolution
67
HVSP4
horizontal pulse 4 for frame synchronization, 8-bit resolution
1997 Jun 10
9
Philips Semiconductors
Objective specification
Memory controller
Table 3
SAA4952WP
Vertical acquisition related pulses
ADDRESS
(HEX)
REGISTER
50
VWE1STA(1)
start of vertical write enable (lower 8 of 9 bits)
51
VWE1STO(1)
stop of vertical write enable (lower 8 of 9 bits)
52
VAMSB
FUNCTION
bit 0: MSB of VWE1STA
bit 1: MSB of VWE1STO
bit 2:
BRE = 0: normal operation
BRE = 1: RE output is blanking every second line in program scan mode
bit 3:
BWE = 0: normal operation
BWE = 1: WE2 output is blanking every second line in program scan mode
bit 4: BPRR: Blanking Phase Relation RE for program
BPRR = 0: AND connection HRDFL and HRE
BPRR = 1: AND connection HRDFLN and HRE
bit 5: BPRW: Blanking Phase Relation WE2 for program
BPRW = 0: AND connection HRDFL and HWE2
BPRW = 1: AND connection HRDFLN and HWE2
bit 6: BVRA: Blanking Vertical Reset Acquisition
BVRA = 0: reset blanking disabled
BVRA = 1: reset blanking enabled
bit 7: BVRD: Blanking Vertical Reset Display
BVRD = 0: reset blanking disabled
BVRD = 1: reset blanking enabled
Note
1. VWE1 programmable in steps of 1 line (64 µs).
1997 Jun 10
10
Philips Semiconductors
Objective specification
Memory controller
Table 4
SAA4952WP
Horizontal acquisition related pulses
ADDRESS
(HEX)
REGISTER
58
CLVSTA
start of clamp pulse
59
CLVSTO
stop of clamp pulse
FUNCTION
5A
HWE1STA
start of horizontal write enable 1 (lower 8 of 9 bits)
5B
HWE1STO
stop of horizontal write enable 1 (lower 8 of 9 bits)
5C
HAMSBDEL
bit 0: MSB of HWE1STA
bit 1: MSB of HWE1STO
bit 2: fine delay of HWE1 (LSB)
bit 3: fine delay of HWE1 (MSB)
bit 4: PWC05: Phase of Write Clock SWC05, determines the phase relationship of
SWC05 towards BLNA or HRA
bit 5: SFR: Select Field Recognition mode
bit 6: FRD: Field Recognition Disabled (FRD = 1)
bit 7: don’t care
5D
HVACQS1
VACQ sample pulse 1
5E
HVACQS2
VACQ sample pulse 2
Table 5
Mode registers
ADDRESS
(HEX)
REGISTER
60
MODE0
mode register 0; see Table 7
61
MODE1
mode register 1; see Table 10
Table 6
FUNCTION
Read registers
ADDRESS
(HEX)
REGISTER
81
FIELDINF2
FUNCTION
bit 0: bit 8 of field length measurement
bit 1: bit 9 of field length measurement (MSB)
bit 2: LSB of display field count
bit 3: field recognition for incoming source
bit 4: MSB of display field count
80
1997 Jun 10
FIELDINF1
result of field length measurement (lower 8 of 10 bits)
11
Philips Semiconductors
Objective specification
Memory controller
Table 7
SAA4952WP
Mode0 register description
REGISTER
BIT
NAME
REMARKS
MODE0
0 (LSB)
FSA0
frequency select acquisition 0; see Table 8
1
FSA1
frequency select acquisition 1; see Table 8
2
FSD0
frequency select display 0; see Table 9
3
FSD1
frequency select display 1; see Table 9
4
SDAF
select doubled acquisition frequency
SDAF = 0: normal operation
SDAF = 1: doubled acquisition frequency (2fa)
5
IMPIP
MPIP select bit
IMPIP = 0: normal operation
IMPIP = 1: MPIP mode active
6
INPIP
number of PIPs
INPIP = 0: 3 × 3 MPIP
INPIP = 1: 4 × 4 MPIP
7
GMOD
generator mode for display
GMOD = 0: normal operation
GMOD = 1: generator mode for display; field length measurement is
disabled
Table 8
Table 9
Acquisition frequency
FSA1
FSA0
FREQUENCY (MHz)
0
0
12.0
0
1
13.5
1
0
16.0
1
1
18.0
FSD1
FSD0
FREQUENCY (MHz)
0
0
27.0
0
1
27.0
1
0
32.0
1
1
36.0
Display frequency
1997 Jun 10
12
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
Table 10 Mode1 register description
REGISTER
BIT
NAME
REMARKS
MODE1
0
DR
1
STPWM1
2
STPWM2
stop writing to memory 2; still picture mode
3
SD0
select mode of display signal at pin 17; bit 0
4
GSC
golden SCART mode
display raster
stop writing to memory 1; still picture mode; STROBE signal can override still
picture mode
GSC = 0: normal operation
GSC = 1: golden SCART mode
5
SD1
6
EXTLLA
select mode of display signal at pin 17; bit 1; see Table 11
external acquisition clock
EXTLLA = 0: normal operation
EXTLLA = 1: LLA and horizontal reference pulse BLNA (horizontal reset)
from external digital source
7
VFS
vertical frequency select
VFS = 0: 100/120 Hz
VFS = 1: 50/60 Hz
Table 11 Signal mode at pin 17
SD1
SD0
MODE
0
0
horizontal signal HD at the output
0
1
vertical signal VD at the output
1
0
composite signal CD (derived from HD and VD by AND connection) at the output
1
1
composite signal CD at the output
Table 12 Display modes
CONTROL BITS
DISPLAY MODE (NUMBER OF LINES VALID FOR STANDARD PAL)
VFS(1)
SSC(2)
DR(3)
0
0
0
100 Hz (312.5 lines) ABAB raster
0
0
1
100 Hz (313, 312.5, 312 and 312.5 lines) AABB raster
0
1
0
not allowed
0
1
1
not allowed
1
0
0
50 Hz (625 lines) 1 : 1; non-interlaced
1
0
1
50 Hz (1250 lines) 2 : 1; interlaced
1
1
0
50 Hz (312.5 lines) 2 : 1
1
1
1
not allowed
Notes
1. VFS: Vertical Frequency Select; register MODE1; bit 7.
2. SSC: Select Single Clock SAA4952WP input pin 41.
3. DR: Display Raster; register MODE1; bit 0.
1997 Jun 10
13
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
Description of the acquisition part
CLV
LLA
The horizontal video clamping output pulse is generated
by the acquisition clock signal LLA and can be used as a
clamp pulse for the incoming luminance and chrominance
signals Y, U and V for the analog-to-digital converter.
The time reference of CLV is the LOW-to-HIGH transition
of the HRA signal. In comparison to the SAA4951WP the
signal CLV has no internal influence on the vertical
processing and is free programmable.
This is the main input clock pulse for the acquisition part of
the memory controller normally generated by an external
PLL circuit. Depending on the chosen system application
LLA operates on the different frequencies of 12, 13.5, 16
and 18 MHz. When SDAF = 1 these frequencies are
doubled to 24, 27, 32 and 36 MHz. The PLL circuit is
controlled by the Analog Burst Key pulse (ABK) provided
by an inserted synchronization circuit (i.e. TDA2579 or
TDA9141) and the horizontal reference signal (HRA)
supplied by the SAA4952WP.
WE1
A HIGH level on this output pin enables picture data to be
written to field memory 1. WE1 is a composite signal,
which includes the horizontal write enable signal (HWE1)
and the vertical write enable signal (VWE1). The position
of HWE1 can be programmed without restrictions.
SWC1
The acquisition clock input signal LLA is connected via the
memory controller circuit SAA4952WP. LLA is internally
buffered and output as serial write clock for memory 1.
Additionally SWC1 is used as a clock signal for the
analog-to-digital converter (e.g. TDA8755).
It is possible to delay the horizontal timing of WE1 by up to
three LLA clock cycles. WE1 operates at a vertical
frequency of 50/60 Hz.
SWC05
IE1
The signal SWC05 is obtained by dividing the clock LLA by
a factor of two. SWC05 is needed for feature concepts
containing new IC generations such as PALplus, LIMERIC
or PAN-IC.
This output signal is used as a data input enable for
memory 1. A logic HIGH level on this output pin enables
the data information to be written into field memory 1.
The still picture function is controlled via signal IE1. When
this mode is selected, IE1 is switched to a LOW level. It is
possible to disable the still picture mode with externally
supplied STROBE pulses. Using this function a live PIP
insertion into a frozen main picture is possible, as the write
pointer of memory 1 is still incremented, depending on the
level of WE1. The STROBE input is not sampled in the
controller. This means that the display part of the PIP
module should be synchronized to the IPQ write clock.
HRA/BLNA
The horizontal reference output pulse (HRA) is used as the
digital feedback pulse for the phase comparator of the
acquisition PLL. The duty cycle of the signal is 50%.
The positive edge of HRA indicates the internal counter
reset.
When the memory controller operates in a digital
environment, a horizontal reference signal (BLNA) and a
suitable acquisition clock pulse have to be supplied from
the externally used circuits (i.e. SAA7151A, DMSD and
SAA7157, CGC). The rising edge of BLNA resets the
internal horizontal acquisition counters of the
SAA4952WP.
1997 Jun 10
HVACQS
The vertical synchronization signal for the acquisition part
(VACQ) is sampled by the pulse HVACQS twice per line.
This signal consists of the two programmable pulses
HVACQS1 and HVACQS2 (see Fig.4). To ensure a save,
sampling the position of each pulse (two per line) can be
programmed in steps of four LLA clock cycles. The signal
is referenced to the rising edge of HRA.
14
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
Table 13 Horizontal programming range of CLV, HWE1 and HVACQS
Nr (programmed start value of corresponding signal) not equal Nf (programmed stop value of corresponding signal).
ACQUISITION FREQUENCY
(MHz)
TIMING EQUATIONS
PROGRAMMING RANGE
12
CLVr = (4Nr + 2)LLA
0 ≤ Nr < 191
CLVf = (4Nf + 2)LLA
0 ≤ Nf < 191
HWE1r = (2Nr + 2)LLA
0 ≤ Nr < 383
HWE1f = (2Nf + 2)LLA
0 ≤ Nf < 383
HVACQS1 = (4N(1) + 2)LLA
0 ≤ N < 191
HVACQS2 =
13.5
0 ≤ Nr < 215
0 ≤ Nf < 215
HWE1r = (2Nr + 2)LLA
0 ≤ Nr < 431
HWE1f = (2Nf + 2)LLA
0 ≤ Nf < 431
+ 2)LLA
0 ≤ N < 215
HVACQS2 = (4M(2) + 2)LLA
0 ≤ M < 215
CLVr = (4Nr + 2)LLA
0 ≤ Nr < 255
(4N(1)
CLVf = (4Nf + 2)LLA
0 ≤ Nf < 255
HWE1r = (2Nr + 2)LLA
0 ≤ Nr < 511
HWE1f = (2Nf + 2)LLA
0 ≤ Nf < 511
+ 2)LLA
0 ≤ N < 255
HVACQS2 = (4M(2) + 2)LLA
0 ≤ M < 255
CLVr = (8Nr + 2)LLA
0 ≤ Nr < 143
(4N(1)
CLVf = (8Nf + 2)LLA
0 ≤ Nf < 143
HWE1r = (4Nr + 2)LLA
0 ≤ Nr < 287
HWE1f = (4Nf + 2)LLA
0 ≤ Nf < 287
+ 2)LLA
0 ≤ N < 143
HVACQS2 = (8M(2) + 2)LLA
0 ≤ M < 143
HVACQS1 =
(8N(1)
Notes
1. N: programmed value of HVACQS1 pulse.
2. M: programmed value of HVACQS2 pulse.
The programmed values include the MSB setting contained in HAMSBDEL.
For SDAF = 1 the factors in front of Nr and Nf are doubled.
For EXTLLA = 1 the equations for LLA = 18 MHz are valid.
The programming margins depend on the used external clock frequency.
1
---------------------- × N ≤ 64 µs
LLAEXT
1997 Jun 10
0 ≤ M < 191
CLVf = (4Nf + 2)LLA
HVACQS1 =
18
+ 2)LLA
CLVr = (4Nr + 2)LLA
HVACQS1 =
16
(4M(2)
15
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
In the 50 Hz/1fH mode only one system clock is required.
The display, deflection and acquisition clocks are equal.
VACQ
This is the 50 Hz vertical synchronization input signal
derived from a suitable vertical synchronization circuit
(i.e. TDA2579). The LOW-to-HIGH transition of this pulse
is the timing reference of all vertical control signals of the
SAA4952WP.
SRC
The display clock input signal from inputs LLD or LLDFL is
buffered in the memory controller. Depending on the
selected mode one of them is output as Serial Read Clock
(SRC) for the field memories. Additionally SRC is used as
a clock pulse for the writing of memory 2, the noise
reduction circuit NORIC and the back-end circuit BENDIC
or for PROZONIC (instead of NORIC) and the following
DAC.
The vertical acquisition timing is illustrated in Fig.5. VWE1
is resynchronized with HWE1 internally. Nr and Nf can
represent values varying between 1 and 511, whereas Nf
should be programmed in accordance with the expected
field length (PAL 312, NTSC 262). If the incoming fields
are shorter than programmed the memory controller resets
VWE1 itself.
HRD
RSTW1
The Horizontal Reference Display pulse (HRD) has a duty
cycle of 50% and a frequency of 32 kHz. HRD is the
reference pulse for the horizontal timing of the control
signals RE1, RE2, WE2, HD and BLND generated by the
display part of the SAA4952WP in the event of a
three-clock system with a selected display frequency of
32 or 36 MHz.
The reset write output pulse 1 starts the write address
pointer of field memory 1. The RSTW1 signal is derived
from the 50 Hz vertical acquisition pulse (VACQ) and has
a pulse width of 32 µs.
STROBE
The asynchronous, active HIGH, STROBE input controls
the input enable signal IE1 to memory 1 in the still picture
mode (see Section “IE1”).
HVSP
The vertical display counter is incremented with every
HVSP pulse (see Fig.6). The HVSP signal is created from
the four pulses HVSP1 to HVSP4. The distance between
the pulses has to be programmed to 16 µs. The HVSP
signal is the equivalent to the HVACQS signal of the
vertical acquisition part. The HVSP1 pulse should be
programmed 32 µs after the HVACQS1 pulse. This
programming ensures that the vertical picture stability is
also kept in the event of unstable sources such as VCRs.
Display and deflection part
LLD
The input signal LLD is a line-locked clock for the display
side of the memory controller.
In the event of a two-clock system the possible display
frequencies (27, 32 and 36 MHz) are derived from one
switchable external PLL. The internal system clocks LLD is
supplied via the input LLDFL. The input pin LLD is not used
and its level can be fixed. This configuration is foreseen for
applications using the TDA9152 or other deflection
controllers which do not need a clock supply.
BLND
The output signal BLND is a horizontal blanking pulse and
is, for example, used for the peripheral circuits NORIC and
BENDIC. A LOW level indicates the blanking interval, a
HIGH level indicates valid data from the memories. It is
possible to delay the horizontal timing of BLND by up to
three LLD clock pulses.
In applications using the TDA9151 a 27 MHz clock is
always required. The system has to operate in a
three-clock mode. The deflection PLL generates the
27 MHz clock frequency only, whereas the display PLL
generates the 32 and 36 MHz in parallel, if conversion
modes are used which operate with these display
frequencies. If the display is operating with 27 MHz, LLD is
switched to the deflection PLL input and the third PLL can
be omitted. The 32 and 36 MHz PLL is synchronized on
the horizontal deflection pulse (HDFL). A digital feedback
signal (HRD) to the phase comparator is supplied by the
memory controller.
1997 Jun 10
WE2
A HIGH level on this output pin enables picture data to be
written to field memory 2. WE2 is a composite signal which
includes the horizontal write enable signal and the vertical
write enable signal. The horizontal timing of WE2 can be
delayed by up to three steps of LLD clock pulses.
16
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
HVCD
RE1
The memory controller supplies a display related output
which can generate, depending on the microcontroller
initialization, three different signals. The desired mode is
activated via microcontroller register MODE1 (control bits
SD0 and SD1).
The output RE1 is the read enable signal for field
memory 1. A HIGH level enables the picture data to be
read from the memory. RE1 is a composite signal and
includes the horizontal read enable timing (HRE) and the
vertical read enable timing (VRE). It is possible to delay the
horizontal timing of RE1 by up to three display clock
pulses. The horizontal timing of RE1 and RE2 is equal.
Table 14 Mode setting of SAA4952WP output HVCD
SD1 SD0
MODE OF OUTPUT PIN 17
RE2
0
0
horizontal output signal HD; programmable
via HDSTA and HDSTO
0
1
vertical output signal VD; programmable via
VDSTA and VDSTO
1
X
composite output signal HVCD; logical
AND connection of HD and VD
The output RE2 is the read enable signal for field
memory 2. A HIGH level enables the picture data to be
read from memory. RE2 is a composite signal and includes
the horizontal read enable timing (HRE) and the vertical
read enable timing (VRE2). The horizontal timing of RE2
can be delayed by up to three display clock pulses.
The new memory controller supplies two completely
independent VRE signals, VRE1 and VRE2. VRE1 is not
generated as an adjustable delay of VRE2 as in the
SAA4951WP.
IE2
This output signal is used as data input enable for
memory 2. A logic HIGH level on this output pin enables
the data information to be written to field memory 2.
Table 15 Programming range of horizontal display signals (BLND, HRE, HWE2, HD and HVSP1 to HVSP4); see Fig.6
Nr (programmed start (rise) value of corresponding signal) not equal Nf (programmed stop (fall) value of corresponding
signal).
ACQUISITION FREQUENCY
(MHz)
TIMING EQUATIONS
PROGRAMMING RANGE
27
HDSPr = (2Nr + 2)LLD
0 ≤ Nr < 431
HDSPf = (2Nf + 2)LLD
0 ≤ Nf < 431
HVSPn
32
=
(4N(2)
+ 2)LLD
0 ≤ Nr < 511
HDSPf = (2Nf + 2)LLD
0 ≤ Nf < 511
(1)
=
(4N(2)
+ 2)LLD
0 ≤ N < 255
HDSPr = (4Nr + 4)LLD
0 ≤ Nr < 287
HDSPf = (4Nf + 4)LLD
0 ≤ Nf < 287
HVSPn
(1)
=
(8N(2)
+ 4)LLD
Notes
1. HVSPn = HVSP1 to HVSP4.
2. N: programmed value of HVSP pulse.
LLD equals LLDFL for 27 MHz display in the three-clock system.
LLD input is not used in the two-clock mode (internally switched to LLDFL input).
The programmed values include the MSB settings contained in HDMSB.
1997 Jun 10
0 ≤ N < 215
HDSPr = (2Nr + 2)LLD
HVSPn
36
(1)
17
0 ≤ N < 145
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
The vertical display signal can be programmed in a range
of Nr, Nf from 1 to 511. The setting should correspond to
the source (PAL, NTSC) and the expected standard field
length. For the display the vertical read window should not
exceed the write window. In the event of non-standard
sources with shortened field lengths the memory controller
disables the vertical control signals if the programmed
STOP setting cannot be reached.
WRD
This is the write/read enable control signal supplied by the
microcontroller. The HIGH-to-LOW transition of WRD
indicates valid data.
P0 TO P7
The SAA4952WP is controlled by the bidirectional parallel
port bus P0 to P7 of a microcontroller. Address and data
are transmitted sequentially on the parallel bus.
LLDFL
The input signal LLDFL is the main line-locked clock pulse
for the display and deflection part generated by an external
PLL circuit. The frequency of LLDFL is 27, 32 or 36 MHz
for a two-clock system. It is fixed to 27 MHz if the
three-clock system is chosen. In this mode, display clocks
of 32 and 36 MHz are generated by an extra display PLL.
The PLL circuit operates on the burst key pulse (ABK) of
the acquisition part and the horizontal reference signal
HRDFL generated by the deflection part of the memory
controller.
TEST
The TEST input pin has to be connected to ground.
SDP
The SDP input pin has to be connected to ground for a
three-clock system. This configuration has to be chosen if
the TDA9151 is controlling the deflection. Connecting SDP
to the supply voltage switches the memory controller into
the two-clock mode.
The LLDFL should not fall below 24 MHz because this
clock is used to sample the input signals at the memory
controller port (P0 to P7), ALE and WRD.
Table 16 SDP mode pin setting
SDP
REMARK
HRDFL
0
three-clock system; supports TDA9151
This horizontal output signal is the reference pulse for the
horizontal deflection drive signal HDFL. The duty cycle of
HRDFL is 50% and the cycle time is 64 µs (PAL). For the
golden SCART mode the cycle time is reduced to 32 µs.
1
two-clock system
SSC
The Select Single Clock (SSC) control pin has to be
connected to ground to activate a 2fH mode and a multi
clock system. For the 50 Hz/1fH mode in a single clock
system the input is connected to the supply (VDD).
VDFL
This is the vertical synchronization output signal generated
by the vertical deflection part of the memory controller.
The timing reference of VDFL is the LOW-to-HIGH
transition of the vertical acquisition input pulse VACQ.
Normally VDFL has a pulse width of 2.5 × HDFL = 80 µs
and a cycle time of 100 Hz.
Table 17 SCC mode pin setting
SCC
HDFL
The output signal HDFL is used for driving the connected
horizontal deflection circuit. HDFL has a cycle time of
32 µs and a pulse width of 64 × LLDFL = 2.37 µs in the 2fH
mode (see Fig.8).
0
2fH mode (100/120 Hz; progressive scan);
two-clock or three-clock system
1
1fH mode (50/60 Hz; 15.625/15.75 kHz);
single clock system
TIMING SPECIFICATION
The internal delays of the output signals referenced to the
respective clock are given in Table 18.
Control inputs and outputs
ALE
The address latch enable input signal ALE is provided by
the microcontroller. A falling edge of ALE denotes a valid
address.
1997 Jun 10
REMARK
18
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
Table 18 Delay table (see Fig.9)
Worst case conditions: VDD = 4.5 V and Tamb = 85 °C. Typical case conditions: VDD = 5 V and Tamb = 25 °C.
CLK
OUTPUT
LOAD
(pF)
th(min)
(ns)
th(typ)
(ns)
tpd(max)
(ns)
tpd(typ)
(ns)
LLA
SWC1
15
2
3
11
8
LLA
SWC05
15
4
5
13
10
LLD
SRC
45
3
4
10
8
LLDFL(1)
SRC
45
3
4
10
8
LLA
WE1
15
7
8
18
13
LLD
WE2
10
7
8
18
13
LLD
RE1
10
8
9
18
13
LLD
RE2
10
7
7
18
13
LLDFL
HDFL
25
7
7
12
10
LLD
BLND
25
8
9
19
13
LLD
HVCD
25
8
8
20
15
LLA
CLV
25
7
8
12
10
LLDFL
VDFL
25
7
7
12
9
Note
1. Source for SRC depends on the setting of register MODE0 and the level on the SDP pin.
handbook, full pagewidth
HRA
CLVr
CLV
CLVf
HWE1r
HWE1
HWE1f
HVACQS1
HVACQS
HVACQS2
MHA725
Fig.4 Horizontal acquisition timing.
1997 Jun 10
19
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
handbook, full pagewidth
VACQ
Vr(WE1)(1)
VWE1
Vf(WE1)(2)
RSTW1
MHA726
(1) Vr(WE1) = Nr × line.
(2) Vf(WE1) = Nf × line.
Fig.5 Vertical acquisition timing.
handbook, full pagewidth
HRD or
HRDFL
HDSPr
HDSP(1)
HDSPf
HVSPn(2)
HVSP(2)
MHA727
(1) HDSP = BLND, HRE and HWE2.
(2) HVSP consists of the 4 pulses HVSP1 to HVSP4 (HVSPn).
Fig.6 Programmable horizontal display signals.
1997 Jun 10
20
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
handbook, full pagewidth
VACQ
VDSPr
VDSP
VDSPf
RSTW2
MHA728
Fig.7 Vertical display timing [VDSP = V(WE2) and V(RE1/2)].
1728 × LLDFL
handbook, full pagewidth
HRDFL
864 × LLDFL
HDFL
64 × LLDFL
64 × LLDFL
Fig.8 Horizontal deflection timing (example for 27 MHz).
1997 Jun 10
21
MHA729
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
handbook, full pagewidth
CLK
OUTPUT
th
tpd
MHA733
Fig.9 Timing diagram.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
VDD
supply voltage
−0.5
MAX.
UNIT
+6.0
V
Vi
input voltage
−0.5
VDD + 0.5
V
fclk
clock frequency
−
38
MHz
Tstg
storage temperature
−40
+125
°C
Tamb
operating ambient temperature
0
85
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth j-c
1997 Jun 10
PARAMETER
thermal resistance from junction to case
22
VALUE
UNIT
46
K/W
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
CHARACTERISTICS
VDD = 5 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
VDD
supply voltage
4.5
TYP.
MAX.
UNIT
5
5.5
V
IDD
supply current
−
35
−
mA
facq
acquisition frequency
−
−
33
MHz
fLLDFL,LLD
operating frequency of display and deflection part note 1
24
−
37
MHz
Ci
input capacitance
−
10
15
pF
VIL
LOW level input voltage
−
−
0.8
V
VIH
HIGH level input voltage
2.0
−
−
V
VOL
LOW level output voltage
Io = 4 mA; note 2
VOH
HIGH level output voltage
Io = −4 mA; note 2 2.4
Tj
junction temperature
Tamb
operating ambient temperature
−
−
0.4
V
3.4
−
V
−
−
125
°C
0
−
85
°C
Notes
1. fmin = 24 MHz for LLDFL, if the data at the microcontroller port P0 to P7, ALE and WRD is supplied from a
microcontroller clocked with 12 MHz.
2. For SRC Io = ±8 mA.
APPLICATION INFORMATION
SAA4990H
Figure 10 illustrates a block diagram of the application
environment of the memory controller SAA4952WP.
The full option chip set of the new TV feature system
controlled by the I2C-bus includes the following circuits:
Progressive scan-Zoom and Noise reduction IC
(PROZONIC) with line flicker reduction.
SAA4991WP
ADC.
The Motion Estimation/Compensation Line flicker
reduction ZOom and Noise reduction IC is abbreviated as
MELZONIC.
SAA4955TJ
SAA4952WP
3 Mbit video RAM.
Memory controller.
SAA4995WP
S87C654-4A44
PANorama-IC (PAN-IC) for linear horizontal zoom and
compression, non-linear (panorama) horizontal aspect
ratio conversion.
Microcontroller.
TDA8755
SAA7165
VEDA2, DAC with digital CTI and luminance peaking.
1997 Jun 10
23
24
3
ABK
VACQ
STROBE
VDFL
I2C-bus
YUV
CLV
SWC1
7
VCO
WE2
24
33
SAA4990H
PROZONIC
12
27 MHz
LLDFL
HDFL
VDFL
TDA9151
DEFLECTION
PROGRESSIVE
24
SCAN, LFR,
VERTICAL ZOOM,
NOISE
REDUCTION
CROSS-COLOUR
REDUCTION
27 MHz
VCO
deflection
PD
CLV
37
38
HRDFL LLDFL
35
Fig.10 Application diagram.
HDFL
display
RE1
4 20 18 19
SRC
32, 36 MHz
LLD
43
VCO
HRD
PD
1
SAA4952WP
MEMORY CONTROLLER
8 42 14 15
12, 13.5, 16
18 MHz
LLA
13
3
IE1
acquisition
PD
HRA
39
11
9
16
21,22
25 to 32
2 × SAA4955TJ
MEMORY BLOCK
RE2 output
VEDA2
MHA730
VIDEO
ENHANCED
DAC
CTI, PEAKING
SAA7165
H
V
YUV
I2C-bus
3
Memory controller
SNERT-bus
2
P83C652/4FBA
P0 to P7
ALE, WRD
RSTR
COMP
SWC1
MICROCONTROLLER
CLV
TDA8755
12
WE1
ADC
RSTW1
1997 Jun 10
HVCD
dbook, full pagewidth
IE2
RE1 output
Philips Semiconductors
Objective specification
SAA4952WP
Application diagrams
12
Y
U
V
12
12
LPF
LPF
ADC
PAN-IC
TDA8755
SAA4995WP
MEMORY 1
12
1 × SAA4955TJ
12
LPF
MEMORY 2
PROZONIC
12
SAA4990H
VERTICAL ZOOM
LINE FLICKER
REDUCTION
NOISE AND
CROSS-COLOUR
REDUCTION
12
1 × SAA4955TJ
12
25
fA
2
I2C-bus
SAA7165
U
CTI
Y-PEAKING
DAC
V
video processor
TDA4780
RGB output stages
TDA6111
I2C-bus
VCO2
HD, VD
SAA4952WP
CONTROL
Y
VEDA2
fD
CONTROL
MEMORY
CONTROLLER
VCO1
HA, VA
Philips Semiconductors
Memory controller
dbook, full pagewidth
1997 Jun 10
FEATURE CONNECTOR
to
deflection
processor
DATA
8
MICROCONTROLLER
SNERT-bus
S87C654
MHA731
Objective specification
SAA4952WP
Fig.11 Block diagram of a full-options IPQ module MK6.
12
Y
U
V
12
12
LPF
LPF
ADC
PAN-IC
TDA8755
SAA4995WP
12
LPF
MELZONIC
MEMORY 1
12
1 × SAA4955TJ
MEMORY 2
SAA4991WP
12
MOTION ESTIMATION
AND COMPENSATION
LINE FLICKER
REDUCTION
NOISE AND
CROSS-COLOUR
REDUCTION
VERTICAL ZOOM
12
1 × SAA4955TJ
12
26
fA
SAA7165
U
CTI
Y-PEAKING
DAC
V
video processor
TDA4780
RGB output stages
TDA6111
I2C-bus
VCO2
HD, VD
SAA4952WP
CONTROL
to
deflection
processor
DATA
2
I2C-bus
Y
VEDA2
fD
CONTROL
MEMORY
CONTROLLER
VCO1
HA, VA
Philips Semiconductors
Memory controller
book, full pagewidth
1997 Jun 10
FEATURE CONNECTOR
8
MICROCONTROLLER
SNERT-bus
S87C654
MHA732
Objective specification
SAA4952WP
Fig.12 Block diagram of a full-options IPQ module MK7.
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
PACKAGE OUTLINE
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
eD
eE
y
X
39
A
29
28
40
ZE
bp
b1
w M
44
1
E
HE
pin 1 index
A
A4 A1
e
(A 3)
6
β
18 k 1
Lp
k
7
detail X
17
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
A
A1
min.
A3
A4
max.
bp
b1
mm
4.57
4.19
0.51
0.25
3.05
0.53
0.33
0.81
0.66
0.180
inches
0.020 0.01
0.165
D (1)
E (1)
e
eD
eE
HD
HE
k
16.66 16.66
16.00 16.00 17.65 17.65 1.22
1.27
16.51 16.51
14.99 14.99 17.40 17.40 1.07
k1
max.
Lp
v
w
y
0.51
1.44
1.02
0.18
0.18
0.10
Z D(1) Z E (1)
max. max.
2.16
β
2.16
45 o
0.630 0.630 0.695 0.695 0.048
0.057
0.021 0.032 0.656 0.656
0.020
0.05
0.007 0.007 0.004 0.085 0.085
0.12
0.590 0.590 0.685 0.685 0.042
0.040
0.013 0.026 0.650 0.650
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT187-2
112E10
MO-047AC
1997 Jun 10
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-02-25
27
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Jun 10
28
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jun 10
29
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
NOTES
1997 Jun 10
30
Philips Semiconductors
Objective specification
Memory controller
SAA4952WP
NOTES
1997 Jun 10
31
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© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
547047/20/01/pp32
Date of release: 1997 Jun 10
Document order number:
9397 750 01973