INTEGRATED CIRCUITS
DATA SHEET
PCF8535
65 × 133 pixel matrix driver
Objective specification
File under Integrated Circuits, IC12
1999 Aug 24
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
CONTENTS
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
Block diagram functions
Oscillator
Power-on reset
I2C-bus controller
Input filters
Display data RAM
Timing generator
Address counter
Display address counter
6
PINNING
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
Pin functions
R0 to R64
C0 to C132
VSS1 and VSS2
VDD1 to VDD3
VLCDOUT
VLCDIN
VLCDSENSE
SDA
SDAOUT
SCL
SA0 and SA1
OSC
RES
T1, T2, T3, T4 and T5
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Reset
Power-down
LCD voltage selector
Oscillator
Timing
Column driver outputs
Row driver outputs
Drive waveforms
Set multiplex rate
1999 Aug 24
2
7.10
7.10.1
7.11
7.11.1
7.12
7.12.1
7.13
7.13.1
7.14
7.14.1
7.15
7.15.1
7.15.2
7.16
7.16.1
7.16.2
7.16.3
7.16.4
7.16.5
7.16.6
7.17
7.17.1
7.17.2
Bias system
Set bias system
Temperature measurement
Temperature read back
Temperature compensation
Temperature coefficients
VOP
Set VOP value
Voltage multiplier control
S[1:0]
Addressing
Input addressing
Output addressing
Instruction set
RAM read/write command page
Function and RAM command page
Display setting command page
HV-gen command page
Special feature command page
Instruction set
I2C-bus interface
Characteristics of the I2C-bus
I2C-bus protocol
8
LIMITING VALUES (PROVISIONAL)
9
HANDLING
10
DC CHARACTERISTICS
11
AC CHARACTERISTICS
12
RESET TIMING
13
APPLICATION INFORMATION
14
BONDING PAD LOCATIONS
15
DEVICE PROTECTION DIAGRAM
16
TRAY INFORMATION
17
DEFINITIONS
18
LIFE SUPPORT APPLICATIONS
19
PURCHASE OF PHILIPS I2C COMPONENTS
20
BARE DIE DISCLAIMER
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
1
PCF8535
FEATURES
• Single-chip LCD controller/driver
• 65 row, 133 column outputs
• Display data RAM 65 × 133 bits
• 133 icons (last row is used for icons)
• Fast mode I2C-bus interface (400 kbits/s)
• Software selectable multiplex rates:
1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65
2
APPLICATIONS
• On-chip:
• Telecommunication systems
• Automotive information systems
– Generation of intermediate LCD bias voltages
• Point-of-sale terminals
– Oscillator requires no external components
(external clock also possible)
• Instrumentation.
– Generation of VLCD.
3
• CMOS compatible inputs
GENERAL DESCRIPTION
The PCF8535 is a low power CMOS LCD row/column
driver, designed to drive dot matrix graphic displays at
multiplex rates of 1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65.
Furthermore, it can drive up to 133 icons. All necessary
functions for the display are provided in a single chip,
including on-chip generation of LCD bias voltages,
resulting in a minimum of external components and low
power consumption. The PCF8535 is compatible with
most microcontrollers and communicates via an industry
standard two-line bidirectional I2C-bus serial interface.
All inputs are CMOS compatible.
• Software selectable bias configuration
• Logic supply voltage range VDD1 to VSS1 4.5 to 5.5 V
• Supply voltage range for high voltage part VDD2 and
VDD3 to VSS2 and VSS3 4.5 to 5.5 V
• Display supply voltage range VLCD to VSS:
– Mux rate 1 : 65: 8 to 16 V.
• Low power consumption, suitable for battery operated
systems
• Internal Power-on reset and/or external reset
• Temperature read back available
• Manufactured in N-well silicon gate CMOS process.
4
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8535U
1999 Aug 24
−
DESCRIPTION
chip with bumps in tray
3
VERSION
−
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
5
PCF8535
BLOCK DIAGRAM
ROW
DRIVERS
VSS2
COLUMN
DRIVERS
INTERNAL
RESET
T1, T2, T3
DATA LATCHES
VLCDIN
VDD3
POWER-ON RESET
PCF8535
T4, T5
VDD2
133
65
VSS1
VDD1
C0 to C132
R0 to R64
handbook, full pagewidth
BIAS
VOLTAGE
GENERATOR
RES
OSCILLATOR
MATRIX
LATCHES
TIMING
GENERATOR
VLCDSENSE
VLCDOUT
DISPLAY DATA RAM
VLCD
GENERATOR
SCL
SDA
SDAOUT
MATRIX DATA
RAM
INPUT
FILTERS
I2C-BUS
CONTROL
COMMAND
DECODER
DISPLAY
ADDRESS
COUNTER
ADDRESS
COUNTER
MGS669
SA1
SA0
Fig.1 Block diagram.
1999 Aug 24
4
OSC
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
5.1
5.1.1
PCF8535
5.1.5
Block diagram functions
The PCF8535 contains a 65 × 133 bit static RAM which
stores the display data. The RAM is divided into 9 banks of
133 bytes. The last bank is used for icon data and is only
one bit deep. During RAM access, data is transferred to
the RAM via the I2C-bus interface. There is a direct
correspondence between the X address and the column
output number.
OSCILLATOR
The on-chip oscillator provides the display clock for the
system; it requires no external components. Alternatively,
an external display clock may be provided via the OSC
input. The OSC input must be connected to VDD1 or VSS1
when not in use. During power-down additional current
saving can be made if the external clock is disabled.
5.1.2
5.1.6
POWER-ON RESET
I2C-BUS CONTROLLER
5.1.7
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel).
The PCF8535 acts as an I2C-bus slave and therefore
cannot initiate bus communication.
5.1.4
ADDRESS COUNTER
The Address Counter (AC) sends addresses to the Display
Data RAM (DDRAM) for writing.
5.1.8
DISPLAY ADDRESS COUNTER
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on or off, normal or inverse
video) is set via the I2C-bus.
INPUT FILTERS
Input filters are provided to enhance noise immunity in
electrically adverse environments; RC low-pass filters are
provided on the SDA, SCL and RES lines.
1999 Aug 24
TIMING GENERATOR
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data bus.
The on-chip Power-on reset initializes the chip after
power-on or power failure.
5.1.3
DISPLAY DATA RAM
5
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
6
PCF8535
PINNING
SYMBOL
PAD
DESCRIPTION
1
dummy pad
2
bump/alignment mark 1
3 to 18
LCD row driver outputs
C0 to C132
19 to 151
LCD column driver outputs
R47 to R33
152 to 166
LCD row driver outputs
167
bump/alignment mark 2
R0 to R15
R48 to R64
168
dummy pad
169 to 185
LCD row driver outputs; R64 is icon row
186
bump/alignment mark 3
187 to 189
dummy pad
OSC
190
oscillator
VLCDIN
191 to 196
LCD supply voltage
VLCDOUT
197 to 203
voltage multiplier output
VLCDSENSE
204
voltage multiplier regulation input (VLCD)
205 and 206
dummy pad
RES
207
external reset input (active LOW)
T3
208
test output 3
T2
209
test output 2
T1
210
test output 1
VDD2
211 to 218
supply voltage 2
VDD3
219 to 222
supply voltage 3
VDD1
223 to 228
supply voltage 1
229
dummy pad
SDA
230 and 231
I2C-bus serial data inputs
SDAOUT
232
I2C-bus serial data output
SA1
233
I2C-bus slave address input
SA0
234
I2C-bus slave address input
VSS2
235 to 242
ground 2
VSS1
243 to 250
ground 1
T5
251
test input 5
T4
252
test input 4
253
dummy pad
254 and 255
I2C-bus serial clock inputs
256
bump/alignment mark 4
257 to 273
LCD row driver outputs
SCL
R32 to R16
6.1
6.1.1
Pin functions
R0 TO R64
These pads output the display row signals.
1999 Aug 24
6
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
6.1.2
PCF8535
C0 TO C132
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8535
will not be able to create a valid logic 0 level. By splitting
the SDA input from the SDAOUT output the device could
be used in a mode that ignores the acknowledge bit.
In COG applications where the acknowledge cycle is
required or where read back is required, it is necessary to
minimize the track resistance from the SDAOUT pad to the
system SDA line to guarantee a valid LOW level.
These pads output the display column signals.
6.1.3
VSS1 AND VSS2
VSS1 and VSS2 must be connected together.
6.1.4
VDD1 TO VDD3
VDD1 is the logic supply. VDD2 and VDD3 are for the voltage
multiplier. For split power supplies VDD2 and VDD3 must be
connected together. If only one supply voltage is available,
all three supplies must be connected together.
6.1.5
6.1.10
I2C-bus serial clock input.
6.1.11
VLCDOUT
Table 1
VLCDIN
This is the VLCD supply for when an external VLCD is used.
If the internal VLCD generator is used, then VLCDOUT and
VLCDIN must be connected together. VLCDIN should not be
driven when VDD1 is below its minimum allowed value,
otherwise a low impedance path between VLCDIN and VSS1
will exist.
6.1.7
MODE
SLAVE ADDRESS
0 and 0
write
78H
read
79H
0 and 1
write
7AH
read
7BH
1 and 0
write
7CH
read
7DH
write
7EH
read
7FH
1. The slave address is a concatination of the following
bits {01111, SA1, SA0 and R/W}.
6.1.12
OSC
If the on-chip oscillator is used this input must be
connected to VDD1 or VSS1.
6.1.13
SDA
RES
External reset pad: when this pad is LOW the chip will be
reset; see Section 7.1. If an external reset is not required,
this pad must be tied to VDD1. Timing for the RES pad is
given in Chapter 12.
SDAOUT
SDAOUT is the serial data acknowledge for the I2C-bus.
By connecting SDAOUT to SDA externally, the SDA line
becomes fully I2C-bus compatible. Having the
acknowledge output separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAOUT pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
1999 Aug 24
SA1 AND SA0
Note
VLCDSENSE
I2C-bus serial data input.
6.1.9
Slave address; see note 1
1 and 1
This is the input to the internal voltage multiplier regulator.
It must be connected to VLCDOUT when the internal voltage
generator is used otherwise it may be left open-circuit.
VLCDSENCE should not be driven when VDD1 is below its
minimum allowed value, otherwise a low impedance path
between VLCDSENCE and VSS1 will exist.
6.1.8
SA0 AND SA1
Least significant bits of the I2C-bus slave address.
If, in the application, an external VLCD is used, VLCDOUT
must be left open-circuit; otherwise (if the internal voltage
multiplier is enabled) the chip may be damaged. VLCDOUT
should not be driven when VDD1 is below its minimum
allowed value otherwise a low impedance path between
VLCDOUT and VSS1 will exist.
6.1.6
SCL
6.1.14
T1, T2, T3, T4 AND T5
In applications T4 and T5 must be connected to VSS.
T1, T2 and T3 are to be left open-circuit.
7
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7
PCF8535
FUNCTIONAL DESCRIPTION
The PCF8535 is a low power LCD driver designed to interface with microprocessors/microcontrollers and a wide variety
of LCDs.
The host microprocessor/microcontroller and the PCF8535 are both connected to the I2C-bus. The SDA and SCL lines
must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external
components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip.
The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and suitable
capacitors for decoupling VLCD and VDD.
VLCD
handbook, full pagewidth
VDD1,
VDD3
VDD(I2C)
VDD2
VDD1 to VDD3
133 column drivers
65 row drivers
PCF8535
LCD PANEL
VSS2
Rpu
VSS1
Rpu
HOST
MICROPROCESSOR/
MICROCONTROLLER
VSS
RES
SA0
SA1
SCL
SDA
VSS1, VSS2
MGS670
Fig.2 Typical system configuration.
1999 Aug 24
8
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.1
PCF8535
7.3
Reset
LCD voltage selector
The PCF8535 has two reset modes; internal Power-on
reset or external reset. Reset initiated from either the RES
pad or the internal Power-on reset block will initialize the
chip to the following starting condition:
The practical value for VOP is determined by equating
Voff(rms) with defined LCD threshold voltage (Vth), typically
when the LCD exhibits approximately 10% contrast.
• Power-down mode (PD = 1)
7.4
• Horizontal addressing (V = 0); no mirror X or Y
(MX = 0 and MY = 0)
The internal logic operation and the multi-level drive
signals of the PCF8535 are clocked by the built-in RC
oscillator. No external components are required.
• Display blank (D = 0 and E = 0)
• Address counter X[6:0] = 0, Y[2:0] = 0 and XM0 = 0
7.5
• Bias system BS[2:0] = 0
• Temperature control mode TC[2:0] = 0
• HV-gen control, HVE = 0 the HV generator is switched
off, PRS = 0 and S[1:0] = 00
7.6
• VLCDOUT is equal to 0 V
Column driver outputs
The LCD drive section includes 133 column outputs
(C0 to C132) which should be connected directly to the
LCD. The column output signals are generated in
accordance with the multiplexed row signals and with the
data in the display latch. When less than 133 columns are
required the unused column outputs should be left
open-circuit.
• RAM data is unchanged (Note: RAM data is undefined
after power-up)
• All row and column outputs are set to VSS (display off)
• TRS and BRS are set to zero
• Direct mode is disabled (DM = 0)
• Internal oscillator is selected, but not running (EC = 0)
• Bias current set to low current mode (IB = 0).
7.7
Row driver outputs
The LCD drive section includes 65 row outputs
(R0 to R64) which should be connected directly to the
LCD. The row output signals are generated in accordance
with the selected LCD drive mode. If lower Mux rates or
less than 65 rows are required, the unused outputs should
be left open-circuit.
Power-down
During power-down all static currents are switched off (no
internal oscillator, no timing and no LCD segment drive
system) and all LCD outputs are internally connected to
VSS. The serial bus function remains active.
1999 Aug 24
Timing
The timing of the PCF8535 organizes the internal data flow
of the device. The timing also generates the LCD frame
frequency which is derived from the clock frequency
generated in the internal clock generator.
• Multiplex rate M[2:0] = 0 (Mux rate 1 : 17)
7.2
Oscillator
9
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.8
PCF8535
Drive waveforms
frame n + 1
frame n
ROW 0
R0 (t)
ROW 1
R1 (t)
COL 0
C0 (t)
COL 1
C1 (t)
Vstate1(t)
Vstate2 (t)
VLCD
V2
V3
V4
V5
VSS
VLCD
V2
V3
V4
V5
VSS
VLCD
V2
V3
V4
V5
VSS
VLCD
V2
V3
V4
V5
VSS
VLCD − VSS
V3 − VSS
Vstate1(t)
VLCD − V2
0V
V3 − VSS
V4 − V5
0V
VSS − V5
V4 − VLCD
VSS − VLCD
VLCD − VSS
V3 − VSS
Vstate2 (t)
VLCD − V2
0V
V3 − VSS
V4 − V5
0V
VSS − V5
V4 − VLCD
VSS − VLCD
0 1 2 3 4 5 6 7 8...
... 64 0 1 2 3 4 5 6 7 8...
Vstate1(t) = C1(t) − R0(t).
Vstate2(t) = C1(t) − R1(t).
Fig.3 Typical LCD driver waveforms.
1999 Aug 24
10
... 64
MGS671
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.9
PCF8535
Set multiplex rate
The PCF8535 can be used to drive displays of varying sizes. The multiplex mode selected controls which rows are used.
In all cases, the last row is always driven and is intended for icons. If Top Row Swap (TRS) is at logic 1 then the icon row
will be output on pad R48. M[2:0] selects the multiplex rate (see Table 2).
Table 2
Multiplex rates
M[2]
M[1]
M[0]
MULTIPLEX RATE
ACTIVE ROWS
0
0
0
1 : 17
R0 to R15 and R64
0
0
1
1 : 26
R0 to R24 and R64
0
1
0
1 : 34
R0 to R32 and R64
0
1
1
1 : 49
R0 to R47 and R64
1
0
0
1 : 65
R0 to R64
do not use
−
101 − 111
7.10
Bias system
7.10.1
SET BIAS SYSTEM
The bias voltage levels are set in the ratio of R − R − nR − R − R. Different multiplex rates require different factors n. This
is programmed by BS[2:0]. For optimum bias values, n can be calculated from: n =
Mux rate – 3
Changing the bias system from the optimum will have a consequence on the contrast and viewing angle. One reason to
come away from the optimum would be to reduce the required VOP. A compromise between contrast and VOP must be
found for any particular application.
Table 3
Programming the required bias system
BS[2]
0
BS[1]
0
BS[0]
0
n
BIAS MODE
TYPICAL MUX RATES
7
1/
11
1/
10
1/
9
1/
8
1/
7
1/
6
1/
5
1/
4
1 : 100
0
0
1
6
0
1
0
5
0
1
1
4
1
0
0
3
1
0
1
2
1
1
0
1
1
1
1
0
1999 Aug 24
11
1 : 80
1 : 65
1 : 49
1 : 33
1 : 26
1 : 17
1:9
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
Table 4
BIAS VOLTAGE FOR 1/7BIAS
V1
V2
V3
V4
V5
VLCD
6/
7
5/
7
2/
7
1/
7
V6
7.11.1
For calibrating the temperature read-out a measurement
must be taken at a defined temperature. The offset
between the ideal read-out and the actual result has to be
stored into a non-volatile register (e.g. EEPROM);
Offset = TR ideal – TR meas
(2)
Example of LCD bias voltage for 1/7bias, n = 3
SYMBOL
7.11
PCF8535
× VLCD
× VLCD
where TRmeas is the actual temperature read-out of the
PCF8535.
× VLCD
× VLCD
The calibrated temperature read-out can be calculated for
each measurement as follows:
TR cal = TR meas + Offset
(3)
VSS
Temperature measurement
The accuracy after the calibration is ±6.7% (plus ±1 lsb) of
the difference between the current temperature and the
calibration temperature. For this reason a calibration at or
near the most sensitive temperature for the display is
recommended.
TEMPERATURE READ BACK
The PCF8535 has an in-built temperature sensor.
For power saving, the sensor should only be enabled
when a measurement is required. It will not operate in
power-down mode. The temperature read back requires a
clock to operate. Normally the internal clock is used but, if
the device is operating from an external clock, then this
must be present for the measurement to work. VDD2 and
VDD3 must also be applied. A measurement is initialized by
setting the SM bit. Once started the SM bit will be
automatically cleared. An internal oscillator will be
initialized and allowed to warm-up for approximately
2 frame periods. After this the measurement starts and
lasts for a maximum of 2 frame periods.
E.g. for a calibration at 25 °C with the current temperature
at −20 °C, the absolute error may be calculated as:
Absolute error = 0.067 × (25 °C − −20 °C)
= ±3 °C + ±1 lsb = ±4.17 °C.
7.12
7.12.1
In the PCF8535 the temperature coefficient of VLCD can be
selected from 8 values by setting bits TC[2:0],
see Table 5.
(1)
where T is the on-chip temperature in °C and c is the
conversion constant; c = 1.17 °C/lsb.
To improve the accuracy of the temperature measurement
a calibration is recommended during the assembly of the
final product.
1999 Aug 24
TEMPERATURE COEFFICIENTS
Due to the temperature dependency of the liquid crystals
viscosity the LCD controlling voltage, V must be increased
at lower temperatures to maintain optimum contrast.
Figure 4 shows VLCD as a function of temperature for a
typical high multiplex rate liquid.
Temperature data is returned via a status register. During
the measurement the register will contain zero. Once the
measurement is completed the register will be updated
with the current temperature (non zero value). Because
the I2C-bus interface is asynchronous to the temperature
measurement, read back prior to the end of the
measurement is not guaranteed. If this mode is required
the register should be read twice to validate the data.
The ideal temperature read-out can be calculated as
follows;
1
TR ideal = 128 + ( T – 27 °C ) × --c
Temperature compensation
12
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
handbook, halfpage
MGS473
VLCD
0 °C
T
Fig.4 VLCD as function of liquid crystal temperature (typical values).
Table 5
TC[2]
TC[1]
TC[0]
TC VALUE
UNIT
0
0
0
0
1/°C
10−3
1/°C
0
0
1
−0.44 ×
0
1
0
−1.10 × 10−3
1/°C
10−3
1/°C
0
1
1
−1.45 ×
1
0
0
−1.91 × 10−3
1/°C
1
0
1
−2.15 × 10−3
1/°C
0
−2.32 ×
10−3
1/°C
−2.74 ×
10−3
1/°C
1
1
1
1
7.13
The low range offers programming from 4.5 to 10.215 V,
with the high range from 10.215 to 15.93 V at the cut point
temperature, Tcut. Care must be taken, when using
temperature coefficients, that the programmed voltage
does not exceed the maximum allowed VLCD voltage,
see Chapter 10.
Selectable temperature coefficients
1
For a particular liquid, the optimum VLCD can be calculated
for a given multiplex rate. For a Mux rate of 1 : 65, the
optimum operating voltage of the liquid can be calculated
as:
1 + 65
V LCD = --------------------------------------- × V th = 6.85 × V th
1
2 × 1 – ----------
65
VOP
7.13.1
where Vth is the threshold voltage of the liquid crystal
material used.
SET VOP VALUE
The voltage at the reference temperature can be
calculated as: [VLCD (T = Tcut)]
V LCD
= ( a + V OP × b )
( Tcut )
Table 6
(4)
Values for parameters of the HV generator
programming
SYMBOL
The operating voltage, VOP, can be set by software.
The generated voltage is dependent on the temperature,
programmed Temperature Coefficient (TC) and the
programmed voltage at the reference temperature (Tcut):
(5)
V LCD = ( a + V OP × b ) × ( 1 + ( ( T – T cut ) × TC ) )
a
b
Tcut
The values for Tcut, a and b are given in Table 6.
The maximum voltage that can be generated is dependent
on the voltage VDD2 and the display load current.
Two overlapping VOP ranges are selectable via the
command page “Hv-gen control”, see Fig.5.
1999 Aug 24
(6)
13
BITS
VALUE
UNIT
PRS = 0
4.5
V
PRS = 1
10.215
V
0.045
V
27
°C
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
handbook, full pagewidth
VLCD
b
a
00
01
02
03
04
05
06
. . . 5F
6F
7F
00
01
02
03
04
LOW
05
06
. . . 5F
6F
7F
HIGH
MGS472
VOP[6:0] programming (00H to 7FH, programming range LOW and HIGH).
Fig.5 VOP programming of PCF8535.
7.14
7.14.1
Voltage multiplier control
Table 7
S[1:0]
The PCF8535 incorporates a software configurable
voltage multiplier. After reset (RES) the voltage multiplier
is set to 2 × VDD2. Other voltage multiplier factors are set
via the HV-gen command page. Before switching on the
charge pump, the charge pump has to be pre-charged
using the following sequence.
A starting state of HVE = 0, DOF = 0, PD = 1 and DM = 0
is assumed. A small delay between steps is indicated.
The recommended wait period is 20 µs per 100 nF of
capacitance on VLCD1.
1. Set DM = 1 and PD = 0
2. Delay
3. Set the multiplication factor to 2 by setting S[1:0] = 00
4. Set the required VOP and PRS.
5. Set HVE = 1 to switch-on the charge pump with a
multiplication factor of 2
6. Delay
7. Increase the number of stages, one at a time, with a
delay between each until the required level is
achieved.
1999 Aug 24
14
HV generator multiplication factor
S[1]
S[0]
MULTIPLICATION FACTOR
0
0
2 × VDD2
0
1
3 × VDD2
1
0
4 × VDD2
1
1
5 × VDD2
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.15
PCF8535
The display RAM has a matrix of 65 × 133 bits.
The columns are addressed by a combination of the
X address pointer and the X-RAM page pointer, whilst the
rows addressed in groups of 8 by the Y address pointer.
The X address pointer has a range of 0 to 127 (7FH).
Its range can be extended by the X-RAM page pointer,
XM0. The Y address pointer has a range of 0 to 8 (08H).
The PCF8535 is limited to 133 columns by 65 rows,
addressing the RAM outside of this area is not allowed.
Addressing
Addressing of the RAM can be split into two parts; input
addressing and output addressing. Input addressing is
concerned with writing data into the RAM. Output
addressing is almost entirely automatic and taken care of
by the device, however, it is possible to affect the output
mode.
7.15.1
INPUT ADDRESSING
Data is down loaded byte wise into the RAM matrix of the
PCF8535 as indicated in Figs 6 to 10.
Table 8
Effect of X-RAM page pointer
X ADDRESS POINTER
X-RAM PAGE POINTER
XM0
ADDRESSED COLUMN
MX = 0
ADDRESSED COLUMN
MX = 1
0
0
C0
C132
1
0
C1
C131
2
0
C2
C130
:
:
:
:
125
0
C125
C7
126
0
C126
C6
127
0
C127
C5
0
1
C128
C4
1
1
C129
C3
:
:
:
:
4
1
C132
C0
Banks 1 to 7 use
the entire byte
MSB
handbook, full
pagewidth
XM0 = 0
XM0 = 1
0
1
LSB
2
4
MSB
5
6
7
icon data
.. ..
X address
Fig.6 RAM format, input addressing.
1999 Aug 24
15
.. ..
119
120
121
122
123
124
125
126
127
0
1
2
3
4
8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LSB
MGS673
Y address
3
Bank 8 is only
1 bit deep and
uses the MSB
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
MSB
PCF8535
bank 0
top of LCD
R0
Data byte in location
X = 0, Y = 0, MX0 = 0
(MX = 0, MY = 0)
LSB
bank 1
R8
bank 2
R16
LCD
bank 3
R24
MSB
bank 7
Data byte in location
Y = 7, X = 0, MX0 = 0
(MX = 0, MY = 0)
R56
LSB
bank 8
R64
MGS674
Fig.7 DDRAM to display mapping.
1999 Aug 24
16
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
Two automated addressing modes are available; vertical
addressing (V = 1) and horizontal addressing (V = 0).
These modes change the way in which the
auto-incrementing of the address pointers is handled and
are independent of multiplex rate. The auto-incrementing
works in a way so as to aid filling of the entire RAM. It is
not a prerequisite of operation that the entire RAM is filled;
in lower multiplex modes not all of the RAM will be needed.
For these multiplex rates, use of horizontal addressing
mode (V = 0) is recommended.
The addressing modes may be further modified by the
mirror X bit MX. This bit causes the data to be written into
the RAM from right to left instead of the normal left to right.
This effectively flips the display about the Y axis. The MX
bit affects the mode of writing into the RAM, changing the
MX bit after RAM data is written will not flip the display.
7.15.1.1
Vertical addressing: non-mirrored;
V = 1 and MX = 0
In the vertical addressing mode data is written top to
bottom and left to right. Here, the Y counter will
auto-increment from 0 to 7 and then wrap around to 0 (see
Fig.8). On each wrap over, the X counter will increment to
address the next column. When the X counter wraps over
from 127 to 0, the XM0 bit will be set. The last address
accessible is Y = 7, X = 4 and XM0 = 1; after this access
the counter will wrap around to Y = 0, X = 0 and XM0 = 0.
Addressing the icon row is a special case as these RAM
locations are not automatically accessed. These locations
must be explicitly addressed by setting the Y address
pointer to 8.
The Y address pointer does not auto-increment when the
X address over or underflows, it stays set to 8. Writing
icon data is independent of the vertical and horizontal
addressing mode, but is effected by the mirror X bit as
described in Sections 7.15.1.2 and 7.15.1.3.
handbook, full pagewidth
0
1
119
120
121
122
123
124
125
126
127
128
129
130
131
132
.. ..
.. ..
3
4
5
Y address
....
2
6
7
8
119
120
121
122
123
124
125
126
127
0
1
2
3
4
12
13
14
15
16
17
18
19
20
21
22
23
24
icon data
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0
1
2
byte order for
icon data
7
15
23
6
14
22
5
13
21
4
12
20
3
11
19
....
2
10
18
26
1
9
17
25
0
8
16
24
1015 1014 1013 1012 ....
1023 1022 1021 1020 1019 1018 1017 1016
1031 1030 1029 1028 1027 1026 1025 1024
.... 1035 1034 1033 1032
XM0 = 1
1063 1062 1061 1060
XM0 = 0
byte number
X address
MGS675
Fig.8 Sequence of writing data bytes into the RAM with normal vertical addressing (V = 1 and MX = 0).
1999 Aug 24
17
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.15.1.2
PCF8535
Vertical addressing: mirrored; V = 1 and MX = 1
It is also possible to write data from right to left, instead of from the normal left to right, still going top to bottom. In the
mirrored vertical addressing mode the Y counter will auto-increment from 0 to 7 and then wrap around to 0 (see Fig.9).
On each wrap-over, the X counter will decrement to address the preceding column. The XM0 bit will be automatically
toggled each time the X address counter wraps over from 0. The last address accessible is Y = 7, X = 0 and XM0 = 0;
after this access the counter will wrap around to Y = 0, X = 4 and XM0 = 1.
handbook, full pagewidth
8
0
9
1
10
2
3
....
4
5
....
5
6
44
36
45
37
46
38
30
47
39
31
4
6
7
.. ..
.. ..
8
119
120
121
122
123
124
125
126
127
0
1
2
3
4
13
12
11
10
9
8
7
6
5
4
3
2
1
0
120
119
118
117
116
115
114
113
112
111
110
109
108
3
7
49
41
33
2
43
35
1
....
0
50
42
34
48
40
32
1063 1062 1061 1060 1059 1058 1057 1056
1055 1054 1053 1052 ....
icon data
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
132
131
130
byte order for
icon data
XM0 = 1
Y address
XM0 = 0
byte number
X address
MGS676
Fig.9 Sequence of writing data bytes into the RAM with mirrored vertical addressing (V = 1 and MX = 1).
1999 Aug 24
18
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.15.1.3
PCF8535
Horizontal addressing: non-mirrored; V = 0 and MX = 0
In horizontal addressing mode data is written from left to right and top to bottom. Here, the X counter will auto-increment
from 0 to 127, set the XM0, then count 0 to 4 before wrapping around to 0 and clearing the XM0 bit (see Fig.10). On each
wrap-over, the Y counter will increment. The last address accessible is Y = 7, X = 4 and XM0 = 1; after this access the
counter will wrap around to Y = 0, X = 0 and XM0 = 0.
handbook, full pagewidth
XM0 = 1
....
133
134
135
136
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
119
120
121
122
123
124
125
126
127
128
129
130
131
132
XM0 = 0
byte number
0
1
2
4
7
119
120
121
122
123
124
125
126
127
128
129
130
131
132
.. ..
.. ..
8
119
120
121
122
123
124
125
126
127
0
1
2
3
4
12
13
14
15
16
17
18
19
20
21
22
23
24
icon data
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
0
1
2
byte order for
icon data
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
....
924
925
926
927
928
929
930
6
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
5
Y address
3
X address
MGS677
Fig.10 Sequence of writing data bytes into the RAM with normal horizontal addressing (V = 0 and MX = 0).
1999 Aug 24
19
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.15.1.4
PCF8535
Horizontal addressing: mirrored; V = 0 and MX = 1
It is also possible to write data from right to left, instead of from the normal left to right, still going top to bottom. In the
mirrored horizontal addressing mode the X counter will auto-decrement from 4 to 0, clear the XM0, then count 127 to 0
before wrapping around to 4 and setting the XM0 bit (see Fig.10). On each wrap-over, the Y counter will increment.
The last address accessible is Y = 7, X = 0 and XM0 = 0; after this access the counter will wrap around to Y = 0, X = 4
and XM0 = 1.
handbook, full pagewidth
1
....
0
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
XM0 = 1
13
12
11
10
9
8
7
6
5
4
3
2
1
0
XM0 = 0
byte number
2
4
....
6
944
943
942
941
940
939
938
937
936
935
934
933
932
931
.. ..
.. ..
7
8
119
120
121
122
123
124
125
126
127
0
1
2
3
4
13
12
11
10
9
8
7
6
5
4
3
2
1
0
120
119
118
117
116
115
114
113
112
111
110
109
108
icon data
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
132
131
130
byte order for
icon data
1063
1062
1061
1060
1059
1058
1057
1056
1055
1054
1053
1052
1051
1050
1049
1048
1047
1046
1045
1044
1043
1042
1041
1040
1039
930
929
928
927
926
925
924
5
Y address
3
X address
MGS678
Fig.11 Sequence of writing data bytes into the RAM with mirrored horizontal addressing (V = 0 and MX = 1).
1999 Aug 24
20
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.15.2
PCF8535
OUTPUT ADDRESSING
The output addressing of the RAM is done automatically in accordance with the currently selected multiplex rate.
Normally the user would not need to make any alterations to the addressing. There are, however, circumstances
pertaining to various connectivity of the device on a glass that would benefit from some in-built functionality. Three modes
exist that enable the user to modify the output addressing, namely:
1. MY, mirror the Y axis. This mode effectively flips the display about the X axis, resulting in an upside down display.
The effect is observable immediately the bit is modified. This is useful if the device is to be mounted above the display
area instead of below.
2. Bottom Row Swap (BRS). This mode swaps the order of the rows on the bottom(1) edge of the chip. This is useful to
aide routing to the display when it is not possible to pass tracks under the device; a typical example would be in tape
carrier package. This mode is often used in conjunction with TRS.
3. Top Row Swap (TRS). As with BRS, but swaps the order of rows on the top(1) edge of the chip.
7.15.2.1
Mirror Y, MY
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
As described above, the Y axis is mirrored in the X axis.
handbook, full pagewidth
..
R0
R1
R2
R3
R4
MY = 0
R5
R6
R7
Y axis
..
R8
R64
... icons ...
..
Mirror
Y axis
R55
R56
R57
R58
MY = 1
R59
R60
R61
R62
R63
R64
... icons ...
MGS679
Fig.12 Mirror Y behaviour (Mux rate 1 : 65).
(1) The top edge is defined as the edge containing the user interface connections. The bottom edge is the opposing edge.
1999 Aug 24
21
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.15.2.2
PCF8535
Bottom Row Swap
Here the order of the row pads is modified. Each block of rows is swapped about its local Y axis.
R16
handbook, full pagewidth
R32
R64
R48
INTERFACE
COLUMNS
R15
R0
R33
R47
MGS680
Fig.13 Bottom row swap.
7.15.2.3
Top Row Swap
Here the order of the row pads is modified. Each block of rows is swapped about its local Y axis.
R32
handbook, full pagewidth
R16
R48
R64
INTERFACE
COLUMNS
R0
R15
R47
R33
MGS681
Fig.14 Top row swap.
1999 Aug 24
22
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.15.2.4
PCF8535
Output row order
The order in which the rows are activated is a function of bits MY, TRS, BRS and the selected multiplex mode.
Tables 9 to 12 give the order in which the rows are activated. In all cases, the RAM is accessed in a linear fashion,
starting at zero with a jump to the last row for the icon data.
Table 9
Row order for BRS = 0 and TRS = 0
MULTIPLEX MODE
MY = 0
MY = 1
1 : 17
R0 to R15 and R64
R15 to R0 and R64
1 : 26
R0 to R24 and R64
R24 to R0 and R64
1 : 33
R0 to R31 and R64
R31 to R0 and R64
1 : 49
R0 to R47 and R64
R47 to R0 and R64
1 : 65
R0 to R64
R63 to R0 and R64
Table 10 Row order for BRS = 1 and TRS = 0
MULTIPLEX MODE
MY = 0
MY = 1
1 : 17
R15 to R0 and R64
R0 to R15 and R64
1 : 26
R15 to R0, R16 to R24 and R64
R24 to R16, R0 to R15 and R64
1 : 33
R15 to R0, R16 to R31 and R64
R31 to R16, R0 to R15 and R64
1 : 49
R15 to R0, R16 to R32, R47 to R33
and R64
R33 to R47, R32 to R16, R0 to R15
and R64
1 : 65
R15 to R0, R16 to R32, R47 to R33
and R48 to R64
R63 to R48, R33 to R47, R32 to R16,
R0 to R15 and R64
Table 11 Row order for BRS = 0 and TRS = 1
MULTIPLEX MODE
MY = 0
MY = 1
1 : 17
R0 to R15 and R48
R15 to R0 and R48
1 : 26
R0 to R15, R32 to R24 and R48
R24 to R32, R15 to R0 and R48
1 : 33
R0 to R15, R32 to R17 and R48
R17 to R32, R15 to R0 and R48
1 : 49
R0 to R15, R32 to R16, R33 to R47
and R48
R47 to R33, R16 to R32, R15 to R0
and R48
1 : 65
R0 to R15, R32 to R16, R33 to R47
and R64 to R48
R49 to R64, R47 to R33, R16 to R32,
R15 to R0 and R48
Table 12 Row order for BRS = 1 and TRS = 1
MULTIPLEX MODE
1999 Aug 24
MY = 0
MY = 1
1 : 17
R15 to R0 and R48
R0 to R15 and R48
1 : 26
R15 to R0, R32 to R24 and R48
R0 to R15, R32 to R24 and R48
1 : 33
R15 to R0, R32 to R17 and R48
R0 to R15, R17 to R32 and R48
1 : 49
R15 to R0, R32 to R16, R47 to R33
and R48
R0 to R15, R16 to R32, R33 to R47
and R48
1 : 65
R15 to R0, R32 to R16, R47 to R33
and R64 to R48
R0 to R15, R16 to R32, R33 to R47,
R47 to R64 and R48
23
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.16
PCF8535
• Oscillator off
Instruction set
• VLCDIN may be disconnected
Data accesses to the PCF8535 can be broken down into
two areas, those that define the operating mode of the
device and those that fill the display RAM; the distinction
being the D/C bit. When the D/C bit is at logic 0, the chip
will respond to instructions as defined in Table 16. When
the D/C bit is at logic 1, the chip will store data into the
RAM. Data may be written to the chip that is independent
to the presence of the display clock.
• I2C-bus interface accesses are possible
• RAM contents are not cleared; RAM data can be written
• Register settings remain unchanged.
V
There are 4 instruction types. Those which:
When V = 0, horizontal addressing is selected. When
V = 1, vertical addressing is selected. The behaviour is
described in Section 7.15.
1. Define PCF8535 functions such as display
configuration, etc.
7.16.2.3
2. Set internal RAM addresses
RAM page
The XM0 bit extends the RAM into a second page. The bit
may be considered to be the Most Significant Bit (MSB) of
an 8-bit X address. The behaviour is described in
Section 7.15.
3. Perform data transfer with internal RAM
4. Others.
In normal use, category 3 instructions are the most
frequently used. To lessen the MPU program load,
automatic incrementing by one of the internal RAM
address pointers after each data write is implemented.
7.16.2.4
Set Y address
The Y address is used as a pointer to the RAM for RAM
writing. The range is 0 to 8. Each bank corresponds to a
set of 8 rows, the only exception being bank 8, which
contains the icon data and is only 1-bit deep; see Table 13.
The instruction set is broken down into several pages,
each command page being individually addressed via the
H[2:0] bits.
Table 13 Y address pointer
7.16.1
RAM READ/WRITE COMMAND PAGE
This page is special in that it is accessible independently
of the H bits. This page is mainly used as a stepping stone
to other pages. Sending the ‘Default H[2:0]’ command will
cause an immediate step to the ‘Function and RAM
command page’ which will allow the H[2:0] bits to be set.
7.16.2
7.16.2.1
FUNCTION AND RAM COMMAND PAGE
Command page
Setting H[2:0] will move the user immediately to the
required command page. Pages not listed should not be
accessed as the behaviour is not defined.
7.16.2.2
Function set
PD
When PD = 1, the LCD driver is in power-down mode:
• All LCD outputs at VSS
1999 Aug 24
24
Y[3]
Y[2]
Y[1]
Y[0]
BANK
ROWS
0
0
0
0
bank 0
R0 to R7
0
0
0
1
bank 1
R8 to R15
0
0
1
0
bank 2
R16 to R23
0
0
1
1
bank 3
R24 to R31
0
1
0
0
bank 4
R32 to R39
0
1
0
1
bank 5
R40 to R47
0
1
1
0
bank 6
R48 to R55
0
1
1
1
bank 7
R56 to R63
1
0
0
0
bank 8
(icons)
R64
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.16.2.5
PCF8535
Set X address
7.16.3.3
The X address is used as a pointer to the RAM for RAM
writing. The range of X is 0 to 127 (7FH) and may be
extended by the XM0 bit. The combined value of XM0 and
X address directly corresponds to the display column
number when MX = 0 and corresponds to the inverse
display column number when MX = 1; see Table 14.
BS[2:0] sets the bias system; see Section 7.10.
7.16.3.4
Display size
Physically large displays require stronger drivers. Bit IB
enables the user to select a stronger driving mode and
should be used if suitable display quality can not be
achieved with the default setting.
Table 14 X address pointer
XM0, X[6:0]
Bias system
7.16.3.5
ADDRESSED
ADDRESSED
COLUMN, MX = 0 COLUMN, MX = 1
Multiplex rate
M[2:0] sets the multiplex rate; see Section 7.9.
0
C0
C132
1
C1
C131
7.16.4
2
C2
C130
7.16.4.1
3
C3
C129
PRS
:
:
:
129
C129
C3
130
C130
C2
131
C131
C1
Programmable charge pump range select. This bit defines
whether the programmed voltage for VOP is in the low or
the high range. The behaviour of this bit is further
described in Section 7.13.
132
C132
C0
HVE
7.16.3
7.16.3.1
HV-GEN COMMAND PAGE
HV-gen control
High voltage generator enable. When set to logic 0, the
charge pump is disabled. When set to logic 1, the charge
pump is enabled.
DISPLAY SETTING COMMAND PAGE
Display control
The D and E bits set the display mode as given in
Table 15.
7.16.4.2
Table 15 Display control
S[1:0] set the multiplication factor of the charge pump
ranging from times 2 to times 5. The behaviour of these
bits is further described in Section 7.14.
HV-gen stages
D
E
MODE
0
0
display blank
7.16.4.3
1
0
normal mode
0
1
all display segments on
1
1
inverse video
TC[2:0] set the required temperature coefficient.
The behaviour of these bits is further described in
Section 7.12.
7.16.3.2
7.16.4.4
External display control
Temperature measurement control
The SM bit is used to initiate a temperature measurement.
The SM bit is automatically cleared at the end of the
measurement. The behaviour of this bit is further
described in Section 7.11.
Mirror X and mirror Y have the effect of flipping the display
left to right or top to bottom respectively. MX works by
changing the order data that is written into the RAM.
As such, the effects of toggling MX will only be seen after
data is written into the RAM. MY works by reversing the
order that column data is accessed relative to the row
outputs. The effect of toggling MY will be seen
immediately. The behaviour of both of these bits is further
described in Section 7.15.
1999 Aug 24
Temperature coefficients
7.16.4.5
VLCD control
VOP[6:0] sets the required operating voltage for the
display.
25
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.16.5
7.16.5.1
PCF8535
When using an external clock and disabling it during
power-down mode will further reduce the standby current.
If it is not possible to disable it externally then it is worth
noting that by selecting the internal clock, which is disabled
during power-down mode, the same effect may be
achieved.
SPECIAL FEATURE COMMAND PAGE
State control
DM
Direct mode allows VLCDOUT to be sourced directly from
VDD2. This may be useful in systems where VDD is to be
used for VLCD.
7.16.5.3
DOF
The chip may be mounted on either a glass, foil or tape
carrier package. For these applications, different
organizations of the row pads are required to negate the
necessity of routing under the device. The TRS and BRS
allow for this swapping. The behaviour of both of these bits
is further described in Section 7.15.
Display off will turn off all internal analog circuitry that is not
required for temperature measurement.
As a consequence the display will be turned off. This
mode is only required if temperature measurements are
required whilst in power-down mode.
7.16.5.2
COG/TCP
Oscillator setting
The internal oscillator may be disabled and the source
clock for the display derived from the OSC pad. It is
important to remember that LCDs are damaged by DC
voltages and that the clock, whether derived internally or
externally, should never be disabled whilst the display is
active. The internal oscillator is switched off during
power-down mode.
7.16.6
INSTRUCTION SET
Table 16 Instruction set
INSTRUCTION
D/C
I2C-BUS COMMAND BYTE
R/W(1)
I2C-BUS COMMANDS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
H[2:0] = XXX; RAM read/write command page
Write data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
writes data to display RAM
Read status
0
1
D7
D6
D5
D4
D3
D2
D1
D0
returns result of
temperature measurement
NOP
0
0
0
0
0
0
0
0
0
0
no operation
Default H[2:0]
0
0
0
0
0
0
0
0
0
1
jump to H[2:0] = 111
H[2:0] = 111; function and RAM command page
Command page
0
0
0
0
0
0
1
H2
H1
H0
select command page
Function set
0
0
0
0
0
1
0
PD
V
0
power-down control, data
entry mode
RAM page
0
0
0
0
1
0
0
XM0
0
0
set RAM page for X address
Set Y address of
RAM
0
0
0
1
0
0
Y3
Y2
Y1
Y0
sets Y address of RAM
0≤Y≤8
Set X address of
RAM
0
0
1
X6
X5
X4
X3
X2
X1
X0
sets X address of RAM
0 ≤ X ≤ 127
1999 Aug 24
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Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
INSTRUCTION
D/C
PCF8535
I2C-BUS COMMAND BYTE
R/W(1)
I2C-BUS COMMANDS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
H[2:0] = 110; display setting command page
Display control
0
0
0
0
0
0
0
1
D
E
sets display mode
External display
control
0
0
0
0
0
0
1
MX
MY
0
mirror X, mirror Y
Bias system
0
0
0
0
0
1
0
BS2
BS1
BS0
set bias system
Display size
0
0
0
0
1
0
0
IB
0
0
set current for bias system
Multiplex rate
0
0
1
0
0
0
0
M2
M1
M0
set multiplex rate
H[2:0] = 101; HV-gen command page
HV-gen control
0
0
0
0
0
0
0
1
PRS HVE VLCD range, enable/disable
HV-gen
HV-gen stages
0
0
0
0
0
0
1
0
S1
S0
# of HV-gen voltage
multiplication
Temperature
coefficients
0
0
0
0
0
1
0
TC2
TC1
TC0
set temperature coefficient
Temperature
measurement
control
0
0
0
0
1
0
0
0
0
SM
start temperature
measurement
VLCD control
0
0
1
VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 set VLCD register
0 ≤ VLCD ≤ 127
H[2:0] = 011; special feature command page
State control
0
0
0
0
0
0
0
1
DOF DM
display off, direct mode
Oscillator setting
0
0
0
0
0
0
1
0
EC
0
enable/disable the internal
oscillator
COG/TCP
0
0
0
1
0
TRS BRS 0
0
0
top row swap, bottom row
swap
Note
1. R/W is set in the slave address.
1999 Aug 24
27
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
Table 17 Description of the symbols used in Table 16
BIT
0
1
PD
chip is active
chip is in power-down mode
V
horizontal addressing
vertical addressing
HVE
voltage multiplier disabled
voltage multiplier enabled
PRS
VLCD programming range LOW
VLCD programming range HIGH
SM
no measurement
start measurement
MX
no X mirror
mirror X
MY
no Y mirror
mirror Y
TRS
top row swap inactive
top row swap active
BRS
bottom row swap inactive
bottom row swap active
EC
internal oscillator enabled; OSC pad ignored
internal oscillator disabled; OSC pad enabled for
input
DM(1)
direct mode disabled
direct mode enabled
DOF(1)
display off mode disabled
display off mode enabled
IB
low current mode for smaller displays
high current mode for larger displays
Note
1. Conditional on other bits.
Table 18 Priority behaviour of bits PD, DOF, HVE and DM; note 1
PD
DOF
HVE
DM
MODE
1
X
X
X
0
1
X
X
all analog blocks except those required for temperature measurement are off
0
0
1
X
chip is active and using the internal VLCD generator
0
0
0
1
chip is active and using VDD as VLCD
0
0
0
0
chip is active and using an external VLCD generator attached to VLCDIN
chip is in power-down mode as defined under PD
Note
1. X = don’t care state.
1999 Aug 24
28
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.17
PCF8535
• Slave: the device addressed by a master
I2C-bus interface
7.17.1
• Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
7.17.1.1
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock
signals of two or more devices.
Bit transfer
7.17.1.4
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
Bit transfer is illustrated in Fig.15.
7.17.1.2
Each byte of 8 bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH signal put on the bus by
the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte. Also a master receiver must
generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a STOP
condition. Acknowledgement on the I2C-bus is illustrated
in Fig.18.
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P). The START
and STOP conditions are illustrated in Fig.16.
7.17.1.3
Acknowledge
System configuration
The system configuration is illustrated in Fig.17.
• Transmitter: the device which sends the data to the bus
• Receiver: the device which receives the data from the
bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig.15 Bit transfer.
1999 Aug 24
29
MBC621
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.16 Definition of START and STOP conditions.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.17 System configuration.
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.18 Acknowledgement on the I2C-bus.
1999 Aug 24
30
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
7.17.2
PCF8535
After the acknowledgement cycle of a write, a control byte
follows which defines the destination for the forthcoming
data byte and the mode for subsequent bytes. For a read,
the PCF8535 will immediately start to output the requested
data until a NOT acknowledge is transmitted by the
master. The sequence should be terminated by a STOP in
the event that no further access is required for the time
being, or by a RE-START, should further access be
required.
I2C-BUS PROTOCOL
The PCF8535 is a slave receiver/transmitter. If data is to
be read from the device the SDAOUT pad must be
connected, otherwise SDAOUT is unused.
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed. Four slave
addresses, 0111100, 0111101, 0111110 and 0111111 are
reserved for the PCF8535. The Least Significant Bits
(LSBs) of the slave address is set by connecting
SA1 and SA0 to either logic 0 (VSS) or logic 1 (VDD).
For ease of operation a continuation bit, Co, has been
included. This bit allows the user to set-up the chip
configuration and transmit RAM data in one access. A data
selection bit, D/C, defines the destination for data. These
bits are contained in the control byte. DB5 to DB0 should
be set to logic 0. These bits are reserved for future
expansion.
A sequence is initiated with a START condition (S) from
the I2C-bus master which is followed by the slave address.
All slaves with the corresponding address acknowledge in
parallel, all the others will ignore the I2C-bus transfer.
Table 19 Co and D/C definitions
BIT
Co
0/1
0
R/W
ACTION
n.a.
last control byte to be sent: only a stream of data bytes are allowed to follow; this stream may
only be terminated by a STOP or RE-START condition
1
D/C
another control byte will follow the data byte unless a STOP or RE-START condition is received
0
1
0
data byte will be decoded and used to set up the device
1
data byte will return the contents of the currently selected status register
0
data byte will be stored in the display RAM
1
no provision for RAM read back is provided
An example of a write access is given in Fig.19. Here, multiple instruction data is sent, followed by multiple display bytes.
An example of a read access is given in Fig.20.
handbook, full pagewidth
acknowledgement
from PCF8535
S S
S 0 1 1 1 1 A A 0 A 1 D/C
1 0
slave address
R/W
Co
acknowledgement
from PCF8535
control byte
A
acknowledgement
from PCF8535
data byte
2n ≥ 0 bytes
A 0 D/C
Co
acknowledgement
from PCF8535
control byte
1 byte
A
acknowledgement
from PCF8535
n ≥ 0 bytes
MSB . . . . . . . . . . . LSB
MGS682
Fig.19 Master transmits to slave receiver; write mode.
1999 Aug 24
31
A P
data byte
update
data pointer
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
acknowledgement
from PCF8535
handbook, full pagewidth
NOT acknowledgement
from master
S S
S 0 1 1 1 1 A A 1 A temp. read out value A P
1 0
slave address
STOP condition
R/W
MGS683
Fig.20 Master reads a slaves’ status register.
8 LIMITING VALUES (PROVISIONAL)
In accordance with the Absolute Maximum Rating System (IEC 134); notes 1, 2 and 3.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+7.0
V
IDD
supply current
−50
+50
mA
VLCD
LCD supply voltage
−0.5
+17.0
V
ILCD
LCD supply current
−50
+50
mA
ISS
negative supply current
−50
+50
mA
VI/VO
input/output voltage (any input/output)
−0.5
VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
Ptot
total power dissipation per package
−
300
mW
P/out
power dissipation per output
−
30
mW
Tamb
ambient temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Tj(max)
maximum junction temperature
−
150
°C
Notes
1. Stresses above these values listed may cause permanent damage to the device.
2. Parameters are valid over the operating temperature range unless otherwise specified. All voltages are referenced
to VSS unless otherwise specified.
3. VSS = 0 V.
9
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
recommended to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1999 Aug 24
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Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
10 DC CHARACTERISTICS
VDD = 4.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 16.0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VLCDIN
ILCDIN
LCD supply voltage
LCD supply current
VLCDOUT
generated supply voltage
VDD1,
VDD2,
VDD3
supply voltage
IDD
supply current
Mux mode 1 : 65
8.0
−
16.0
V
Mux mode 1 : 49
8.0
−
16.0
V
Mux mode 1 : 34
−
−
16.0
V
Mux mode 1 : 26
−
−
16.0
V
Mux mode 1 : 17
−
−
16.0
V
normal mode; notes 1 and 2
−
40
90
µA
normal mode; notes 1 and 4
−
18
40
µA
LCD voltage generator
enabled
−
−
16.0
V
4.5
−
5.5
V
power-down mode;
notes 1, 3 and 5
−
2
10
µA
display off mode;
notes 1 and 5
−
−
−
µA
normal mode; notes 1 and 6
−
160
350
µA
normal mode; notes 1 and 2
−
40
90
µA
−
0.3VDD V
Logic
VIL
LOW-level input voltage
VSS
VIH
HIGH-level input voltage
0.7VDD −
IOL
LOW-level output current (SDA)
VOL = 0.4 V; VDD = 5 V
3.0
IL
leakage current
VI = VDD or VSS
VDD
V
−
−
mA
−1
−
+1
µA
Column and row outputs
Ro(col)
column output resistance C0 to C132 VLCD = 12 V; note 7
−
−
10
kΩ
Ro(row)
row output resistance R0 to R33
−
−
3.0
kΩ
Vbias(col)
bias tolerance C0 to C132
−100
0
+100
mV
Vbias(row)
bias tolerance R0 to R64
−100
0
+100
mV
−
27
−
°C
VLCD = 12 V; note 7
Temperature coefficient
tcut
cut point temperature
Tamb = −20 to +70 °C
Notes
1. LCD outputs are open-circuit, inputs at VDD or VSS, bus inactive, fOSC = typical internal oscillator frequency.
2. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = 12.0 V and external VLCD.
3. Power-down mode. During power-down all static currents are switched off.
4. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = VDD2 and external VLCD.
5. Internal VLCD generation or external VLCD.
6. Conditions are: VDD1 to VDD3 = 5.0 V, VLCD = 12.0 V and voltage multiplier = 3VDD.
7. ILCD = 10 µA. Outputs tested one at a time.
1999 Aug 24
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Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
11 AC CHARACTERISTICS
VDD = 4.5 to 5.5 V; VSS = 0 V; VLCD = 4.5 to 16.0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
ffr(LCD)
LCD frame frequency (internal clock)
fclk(ext)
external clock frequency
tW(RESL)
reset LOW pulse width
tW(RESH)
reset HIGH pulse width
tSU;RESL
reset LOW pulse set-up time after power-on
tR(op)
end of reset pulse to interface being operational
see Table 20
notes 1 and 2
MIN.
TYP.
MAX.
UNIT
48
80
165
Hz
120
−
410
kHz
1
−
−
µs
5
−
−
µs
−
−
30
µs
−
−
3
µs
Serial-bus interface; note 3
fSCL
SCL clock frequency
0
−
400
kHz
tLOW
SCL clock LOW period
1.3
−
−
µs
tHIGH
SCL clock HIGH period
0.6
−
−
µs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
0.9
µs
tr
SCL, SDA rise time
note 4
20 + 0.1Cb −
300
ns
tf
SCL, SDA fall time
note 4
20 + 0.1Cb −
300
ns
Cb
capacitive load represented by each bus line
−
−
400
pF
tSU;STA
set-up time for a repeated START condition
0.6
−
−
µs
tHD;STA
START condition hold time
0.6
−
−
µs
tSU;STO
set-up time for STOP condition
0.6
−
−
µs
tSP
tolerable spike width on bus
−
−
50
ns
tBUF
bus free time between a STOP and START
condition
1.3
−
−
µs
Notes
1. VDD1 to VDD3 = 5 V.
2. Decoupling capacitor VLCD and VSS = 100 nF (higher capacitor size increases tSU;RESL and higher VDD1 to VDD3
reduces tSU;RESL).
3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
4. Cb = total capacitance of one bus line in pF.
1999 Aug 24
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Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
handbook, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
t SU;STA
MGA728
t SU;STO
Fig.21 I2C-bus timing diagram.
Table 20 External clock frequency
MUX MODE
DIVISION RATIO
EXTERNAL CLOCK FREQUENCY FOR AN 80 Hz FRAME
FREQUENCY (DIVISION RATIO × 80 Hz)
1 : 65
3168
253 kHz
1 : 48
3136
251 kHz
1 : 33
2720
218 kHz
1 : 26
2592
207 kHz
1 : 17
2592
207 kHz
1999 Aug 24
35
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
12 RESET TIMING
handbook, full pagewidth
VDD
t W(RESL)
t W(RESH)
t W(RESL)
RES
VDD
t SU;RESL
t W(RESL)
t W(RESH)
t W(RESL)
RES
RES
t R(op)
SDA,
SCL
MGS684
Fig.22 Reset timing.
1999 Aug 24
36
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
13 APPLICATION INFORMATION
Table 21 Programming example for PCF8535
STEP
DISPLAY(1)
SERIAL BUS BYTE
1
START condition
2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
1
1
1
1
SA1 SA0 0
slave address, R/W = 0
3
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
0
0
0
0
0
control byte, Co = 0, D/C = 0
4
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
0
0
0
0
1
H[2:0] independent command;
select function and RAM command
page H[1:0] = 111
5
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
1
0
0
0
0
function and RAM command page;
PD = 0, V = 0
6
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
0
1
1
1
0
function and RAM command page;
select display setting command
page H[1:0] = 110
7
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
1
0
0
1
0
display setting command page; set
bias system to 1/9BS[2:0] = 010
8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
0
0
1
1
0
display setting command page; set
normal mode (D = 1, E = 0)
9
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
1
0
0
0
0
1
0
0
select Mux rate 1 : 65
10
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
0
0
0
0
1
H[2:0] independent command;
select function and RAM command
page H[1:0] = 111
11
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
0
1
1
0
1
function and RAM command page;
select Hv-gen command page
H[1:0] = 101
12
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
0
1
0
0
1
Hv-gen command page; select
voltage multiplication factor 3
S[1:0] = 01
13
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
1
0
0
1
0
Hv-gen command page; select
temperature coefficient 2
TC[2:0] = 010
14
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
1
0
1
0
1
0
0
0
Hv-gen command page; set
VLCD = 12.02 V;
VOP[6:0] = 0101000
15
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
0
0
0
0
1
1
1
Hv-gen command page; select high
VLCD programming range
(PRS = 1), voltage multiplier on
(HVE = 1)
16
START condition
repeat start
17
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
1
1
1
1
SA1 SA0 0
slave address, R/W = 0
18
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BLANK
0
1
0
0
0
0
0
0
control byte, Co = 0, D/C = 1
1999 Aug 24
BLANK
OPERATION
BLANK
37
start
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
STEP
19
PCF8535
DISPLAY(1)
SERIAL BUS BYTE
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
1
1
OPERATION
data write; Y, X are initialized to
logic 0 by default, so they are not
set here
MGS405
20
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
0
1
data write
MGS406
21
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
1
1
data write
MGS407
22
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
data write
MGS408
23
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
1
1
data write
MGS409
24
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
0
0
data write
MGS410
25
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
1
1
data write, last data, stop
transmission
MGS411
26
START condition
repeat start
27
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
1
1
1
SA1 SA0 0
slave address, R/W = 0
MGS411
1999 Aug 24
38
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
STEP
28
PCF8535
DISPLAY(1)
SERIAL BUS BYTE
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
OPERATION
control byte, Co = 1, D/C = 0
MGS411
29
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
H[1:0] independent command;
select function and RAM command
page H[1:0] = 111
MGS411
30
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
control byte, Co = 1, D/C = 0
MGS411
31
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
1
0
function and RAM command page;
select display setting command
page H[1:0] = 110
MGS411
32
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
control byte, Co = 1, D/C = 0
MGS411
33
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
1
0
1
display control; set inverse video
mode (D = 1, E = 1)
MGS412
34
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
control byte, Co = 1, D/C = 0
MGS412
35
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
0
0
0
0
0
set X address of RAM; set address
to ‘0000000’
MGS412
1999 Aug 24
39
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
STEP
36
PCF8535
DISPLAY(1)
SERIAL BUS BYTE
OPERATION
control byte, Co = 0, D/C = 1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
0
0
0
0
MGS412
37
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
data write
MGS414
38
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
data write
MGS685
39
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
data write
MGS686
40
STOP condition
end of transfer
Note
1. Assumes the display RAM was previously empty.
The pinning of the PCF8535 is optimized for single plane wiring e.g. for chip-on-glass display modules.
Display size: 65 × 133 pixels.
1999 Aug 24
40
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
handbook, full pagewidth
DISPLAY 65 × 133 PIXELS
33
133
32
PCF8535
R I/O
Rsupply
Rcommon
Cext
3
VSS1,
I/O
VDD1
to
VDD3
VSS2
VLCD
MGS687
Fig.23 Application diagram (COG).
The required minimum value for the external capacitors in an application with the PCF8535 are:
Cext for VLCD, VSS1 and VSS2 = 100 nF (min.) (recommended 470 nF to 1 µF); Cext for VDD1 to VDD3, VSS1 and
VSS2 = 470 nF (recommended capacitor larger than the capacitor for VLCD, VSS1 and VSS2).
Higher capacitor values are recommended for ripple reduction.
For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections.
Maximum values for supply tracks (Rsupply) are 120 Ω. Maximum values for the common resistance to the source,
(Rcommon) are 120 Ω. Higher track resistance reduces performance and increases current consumption.
Three I/O lines are required for the COG module; SDA, SCL and RES (optional). Other signals may be fixed on the
module to appropriate levels. RI/O should also be minimized. In particular, if the I2C-bus acknowledge or temperature
read back is required, the RI/O for the SDA line must be carefully considered in conjunction with the value of the external
pull-up resistor.
1999 Aug 24
41
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
14 BONDING PAD LOCATIONS
SYMBOL
Table 22 Bonding pad locations
All x and y coordinates are referenced to the centre of the
chip (dimensions in µm; see Fig.27).
SYMBOL
x
y
1
−1050
−6156
bump/align 1 2
+1050
−6081
R0
3
+1050
−5985
R1
4
+1050
−5915
R2
5
+1050
−5845
R3
6
+1050
−5775
R4
7
+1050
−5705
R5
8
+1050
−5635
R6
9
+1050
−5565
R7
10
+1050
−5495
R8
11
+1050
−5425
R9
12
+1050
−5355
R10
13
+1050
−5285
R11
14
+1050
−5215
R12
15
+1050
−5145
R13
16
+1050
−5075
R14
17
+1050
−5005
R15
18
+1050
−4935
C0
19
+1050
−4725
C1
20
+1050
−4655
C2
21
+1050
−4585
C3
22
+1050
−4515
C4
23
+1050
−4445
C5
24
+1050
−4305
C6
25
+1050
−4235
C7
26
+1050
−4165
C8
27
+1050
−4095
C9
28
+1050
−4025
C10
29
+1050
−3955
C11
30
+1050
−3885
C12
31
+1050
−3815
C13
32
+1050
−3745
C14
33
+1050
−3675
C15
34
+1050
−3605
C16
35
+1050
−3535
C17
36
+1050
−3465
C18
37
+1050
−3395
dummy
1999 Aug 24
PAD
42
PAD
x
y
C19
38
+1050
−3325
C20
39
+1050
−3255
C21
40
+1050
−3185
C22
41
+1050
−3115
C23
42
+1050
−3045
C24
43
+1050
−2975
C25
44
+1050
−2905
C26
45
+1050
−2835
C27
46
+1050
−2765
C28
47
+1050
−2695
C29
48
+1050
−2625
C30
49
+1050
−2555
C31
50
+1050
−2485
C32
51
+1050
−2415
C33
52
+1050
−2345
C34
53
+1050
−2275
C35
54
+1050
−2205
C36
55
+1050
−2135
C37
56
+1050
−1995
C38
57
+1050
−1925
C39
58
+1050
−1855
C40
59
+1050
−1785
C41
60
+1050
−1715
C42
61
+1050
−1645
C43
62
+1050
−1575
C44
63
+1050
−1505
C45
64
+1050
−1435
C46
65
+1050
−1365
C47
66
+1050
−1295
C48
67
+1050
−1225
C49
68
+1050
−1155
C50
69
+1050
−1085
C51
70
+1050
−1015
C52
71
+1050
−945
C53
72
+1050
−875
C54
73
+1050
−805
C55
74
+1050
−735
C56
75
+1050
−665
C57
76
+1050
−595
C58
77
+1050
−525
C59
78
+1050
−455
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
SYMBOL
PAD
PCF8535
x
y
SYMBOL
PAD
x
y
C60
79
+1050
−385
C101
120
+1050
+2625
C61
80
+1050
−315
C102
121
+1050
+2695
C62
81
+1050
−245
C103
122
+1050
+2765
C63
82
+1050
−175
C104
123
+1050
+2835
C64
83
+1050
−105
C105
124
+1050
+2905
C65
84
+1050
−35
C106
125
+1050
+2975
C66
85
+1050
+35
C107
126
+1050
+3045
C67
86
+1050
+105
C108
127
+1050
+3115
C68
87
+1050
+175
C109
128
+1050
+3185
C69
88
+1050
+315
C110
129
+1050
+3255
C70
89
+1050
+385
C111
130
+1050
+3325
C71
90
+1050
+455
C112
131
+1050
+3395
C72
91
+1050
+525
C113
132
+1050
+3465
C73
92
+1050
+595
C114
133
+1050
+3535
C74
93
+1050
+665
C115
134
+1050
+3605
C75
94
+1050
+735
C116
135
+1050
+3675
C76
95
+1050
+805
C117
136
+1050
+3745
C77
96
+1050
+875
C118
137
+1050
+3815
C78
97
+1050
+945
C119
138
+1050
+3885
C79
98
+1050
+1015
C120
139
+1050
+3955
C80
99
+1050
+1085
C121
140
+1050
+4025
C81
100
+1050
+1155
C122
141
+1050
+4095
C82
101
+1050
+1225
C123
142
+1050
+4165
C83
102
+1050
+1295
C124
143
+1050
+4235
C84
103
+1050
+1365
C125
144
+1050
+4305
C85
104
+1050
+1435
C126
145
+1050
+4375
C86
105
+1050
+1505
C127
146
+1050
+4445
C87
106
+1050
+1575
C128
147
+1050
+4515
C88
107
+1050
+1645
C129
148
+1050
+4585
C89
108
+1050
+1715
C130
149
+1050
+4655
C90
109
+1050
+1785
C131
150
+1050
+4725
C91
110
+1050
+1855
C132
151
+1050
+4795
C92
111
+1050
+1925
R47
152
+1050
+5005
C93
112
+1050
+1995
R46
153
+1050
+5075
C94
113
+1050
+2065
R45
154
+1050
+5145
C95
114
+1050
+2135
R44
155
+1050
+5215
C96
115
+1050
+2205
R43
156
+1050
+5285
C97
116
+1050
+2275
R42
157
+1050
+5355
C98
117
+1050
+2345
R41
158
+1050
+5425
C99
118
+1050
+2415
R40
159
+1050
+5495
C100
119
+1050
+2485
R39
160
+1050
+5565
1999 Aug 24
43
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
SYMBOL
PAD
PCF8535
x
y
SYMBOL
PAD
x
y
R38
161
+1050
+5635
VLCDOUT
202
−1050
+2034
R37
162
+1050
+5705
VLCDOUT
203
−1050
+1964
R36
163
+1050
+5775
VLCDSENCE
204
−1050
+1894
R35
164
+1050
+5845
dummy
205
−1050
+1544
R34
165
+1050
+5915
dummy
206
−1050
+1264
R33
166
+1050
+5985
RES
207
−1050
+914
bump/align 2 167
+1050
+6081
T3
208
−1050
+704
dummy
168
−1050
+6094
T2
209
−1050
+494
R48
169
−1050
+5954
T1
210
−1050
+284
R49
170
−1050
+5884
VDD2
211
−1050
+144
R50
171
−1050
+5814
VDD2
212
−1050
+74
R51
172
−1050
+5744
VDD2
213
−1050
+4
R52
173
−1050
+5674
VDD2
214
−1050
−66
R53
174
−1050
+5604
VDD2
215
−1050
−136
R54
175
−1050
+5534
VDD2
216
−1050
−206
R55
176
−1050
+5464
VDD2
217
−1050
−276
R56
177
−1050
+5394
VDD2
218
−1050
−346
R57
178
−1050
+5324
VDD3
219
−1050
−416
R58
179
−1050
+5254
VDD3
220
−1050
−486
R59
180
−1050
+5184
VDD3
221
−1050
−556
R60
181
−1050
+5114
VDD3
222
−1050
−626
R61
182
−1050
+5044
VDD1
223
−1050
−696
R62
183
−1050
+4974
VDD1
224
−1050
−766
R63
184
−1050
+4904
VDD1
225
−1050
−836
R64
185
−1050
+4834
VDD1
226
−1050
−906
bump/align 3 186
−1050
+4414
VDD1
227
−1050
−976
dummy
187
−1050
+4274
VDD1
228
−1050
−1046
dummy
188
−1050
+3996
dummy
229
−1050
−1186
dummy
189
−1050
+3574
SDA
230
−1050
−1466
OSC
190
−1050
+3154
SDA
231
−1050
−1536
VLCDIN
191
−1050
+2874
SDAOUT
232
−1050
−1886
VLCDIN
192
−1050
+2804
SA1
233
−1050
−2166
VLCDIN
193
−1050
+2734
SA0
234
−1050
−2376
VLCDIN
194
−1050
+2664
VSS2
235
−1050
−2586
VLCDIN
195
−1050
+2594
VSS2
236
−1050
−2656
VLCDIN
196
−1050
+2524
VSS2
237
−1050
−2726
VLCDOUT
197
−1050
+2384
VSS2
238
−1050
−2796
VLCDOUT
198
−1050
+2314
VSS2
239
−1050
−2866
VLCDOUT
199
−1050
+2244
VSS2
240
−1050
−2936
VLCDOUT
200
−1050
+2174
VSS2
241
−1050
−3006
VLCDOUT
201
−1050
+2104
VSS2
242
−1050
−3076
1999 Aug 24
44
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
SYMBOL
PAD
PCF8535
x
y
Table 23 Alignment marks
MARKS
x
y
VSS1
243
−1050
−3146
VSS1
244
−1050
−3216
Alignment mark 1
−1045
−4720
VSS1
245
−1050
−3286
Alignment mark 2
−1045
+4620
VSS1
246
−1050
−3356
Alignment mark 3
+1045
+6196
VSS1
247
−1050
−3426
Alignment mark 4
+1045
−6196
VSS1
248
−1050
−3496
−6081
VSS1
249
−1050
−3566
Dummy bump/alignment +1050
mark 1
VSS1
250
−1050
−3636
+6081
T5
251
−1050
−3846
Dummy bump/alignment +1050
mark 2
T4
252
−1050
−4056
+4414
dummy
253
−1050
−4126
Dummy bump/alignment −1050
mark 3
254
−1050
−4406
Dummy bump/alignment −1050
mark 4
−4605
SCL
SCL
255
−1050
−4476
Bottom left
−1180
−6330
bump/align 4 256
−1050
−4605
Top right
+1180
+6330
R32
257
−1050
−4826
R31
258
−1050
−4896
R30
259
−1050
−4966
R29
260
−1050
−5036
Pad pitch
minimum 70
µm
R28
261
−1050
−5106
Pad size; Al
62 × 100
µm
R27
262
−1050
−5176
CBB opening
36 × 76
µm
R26
263
−1050
−5246
Bump dimensions
50 × 90 × 17.5 (± 5)
µm
R25
264
−1050
−5316
µm
265
−1050
−5386
Wafer thickness
(including bumps)
maximum 381
R24
R23
266
−1050
−5456
R22
267
−1050
−5526
R21
268
−1050
−5596
R20
269
−1050
−5666
R19
270
−1050
−5736
R18
271
−1050
−5806
R17
272
−1050
−5876
R16
273
−1050
−5946
1999 Aug 24
Table 24 Bonding pads
PAD
45
SIZE
UNIT
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
handbook, halfpage
handbook, halfpage
100
µm
y centre
x centre
x centre
MGS689
MGS688
Fig.24 Shape of alignment mark.
handbook, halfpage
12.66 mm
2.36
mm
PCF8535
Fig.25 Shape of dummy bump/alignment mark.
pitch
MGS690
Fig.26 Bonding pads.
1999 Aug 24
80
µm
y centre
46
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
handbook, full pagewidth
R33
.
R48
.
..
..
..
.
..
.
R47
C132
.
R64
VLCDIN
PC8535
OSC
..
VLCDOUT
VLCDSENSE
RES
T3
T2
T1
y
VDD2
VDD3
0, 0
x
VDD1
SDA
SDAOUT
SA1
SA0
VSS2
VSS1
T5
T4
..
.
SCL
R32
.
C0
R15
.
..
.
..
.
..
..
R16
PAD ONE
R0
Dummy bump
Alignment mark
MGS693
The position of the bonding pads is not to scale.
Fig.27 Bonding pad location (viewed from bump side).
1999 Aug 24
47
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
15 DEVICE PROTECTION DIAGRAM
handbook, full pagewidth
PADS 223 to 228
PADS 219 to 222
PADS 211 to 218
VDD2
VDD1
VDD3
PADS 243 to 250
VSS1
VSS1
VSS1
PADS 235 to 242
VSS2
PADS
PADS 197 to 203
VSS2
VLCDOUT
PADS 191 to 196, 204
VLCDIN,
VLCDSENSE
VSS1
VSS1
VSS1
VDD1
VLCDIN
PADS 254, 255, 230 to 232
PADS 3 to 166, 169 to 185,
257 to 273
SCL, SDA, SDAOUT
VSS1
VSS1
VDD1
VDD1
PADS 190, 233, 234, 252, 251, 207
PADS 208 to 210
T1, T2, T3
OSC, SA0, SA1, T4, T5, RES
VSS1
MGS672
Fig.28 Device diode protection diagram.
1999 Aug 24
48
VSS1
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
16 TRAY INFORMATION
x
handbook, full pagewidth
A
C
y
D
B
F
E
MGS691
The dimensions are given in Table 25.
Fig.29 Tray details.
Table 25 Dimensions
DIM.
handbook, halfpage
PC8535-1
MGS692
The orientation of the IC in a pocket is indicated by the
position of the IC type name on the die surface with
respect to the chamfer on the upper left corner of the tray.
Refer to the bonding pad location diagram for the
orientating and position of the type name on the die
surface.
Fig.30 Tray alignment.
1999 Aug 24
49
DESCRIPTION
VALUE
A
pocket pitch in x direction
14.88 mm
B
pocket pitch in y direction
4.06 mm
C
pocket width in x direction
12.76 mm
D
pocket width in y direction
2.46 mm
E
tray width in x direction
50.8 mm
F
tray width in y direction
50.8 mm
x
number of pockets in x direction
3
y
number of pockets in y direction
11
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
17 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
18 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
20 BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of
ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately
indicated in the data sheet. There is no post waffle pack testing performed on individual die. Although the most modern
processes are utilized for wafer sawing and die pick and place into waffle pack carriers, Philips Semiconductors has no
control of third party procedures in the handling, packing or assembly of the die. Accordingly, Philips Semiconductors
assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of
the die. It is the responsibility of the customer to test and qualify their application in which the die is used.
1999 Aug 24
50
Philips Semiconductors
Objective specification
65 × 133 pixel matrix driver
PCF8535
NOTES
1999 Aug 24
51
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SCA 67
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465006/01/pp52
Date of release: 1999
Aug 24
Document order number:
9397 750 06201