T6A04A TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic T6A04A Column and Row Driver LSI for a Dot Matrix Graphic LCD The T6A04A is a driver for a small-to-medium-sized scale dot matrix graphic LCD. It includes the functions of the T9841B (column driver) and the T9842B (row driver). It has an 8-bit interface circuit and can be operated with an 80-Series MPU. It generates all the timing signals for the display with an on-chip oscillator. It receives 8-bit data from an MPU, latches the data to an on-chip RAM, and displays the image on the LCD (the data in the display RAM correspond to the dots on the display). The device has 120 column driver outputs and 64 row driver outputs enabling it to drive a 120-dot by 64-dot LCD. In addition, there are resistors to divide the bias voltage, a power supply op-amp, DC-DC converter (+5 V →−5 V) and contrast control circuit, enabling the LCD to be driven by a single power supply. The device can be connected to another T6A04A to drive a 240-dot by 64-dot LCD. Unit: mm T6A04A Lead Pitch IN OUT (UAW, 6NS) 1.0 0.28 (UEM, 7NS) 0.4 0.4 Please contact Toshiba or an authorized Toshiba dealer for information on package dimensions. TCP (Tape Carrier Package) Features · On-chip display RAM capacity · Display RAM data : 120 × 64 = 7.5 kbits (1) Display data = 1.................. LCD turns on. (2) Display data = 0.................. LCD turns off. · 1/64 duty cycle · Word length of display data can be switched between eight bits and six bits according to the character font. · LCD driver outputs · Interface with 80-series MPU · On-chip oscillator with one external resistor · Low power consumption · On-chip resistors to divide bias voltage, on-chip operational amplifier for LCD supply, on-chip DC-DC converter, on-chip contrast control circuit · CMOS process · Operating voltage · Operating voltage for LCD drive signal : VDD − VEE = 16.0 V (max) · Package : 120 column driver outputs and 64 row driver outputs : 4.5 to 5.5 V : TCP (tape carrier package) 1 2002-03-06 VOUT VIN VEE R2 R1 VLC1 VLC2 VLC3 VLC4 VLC5 FS1 FS2 M/S 3 C1 C2 DC-DC CONVERTER CONTRAST CONTROL CIRCUIT RESISTOR LADDERS OP-AMP (´5) 2 3 PM CL FRM 5 2 120 LATCH 8 4 X･Y COUNTER SELECT REGISTER CONTRAST CONTROL REGISTER /CE DB0 to DB7 8 Z-ADDRESS REGISTER T6A04A 2002-03-06 WORD LENGTH CONVERTER REGISTER INPUT REGISTER COUNTER UP/DOWN REGISTER INPUT/OUTPUT BUFFER 8 OUTPUT REGISTER BIT TRANSFER CIRCUIT DISPLAY ON/OFF REGISTER OP-AMP CONTROL REGISTER Y-ADDRESS COUNTER/DECODER INPUT/OUTPUT GATE 120 ´ 64 = 7.5 kbits DISPLAY RAM I/F CONTROL CIRCUIT 4 8 SEG120 LCD DRIVE CIRCUIT (120) SEG1 M /STB EXP /RST D/I /WR Z-COUNTER X-COUNTER MPX OUTPUT BUFFER INPUT/OUTPUT BUFFER COMD SCLK OSC1 OSC2 /f INPUT/OUTPUT BUFFER OSCILLATOR CIRCUIT GENERATION TIMING 32-bit SHIFT REGISTER MPX COM64 32-bit SHIFT REGISTER COM33 LCD DRIVE CIRCUIT (32) COM32 LCD DRIVE CIRCUIT (32) COM1 Block Diagram DECODER T6A04A Pin Assignment COM32 COM1 SEG1 T6A04A (top view) SEG120 COM33 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 /RST /CE /WR D/I EXP M/S OSC2 OSC1 FS2 FS1 VDD /f PM fB fA Pf FRM M CL COMB VSS /STB VOUT C2 C1 VIN R2 R1 VEE VLC1 VLC2 VLC3 VLC4 VLC5 COM64 Note 1: The above diagram shows the pin configuration of the LSI chip; it does not show the configuration of the tape carrier package. 3 2002-03-06 T6A04A Pin Functions Pin Name I/O SEG1 to SEG120 Output Functions Column driver output Row driver output COM1 to COM64 Output ● Disable expansion mode (EXP = L, M/S = H) ® COM1 to COM64 are enabled. ● Enable expansion mode/master mode (EXP = H, M/S = H) ® COM1 to COM32 are enabled and COM33 to COM64 are disabled. ● Enable expansion mode/slave mode (EXP = H, M/S = L) ® COM1 to COM32 are disabled and COM33 to COM64 are enabled. Input/output for shift clock pulse CL I/O ● Master mode (M/S = H) ® Output ● Slave mode (M/S = L) ® Input Input/output for frame signal M I/O ● Master mode (M/S = H) ® Output ● Slave mode (M/S = L) ® Input Input/output for display synchronous signal FRM I/O ● Master mode (M/S = H) ® Output ● Slave mode (M/S = L) ® Input Input/output system clock signal Pf, fA, fB I/O ● Master mode (M/S = H) ® Output ● Slave mode (M/S = L) ® Input Input/output row signal data COMD I/O DB0 to DB7 I/O D/I Input ● Master mode (M/S = H) ® Output ● Slave mode (M/S = L) ® Input Data bus Input for data/instruction select signal ● D/I = H ® indicates that the data on DB0 to DB7 is display data. ● D/I = L ® indicates that the data on DB0 to DB7 is control data. Input for write select signal /WR Input ● /WR = H ® Read selected ● /WR = L ® Write selected Input for chip enable signal /CE /RST Input Input ● /WR = L ® Data on DB0 to DB7 is latched on the rising edge of /CE. ● /WR = H ® Data appears at DB0 to DB7 while /CE is Low. Input for reset signal ● /RST = L ® Reset state Input for standby signal /STB FS1, FS2 Input Input ● Usually connected to VDD ● /STB = L ® T6A04A is in standby state and cannot accept any commands or data. Column driver signal and row driver signal are at the VDD level Input for frequency selection Input for expansion mode selection EXP Input ● M/S = H ® enables expansion mode. Two chips can be used together. ● M/S = L ® disables expansion mode. 4 2002-03-06 T6A04A Pin Name I/O M/S Input Functions Input for master/slave selection OSC1, OSC2 ¾ ● M/S = H ® T6A04A is master chip. ● M/S = L ® T6A04A is slave chip. When using the internal clock oscillator, connect a resistor between OSC1 and OSC2. When using an external clock, connect the clock as input to OSC1 and leave OSC2 open. Input for LCD drive bias selection ● R1, R2 LCD drive bias selection is shown in the following table ¾ C1, C2 ¾ Connected by a capacitor for DC-DC converter VIN ¾ Input for DC-DC converter. Connect to VDD. VOUT ¾ DC-DC converter output VEE ¾ R2 R1 Bias 0 0 1/6 0 1 1/7 1 0 1/8 1 1 1/9 Power supply for LCD driver circuit ● When using on-chip DC-DC converter, connect VEE to VOUT Power supply for LCD driver circuit VLC1 to VLC5 ¾ ● M/S = H ® bias voltage output VDD ¾ ● Power supply for logic circuit M/S = L ® bias voltage input VSS ¾ Ground: Reference PM ¾ Pre-frame signal for Toshiba T9841B /f ¾ Output system clock for Toshiba T9841B 5 2002-03-06 T6A04A Function of Each Block · Interface logic The T6A04A can be operated with an 80-Series MPU. Figure 1 shows an example of the interface. D/1 /CE /WR <T6A04A> DB0 to DB7 /RST A0 /IORQ /WR <MPU> D0 to D7 /RESET Figure 1 · Input register This register stores 8-bit data from the MPU. The D/I signal distinguishes between command data and display data. · Output register This register stores 8-bit data from the display RAM. When display data is read, the display data specified by the address in the address counter is stored in this register. After that, the address is automatically incremented or decremented. Therefore, when an address is set, the correct data does not appear as the first data item that is read. The data in the specified address location appears as the second data item that is read. · X-address counter The X-address counter is a 64-up/down counter. It holds the row address of a location in the display RAM. Writing data to or reading data from the display RAM causes the X-address to be automatically incremented or decremented. · Y-(page) address counter The Y-(page) address counter is either a 15-up/down counter, when the word length is eight bits, or a 20-up/down counter, when the word length is six bits. It holds the column address of a location in the display RAM. Writing data to or reading data from the display RAM causes the Y-address to be automatically incremented or decremented. · Z-address counter The Z-address counter is a 64-up counter that provides the display RAM data for the LCD drive circuit. The data stored in the Z-address register is sent to the Z-address counter as the Z start address. For instance, when the Z start address is 32, the counter increments as follows: 32, 33, 34 ..., 62, 63, 0, 1, 2 ... 30, 31, 32. Therefore, the display start line is line 32 of the display RAM. · Up/down register The 1-bit datum stored in this register selects either Up or Down mode for the X-and Y-(page) address counters. · Counter select register The 1-bit datum stored in this register selects the X-address counter or Y-(page) address counter. · Display ON/OFF register This 1-bit register holds the display ON/OFF state. In the OFF state, the output data from the display RAM is cleared. In the ON state, the display RAM data is displayed. The display ON/OFF state does not affect the data in the display RAM. · Z-address register This 6-bit register holds the data which specifies the display start line. The data is loaded into the Z-address counter on the FRM signal. Using the Z-address register, vertical scrolling is possible. 6 2002-03-06 T6A04A · Word length register The 1-bit datum stored in this register selects the word length: eight bits per word or six bits per word. · Word length change circuit This circuit is controlled by the word length register. when the word length is eight bits, data is transferred eight bits at a time. When the word length is six bits, the data transfer method is shown in Figure 2 as follows: Display RAM * * D5 D4 D3 D2 D1 D0 * * D5 Word length change circuit MPU D4 D3 D2 D1 D0 Word length change circuit D7 D6 D5 D4 D3 D2 D1 D0 0 0 D5 D4 D3 D2 D1 D0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 *: INVALID Figure 2 · Oscillator The T6A04A includes an on-chip oscillator. When using this oscillator, connect an external resistor between OSC1 and OSC2, as shown in Figure 3. When using an external clock, connect the clock input to OSC1 and leave OSC2 open. /STB Internal Circuit OSC1 OSC2 Figure 3 · Timing generation circuit This circuit divides the signals from the oscillator and generates the display timing signals and the operating clock signal. · Shift register The T6A04A has two 32-bit shift registers. In disable expansion mode, both the shift registers are enabled. These two 32-bit shift registers can be combined to form a 64-bit shift register. In enable expansion mode the 32-bit shift register for COM1 to COM32 is enabled in master chip mode, and the 32-bit shift register for COM33 to COM64 is enabled in slave chip mode. · Latch circuit The latch circuit latches data from the display RAM on the rising edge of the CL signal. 7 2002-03-06 T6A04A · Column driver circuit The column driver circuit consists of 120 driver circuits. One of the four LCD driving levels is selected by the combination of the M signal and the display data transferred from the latch circuit. Details of the column driver circuit are shown in Figure 4. VLC5 Vcon VDD Display Data SEG1 to SEG120 VLC3 Vcoff VLC2 M Figure 4 · Row driver circuit The row driver circuit consists of 64 driver circuits. One of the four LCD driving levels is selected by the combination of the M signal and the data from the shift-register. Details of the row driver circuit are shown in Figure 5. VDD Vron VLC5 Shift Data COM1 to COM64 VLC4 VLC1 Vroff M Figure 5 8 2002-03-06 T6A04A · DC-DC converter The T6A04A has an on-chip DC-DC converter. When +5 V is applied to VIN, the DC-DC converter generates -5 V at VOUT. The voltage from VOUT will drop due to the load current for VEE. This characteristic is defined in “Electrical Characteristics”. Normally the value of external capacitors is 1.0 mF; this value may need some adjustment according to the application. When the T6A04A is in standby state, VOUT = 0 V. See Figure 6. Usually connected to VEE Usually connected to VDD External capacitor C = 1.0 mF External capacitor C = 1.0 mF C1 C2 VIN VOUT DC-DC Figure 6 When using an external power supply, input the voltage to VEE and leave the C1, C2 VOUT pins open. 9 2002-03-06 T6A04A · Voltage divider resistors, contrast control circuit The T6A04A has on-chip resistors which include op-amps, that divide the bias voltage, and a contrast control circuit. The voltage bias is modified by the values of R1 and R2. One of four biases can be selected. These resistors and the contrast control circuit are shown in Figure 7 below. = Voltage Follower Circuit RB = 134 kW (typ.) RC = 10.1 kW (typ.) RB RB R2 VDD VLC1 VLC2 Decoder R1 RB RB VLC3 VLC4 VLC5 5RB 4RB 3RB 2RB DB0 RC DB1 4RC 8RC Contrast Control Register 2RC DB2 DB3 16RC DB4 32RC DB5 VEE /STB DB6 Decoder DB7 Figure 7 · Op-amp, op-amp control register The T6A04A has five operational amplifiers which determine the LCD driving level. The power supplied by these op-amps is modified by the contents of the op-amp control register to match the LCD panel. The op-amp can also be controlled in such a way that it supplies full current on the rising edge of CL and a reduced current otherwise. To maintain good LCD contrast, connect a capacitor between the op-amp output and VDD. The value of the capacitor should normally be in the range 0.1 to 1.0 mF. 10 2002-03-06 T6A04A Display RAM SEG16 0 1 0 1 0 1 0 XAD1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SEG120 SEG15 SEG14 SEG13 SEG12 SEG11 1 SEG9 0 SEG8 1 SEG7 0 SEG6 1 SEG5 0 SEG4 1 SEG3 0 SEG2 XAD0 1 SEG1 SEG10 The display RAM consists of 64 rows ´ 120 columns for a total of 7680 cells. It is directly bit-mapped to the LCD. The relation between the display RAM and LCD is shown in Figure 8. When the word length is set to eight bits, the display RAM is arranged in 15 pages and each page contains 64 words. When the word length is set to six bits, the display RAM is arranged in 20 pages and each page contains 64 words. See Figure 8. COM1 COM2 120 ´ 64 dot LCD COM64 X-Address D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 LSB XAD63 MSB · 120 ´ 64 bit DISPLAY RAM Figure 8 (1) 8-bits-per-word mode PAGE0 PAGE1 Y- (page) Address PAGE13 PAGE2 PAGE14 XAD0 XAD1 D7 D0 X-Address XAD62 XAD63 (2) 6-bits-per-word mode PAGE0 PAGE1 PAGE2 Y- (page) Address PAGE18 PAGE19 XAD0 XAD1 D5 D0 X-Address XAD62 XAD63 Figure 9 11 2002-03-06 T6A04A Command Definitions Command Name D/I /WR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function DPE 0 0 0 0 0 0 0 0 1 1/0 Display ON (1)/OFF (0) 86E 0 0 0 0 0 0 0 0 0 1/0 Word Length: 8 bits (1)/6 bits (0) UDE 0 0 0 0 0 0 0 1 1/0 1/0 CHE 0 0 0 0 0 1 1 * * * OPA1 0 0 0 0 0 1 0 * 1/0 1/0 Op-amp Power Control 1 OPA2 0 0 0 0 0 0 1 * 1/0 1/0 Op-amp Power Control 2 SYE 0 0 0 0 1 SZE 0 0 0 SXE 0 0 SCE 0 STRD Counter Select : DB1 Y (1)/X (0) Mode Select : DB0 UP (1)/DOWN (0) Test Mode Select Y-(page) Address (0 to 19) Y-(page) Address Set 1 Z-Address (0 to 63) Z-Address Set 1 0 X-Address (0 to 63) X-Address Set 0 1 1 CONTRAST CONTROL (0 to 63) 0 1 B 8/6 DAWR 1 0 Write Data Display Data Write DARD 1 1 Read Data Display Data Read D R 0 0 Y/X U/D Contrast Set Status Read *: INVALID · Display ON/OFF select (DPE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 1 Display ON (03H) 0 0 0 0 0 0 0 0 1 0 Display OFF (02H) This command turns display ON/OFF. It does not affect the data in the display RAM. Note 2: An L input on /RST turns display OFF. · Word length 8 bits/6 bits select (86E) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 8 Bits/Word Mode (01H) 0 0 0 0 0 0 0 0 0 0 6 Bits/Word Mode (00H) This command sets the word length for display RAM data to eithers six bits or eight bits. Note 3: An L input on /RST sets the word length to eight bits per word. 12 2002-03-06 T6A04A · X/Y (page) counter, up/down mode select (UDE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 0 0 X-Counter/Down Mode (04H) 0 0 0 0 0 0 0 1 0 1 X-Counter/Up Mode (05H) 0 0 0 0 0 0 0 1 1 0 Y-Counter/Down Mode (06H) 0 0 0 0 0 0 0 1 1 1 Y-Counter/Up Mode (07H) This command selects the counter and the up/down mode. For instance, when X-counter/up mode is selected, the X-address is incremented in response to every data read and write. However, when X-counter/up mode is selected, the address in the Y-(page) counter will not change. Hence the Y-address must be set (with the SYE command) before it can be changed. Note 4: An L input to /RST sets the Y-counter to up mode. · Test mode select (CHE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 1 * * * *: INVALID This command selects the test mode. Do not use this command. · Set Y-(page) address (SYE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 A A A A A Range: 8-bit/Word: 20H to 2EH (page 0 to page 14) 6-bit/Word: 20H to 33H (page 0 to page 19) When operating in 8-bits-per-word mode, this command selects one of the 15 pages from the display RAM. (Do not try to select a page outside this range.) When operating in 6-bits-per-word mode, this command selects one of the 20 pages from the display RAM. Note 5: An L input to /RST sets the Y-address to page 0. · Set Z-address (SZE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 A A A A A A Range: 40H to 7FH (ZAD0 to ZAD63) This command sets the top row of the LCD screen, irrespective of the current X-address. For instance, when the Z-address is 32, the top row of the LCD screen is address 32 of the display RAM, and the bottom row of the LCD screen is address 31 of the display RAM. Note 6: An L input to /RST sets the Z-address to 0. 13 2002-03-06 T6A04A · Set X-address (SXE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 A A A A A A Range: 80H to BFH (XAD0 to XAD63) This command sets the X-address (in the range 0 to 63). An L input to /RST sets the X-address to 0. · Set contrast (SCE) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 A A A A A A Range: C0H to FFH This command sets the contrast for the LCD. The LCD contrast can be set in 64 steps. The command C0H selects the brightest level; the command FFH selects the darkest. · Op-amp control 1 (OPA1) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 * A A *: INVALID Range: 10H to 13H (when DB2 = 0) This command sets the power supply strength for the operational amplifier. This command selects one of four levels. The command 10H selects the lowest power supply strength and the command 13H selects the maximum strength. Note 7: An L input to /RST sets the op-amp power supply strength to the lowest level. · Op-amp control 2 (OPA2) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 * A A *: INVALID Range: 08H to 0BH (when DB2 = 0) This command enhances the power supply strength of the operational amplifier over a short period from the rising edge of CL. This command selects one of four levels of strength. Note 8: An L input to /RST sets t to 0 for op-amp. See Figure 10. T CL (1) When this command is 08H (2) When this command is 09H (3) When this command is 0AH (4) When this command is 0BH t=0 t t/T = 1/12 t t/T = 1/6 t t/T = 1/3 The amplifier’s strength is enhanced over the period denoted by «, starting on the rising edge of CL. Figure 10 14 2002-03-06 T6A04A · Status read (STRD) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 B 8/6 D R 0 0 Y/X U/D B (busy) : When B is 1, the T6A04A is executing an internal operation and no instruction can be accepted except STRD. When B is 0, the T6A04A can accept an instruction. 8/6 (word length) : When 8/6 is 1, the word length of the display data is eight bits per word. When 8/6 is 0, the word length of the display data is six bits per word. · D (display) : When D is 1, display is ON. When D is 0, display is OFF. R (reset) : When R is 1, the T6A04A is in reset state. When R is 0, the T6A04A is in operating state. Y/X (counter) : When Y/X is 1, the Y counter is selected. When Y/X is 0, the X counter is selected. U/D (up/down) : When U/D is 1, the X and Y counters are in up mode. When U/D is 0, the X and Y counters are in down mode. Write/read display data (DAWR/DARD) /WR D/I DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 D D D D D D D D DAWR: Display Data Write 1 1 D D D D D D D D DARD: Display Data Read The command DAWR writes the display data to the display RAM. The command DARD outputs the display data from the display RAM. However, when a data read is executed, the correct data does not appear on the first data reading. Therefore, ensure that the T6A04A performs a dummy data read before reading the actual data. 15 2002-03-06 T6A04A Function Description · X-address counter and Y-(page) address counter Figure 11-1 shows a sample operation involving the X-address counter. After Reset is executed, the X-address (XAD) becomes 0, then X-counter/up mode is selected. Next, the X-address is set to 62 using the SXE command. After data has been written or read, the X-address is automatically incremented by 1. After X-counter/down mode has been selected and data has been written or read, the X-address is automatically decremented by 1. When the X-counter is selected, the Y-counter is not incremented or decremented. Reset UDE = 05H SXE = BEH DAWR DAWR DAWR DAWR XAD = 0 X-Counter/Up Mode UDE = 04H X-Address Set XAD = 62 Data Write XAD = 63 DAWR DAWR X-Counter/Down Mode XAD = 1 XAD = 0 DAWR XAD = 0 XAD = 63 XAD = 1 XAD = 2 Figure 11-1 Figure 11-2 shows a sample operation involving the Y-address counter in 8-bit word length mode. After Reset is executed, the Y-(page) address (page) becomes 0, then Y-(page) counter/up mode and 8-bit word length mode are selected. After data has been written or read, the Y-(page) address counter is automatically incremented by 1. After Y-(page) counter/down mode has been selected and data has been written or read, the Y-(page) address is automatically decremented by 1. When the Y-(page) counter is selected, the X-counter is not incremented or decremented. Reset UDE = 07H Page = 0 Y-counter/Up mode 86E = 01H Word length 8 Bits/Word SYE = 2DH Y-address Set Page = 13 DAWR DAWR DAWR DAWR UDE = 06H DAWR DAWR Page = 14 Page = 2 X-Counter/Down Mode Page = 1 Page = 0 DAWR Page = 0 Page = 14 Page = 1 Figure 11-2 When operating in 6-bit word length mode, the Y-(page) address counter can court up to 19. If Page = 18 in up mode, after data has been written or read, the Y-(page) address (page) becomes 0. If Page = 0 in down mode, after data has been written or read, the Y-(page) address (page) becomes 18. 16 2002-03-06 T6A04A · Data read When reading data, there are some cases when dummy data must be read. This is because when the data read command invoked, the data pointed to by the address counter is transferred to the output register; the contents of the output register are then transferred by the next data read command. Therefore when reading data straight after power-on or straight after an address-setting command, such as SYE or SXE, a dummy data read must be performed. See Figure 12. Power on SYE = 20H DARD 0 SXE = 80H DARD 1 UDE = 05H SYE = 21H Dummy Read Dummy Read DARD 0 DARD 0 DARD 1 DARD 1 DARD 2 Figure 12 · Reset function When /RST = L, the reset function is executed and the following settings are mode. (3) Display .....................................OFF (4) Word length..............................8 bits/word (5) Counter mode...........................Y-counter/up mode (6) Y-(page) address.......................Page = 0 (7) X-address .................................XAD = 0 (8) Z-address..................................ZAD = 0 (9) Op-amp1 (OPA1) ......................min (10) Op-amp2 (OPA2) ......................min · Standby function When /STB = L, the T6A04A is in standby state. The internal oscillator is stopped, power consumption is reduced, and the power supply level for the LCD (VLC1 to VLC5) becomes VDD. · Busy flag When the T6A04A is executing an internal operation (other than the STRD command), the busy flag is set to logical H. The state of the busy flag is output in response to the STRD command. While the busy flag is H, no instruction can be accepted (except the STRD command). The busy state period (T) is as follows. < 4/fosc [seconds] fosc: Frequency of OSC1 2/fosc < =T= 17 2002-03-06 T6A04A · Oscillation frequency The frequency select pins (FS1 and FS2), are used to set the relation between the oscillation frequency (fOSC) and frame frequency (fM), as shown in the table below. Rf (kW) fOSC (kHz) f/f (kHz) fFRM (Hz) fM (Hz) FS1 FS2 1000 26.88 13.44 70 35 0 0 480 53.76 26.88 70 35 1 0 105 215.00 107.50 70 35 0 1 50 430.10 215.00 70 35 1 1 Note 9: The resistance values are typical values. The oscillation frequency depends on how the device is mounted. It is necessary to adjust the oscillation frequency to a target value. · Expansion function The T6A04A’s expansion function, allows two, T6A04As to drive an LCD panel of up to 240 by 64 dots. The table below shows the functions which can be selected with the M/S and EXP pins. M/S H H ● Two-chip mode (enable expansion mode) ● Two-chip mode (enable expansion mode) ● Slave chip ● Master chip COM1 to COM32 are available. ● COM33 to COM64 are available. ● Timing signals and power voltage are supplied from master chip. ● Do not select. EXP L L ● Single-chip mode (disable expansion mode) ● COM1 to COM32 are available. Figures 13-1 and -2 illustrate application examples of disable expansion mode and enable expansion mode. Enable Expansion Mode (two-chip mode) As shown in Figure 13-2, and Figure 14 the master chip supplies the LCD drive signals and power voltage to the slave chip (the oscillator, the timing circuits, op-amp and contrast control circuit are disabled). COM1 to COM32 of the master chip and COM33 to COM64 of the slave chip are available (COM33 to COM64 of the master chip and COM1 to COM32 of the slave chip are disabled). The T9841B is available as an expansion driver for the T6A04A (a T6A04A and T9841B can drive a 200 ´ 64-dot LCD panel). (1) Disable expansion mode 120 dots 32 dots 32 dots COM33 to 64 COM1 to 32 SEG1 to 120 COM32 Out 32 SEG 120 Out 120 COM32 Out 32 32-bit SR RAM 120 ´ 64 Cell 32-bit SR Figure 13-1 18 2002-03-06 T6A04A (2) Expansion mode 120 dots 120 dots 32 dots COM1 to 32 32 dots COM33 to 64 A COM Output COM fB SEG 120 Out fA Slave Chip Pf FRM B COM Output (disable) M CL C COM Output (disable) CL M SEG 120 Out Master chip FRM Pf fA D COM Output fB COMD Figure 13-2 MS = L MS = H Contrast Control 0.1 mF Op-Amp VLC1 VLC1 VLC2 VLC2 VLC3 VLC3 VLC4 VLC4 VLC5 VLC5 VEE VEE VOUT VOUT DC-DC Converter Master Slave Op-Amp Contrast Control DC-DC Converter Figure 14 19 2002-03-06 T6A04A LCD Driver Waveform fA /f CL 64 1 2 3 64 1 2 3 64 1 FRM PM M VDD V1 COM1 V4 V4 VDD V5 V1 COM2 V5 V1 V1 V4 V4 V4 V5 to VDD VDD V1 V1 COM64 V4 V4 V5 VDD VDD V2 SEG1 V3 V3 V5 VDD to VDD V2 SEG120 V3 V3 V5 ON OFF ON OFF LCD driver timing chart (1/64 duty) Absolute Maximum Ratings (Ta = 25°C) Characteristics Supply voltage (1) Symbol Rating Unit -0.3 to 7.0 V VDD - 18.0 to VDD + 0.3 V -0.3 to VDD + 0.3 V VDD (Note 10) VLC1, 2, 3, 4, 5 Supply voltage (2) VEE (Note 12) Input voltage VIN (Note 10, 11) Operating temperature Topr -20 to 75 °C Storage temperature Tstg -55 to 25 °C Note 10: Referenced to VSS = 0 V Note 11: Applies to all data bus pins and input pins except VEE, VLC1, VLC2, VLC3, VLC4 and VLC5. Note 12: Ensure that the following condition is always maintained. VDD > = VLC1 > = VLC2 > = VLC3 > = VLC4 > = VLC5 > = VEE 20 2002-03-06 T6A04A Electrical Characteristics DC Characteristics Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V ± 10%, VLC5 = 0 V, Ta = -20 to 75°C) Characteristics Operating supply (1) Operating supply (2) Symbol Test Circuit Test Condition Min Typ. Max Unit VDD ¾ ¾ 4.5 ¾ 5.5 V VDD, VIN ¾ ¾ VDD - 16.0 ¾ VDD - 4.0 V VEE, VLC5 V M/S, EXP, R1, R2, CL, M, FRM, fA, fB, COMD, FS1, FS2, Pf V DB0 to DB7, D/I, /WR, /CE, /RST, /STB V CL, M, FRM, Pf, COMD, fA, fB V D/I, /WR, /CE, DB0 to DB7, /RST, /STB VLC5 VEE PIN Name H level VIH1 ¾ ¾ 0.7 VDD ¾ VDD L level VIL1 ¾ ¾ 0 ¾ 0.3 VDD Input voltage (2) H level VIH2 ¾ ¾ 2.2 ¾ VDD L level VIL2 ¾ ¾ 0 ¾ 0.8 Output voltage (1) H level VOH1 ¾ IOH = -400 mA VDD - 0.4 ¾ VDD L level VOL1 ¾ IOL = 400 mA 0 ¾ 0.4 Output voltage (2) H level VOH2 ¾ IOH = -205 mA 2.4 ¾ VDD L level VOL2 ¾ IOL = 1.6 mA 0 ¾ 0.4 Column output resistance Rcol ¾ ¾ ¾ 7.5 kW SEG1 to SEG120 Row output resistance Rrow ¾ ¾ ¾ 1.5 kW COM1 to COM64 Input voltage (1) Input leakage IIL ¾ Operating freq. fφ ¾ VDD - VLC5 = 11.0 V Load current = ±100 mA VDD - VLC5 = 11.0 V Load current = ±100 mA VIN = VDD to GND ¾ -1 ¾ 1 mA M/S, EXP, R1, R2, CL, M, FRM, D/I, /WR, COMD, /CE, DB0 to DB7, /STB, /RST, FS1, FS2, Pf, fA, fB 10 ¾ 250 kHz /f External clock freq. fex ¾ ¾ 20 ¾ 500 kHz OSC1 External clock duty fduty ¾ ¾ 45 50 55 % OSC1 External clock rise/fall time tr/tf ¾ ¾ ¾ ¾ 50 ns VDD Current consumption (1) IDD1 ¾ (Note 13) ¾ 850 1400 mA VDD Current consumption (2) IDD2 ¾ (Note 14) ¾ 950 1600 mA VDD Current consumption (3) IDDSTB ¾ (Note 15) -1 ¾ 1 mA VDD Vo 1 (Note 16) -4.0 -4.2 ¾ V VOUT Output voltage Note 13: VDD = 5.0 V ± 10%, VEE = VOUT (from DC-DC converter) Master mode, no data access Rf = 47 kW, no load 1/9 bias, FS1, 2 = H, op-amp strength at minimum level Note 14: VDD = 5.0 V ± 10%, VEE = VOUT (from DC-DC Converter) Master mode, data access cycle f/CE = 1 MHz Rf = 47 kW, No load 1/9 bias, FS1, 2 = H, op-amp strength at minimum level Note 15: VDD = 5.0 V ± 10%, VDD - VEE = 16 V Master mode, /STB = L Note 16: VIN = 5.0 V, ILoad = 500 mA, VEE = -5.0 V (external power supply) C1 - C2 = 1.0 mF, VIN - VOUT = 1.0 mF, R = 47 kW, Ta = 25°C 21 2002-03-06 T6A04A Test Circuit 1. VDD OSC1 VIN R OSC2 C1 C C2 C R = 47 kW C = 1.0 mF ILoad ILoad = 500 mA EXTERNAL POWER SUPPLY VOUT VEE VSS AC Characteristics VIH2 VIL2 D/I VIH2 VIL2 tAH /WR VIL2 tAS VIH2 VIL2 /CE tEf Data Write tDD Data Read PWEL tDS tAH tEr VIH2 VIL2 tDHW VIH2 VIL2 Valid Data VOH2 VOL2 Valid Data tDHR VIH2 VIL2 VOH2 VOL2 tcycE Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V ± 10%, Ta = -20 to 75°C) Characteristics Symbol Min Max Unit Enable cycle time tcycE 500 ¾ ns Enable pulse width PWEL 220 ¾ ns Enable rise/fall time tEr, tEf ¾ 20 ns Address set-up time tAS 40 ¾ ns Address hold time tAH 0 ¾ ns Data set-up time tDS 60 ¾ ns Data hold time tDHW 10 ¾ ns Data delay time tDD ¾ 200 ns Data hold time tDHR 10 ¾ ns (Note 17) Load Circuit VDD D RL R D D D DB0 to 7 C RL = 2.4 kW R = 11 kW C = 130 pF (including wiring capacitance) D = 1S1588 (Note 17) Note 17: With load circuit connected 22 2002-03-06 DC-DC converter is used. · MPU RESET CIRCUIT /RESET /WR A0 An D/I A1 FS2 M/S COM1 to COM32 /RST /STB FS1 /WR /CE /IORQ DECODER LCD drive bias is 1/9. · DB0 to DB7 Oscillation frequency is at a minimum. · T6A04A single-chip mode D0 to D7 (1) Application Circuit EXP 23 R1 R2 VDD 1.0 mF VIN VOUT VEE GND 0.1 mF VCC VSS T6A04A SEG1 to SEG120 LCD 120 ´ 64-dot C2 1.0 mF C1 VLC4 VLC3 VLC2 VLC1 VLC5 OSC1 OSC2 COM33 to COM64 0.1 mF 2002-03-06 VCC T6A04A (2) RESET CIRCUIT GND 0.1 mF VCC 0.47 mF 24 T6A04A (slave) COM33 to COM64 C1 C2 CL M FRM VIN VOUT VEE FS1 M/S VDD VLC2 VLC4 Pf /STB FS2 EXP R1 R2 VSS VLC3 VLC5 fA fB VLC1 /RST CL /RST FS1 M/S VLC4 VDD VLC2 Pf /STB FS2 EXP R1 R2 VSS VLC3 VLC5 fA fB VLC1 DB0 to DB7 M DB0 to DB7 /WR /CE OSC2 OSC1 FRM VCC SEG1 to SEG120 COMD /WR VOUT VEE C1 C2 COMD SEG1 to SEG120 D/I T6A04A (master) COM1 to COM32 VIN /RESET D0 to D7 /WR A0 LCD 240 ´ 64-dot D/I /CE OSC1 OSC2 MPU An /CE2 DECODER A1 DC-DC converter is used. · /CE1 LCD drive bias is 1/9. · /IORQ Oscillation frequency is at a minimum. · T6A04A two-chip mode Application Circuit 1.0 mF VCC 1.0 mF 2002-03-06 T6A04A T6A04A RESTRICTIONS ON PRODUCT USE 000707EBE · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. · Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 25 2002-03-06