STMICROELECTRONICS STE2007

STE2007
96 x 68 Single Chip LCD Controller/Driver
Features
■
68 x 96 bits Display Data RAM
■
33,49, 65 and 68 Lines Mode
■
Row by Row Scrolling
■
Interfaces
– 3-lines Serial Interface (read and write)
– I2C (read and write)
– 4-Line Serial (read and write)
■
Partial Display Mode (33,25,17,9 Lines Mode)
■
Fully Integrated Oscillator requires no external
components
■
CMOS Compatible Inputs
■
Programmable ID-Number
■
Programmable Bias Ratio
■
Programmable Columns Organization
■
Fully Integrated Configurable LCD bias voltage
generator with:
– Selectable multiplication factor (3x, 4X and
5X)
– Effective sensing for High Precision Output
– Eight selectable temperature compensation
coefficients
■
Designed for chip-on-glass (COG) applications
November 2005
■
Low Power Consumption, suitable for battery
operated systems
■
Interfaces Supply Voltage range from 1.6 to
3.6V
■
High Voltage Generator Supply Voltage range
from 2.4 to 3.6V
■
Display Supply Voltage range from 3 to 13.2V
(Tamb = 25°C)
Description
The STE2007 is a low power LCD driver, capable
to drive 96 columns and up to 68 lines, designed
for monochrome displays.
The STE2007 includes fully integrated bias
voltage generator (up to 5x multiplication factor),
and internal oscillator, thus reducing to minimum
the number of external components required and
the current consumption.
The STE2007 features the three standard serial
interfaces (3 and 4 lines serial, I2C interface).
Order codes
Type
Ordering Number
Bumped Dice on Waffle Pack
STE2007DIE2
Rev 1
1/62
www.st.com
62
STE2007
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Driver Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
2.1
CPU Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Display Driver Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
MCU Tx Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4.1
Driver TxData Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.2
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
4.2
4.3
4.4
3-lines 9 bit Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1
MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2
Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4-Line SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1
MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.2
Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.2
Starting the Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.3
MCU TxData Mode (Write Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.4
Driver TxData Mode (Read Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reading Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.1
5
Display Data RAM (DDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
2/62
IIdentification byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DDRAM and Page/column address circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STE2007
5.2
Line address circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3
Partial Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4
6
5.3.1
33 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.2
25 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.3
17 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.4
9 Line Partial Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Command Parameters Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . 38
Instruction Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1
Initialization (Power ON Sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.2
Display Data Writing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.3
Power OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7
Power ON/Power OFF timing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1
Display ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.2
Display normal/reverse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.3
Display all points ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.4
Page address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.5
Column address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.6
Display start line address set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.7
Segment driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.8
Common driver direction select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.9
Display data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.10
Data reading from driver (Driver TxData–mode) . . . . . . . . . . . . . . . . . . . . . . 46
8.11
Power Control Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.12
VLCD set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.12.1 V0R - Voltage Range Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.12.2 VOP Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.12.3 Electronic volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.13
Power saver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.14
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.15
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.16
Image Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/62
STE2007
8.17
Bias Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.18
Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.19
Charge Pump Multiplication Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.20
Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.21
Icon Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.22
N- Line Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.23
Number of Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9
Chip Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4/62
STE2007
1
1 Introduction
Introduction
In this document is specified LCD driver for Black&White full graphic displays with a resolution
of 96x68, 96x65, 96x49, and 96x33 (ColumnsXRows).
Abbreviations
LCD
Liquid Crystal Display
COG
Chip On Glass –technology
MCU
Micro Controller Unit
DDRAM Display Data Random Access Memory
MSB
Most Significant Bit
LSB
Least Significant Bit
T.B.D.
To Be Defined
Table 1.
General Driver Parameters
Driver assembly technology
Chip On Glass (COG)
Memory Size
(Columns x Rows)
96x68
DDRAM capacity:
6528 bits
Mux
1:68
1:65
1:49
1:33
Frame frequency (Hz)
65
70
75
80
5/62
STE2007
1 Introduction
Figure 1.
Chip Mechanical Drawing
R66
STE2007
BUMP SIDE
(0,0)
Y
X
! /
!
!
45µm
VSS_AUX
72µm
VSS_AUX
VSS_AUX
VSS_AUX
R67
R65
6/62
STE2007
2 Driver Pin Description
2
Driver Pin Description
2.1
CPU Interface Pins
Table 2.
PIN
CPU Interface Logic
Signal
Type
!RES
I
Reset Input
Description
Note
!CS
I
Chip Select Input
SDOUT
0
Serial Data Output
SDAIN
I
Serial Data Input /I2C Interface Data Input
SCLK
I
Serial Clock Input/I2C Interface Clock
SDA_OUT
0
I2C Bus Data Out
when I2C Interface is
not is use
SA1
I
I2C Slave Address
Cannot be left floating
SA0
I
I2C Slave Address
Cannot be left floating
4 Line SPI Data/Command Selector
Must be connected to
VSSAUX at Module
Level when 4-Line SPI
is not in USE
When Low the
communication port is
enabled
Must be connected to
SDAIN at Module
Level
Must be left floating
!D/C
2.2
I
Power Supply Pins
Table 3.
PIN
Table 4.
PIN
Power Supply Pins
Signal
Type
VSS
VSS_LCD
VSS_CP
VDDI
VDD
VDD_CP
VSSAUX
Power
Power
Power
Power
Power
Power
Power
Description
Note
Analog & Digital Grounds
Drivers Analog Ground
Booster Ground
Digital Power
Analog Supply
Booster Power Supply
Auxiliar Vss Output
High Voltage Pins
Signal
Type
Description
Note
VLCD
High
Voltage
Booster Output
Cext = 0.1-1µF
Connected to Vss
VLCD_SENSE
High
Voltage
Booster Sense Input
Must be connected to
Vlcd at module level
7/62
STE2007
2 Driver Pin Description
Table 4.
PIN
2.3
High Voltage Pins (continued)
Signal
Type
PIN
COM0 to
COM67
High
Voltage
LCD Row Driver Output
Unused lines must be
left floating
COMS
High
Voltage
LCD Row Driver Output
Unused lines must be
left floating
SEG0 to
SEG95
High
Voltage
LCD Column Driver Output
Unused lines must be
left floating
Configuration Pin Description
Signal
Type
OSCIN
I
SEL0 -SEL1
I
IDA
Config
Description
Note
VSS/VSSAUX
Internal Oscillator Stopped
VDDI
Internal Oscillator Active
SEL1
SEL0
Interface
VSS/VSSAUX
VSS//VSSAUX
I2C
VSS/VSSAUX
VDD1
SPI 4-Lines 8 bit
VDD1
VSS/VSSAUX
Serial 3-Lines 9 bit
VDD1
VDD1
Not Used
VSS/VSSAUX
IDA=”0”
VDDI
IDA=”1”
VSS/VSSAUX
IDB=”0”
VDDI
IDB=”1”
I
IDB
I
Test Pins
Table 6.
PIN
8/62
Note
Configuration Pins
Table 5.
2.4
Description
Test Pin Description
Signal
Type
Description
Note
T2
I
Test Input. Enable Test Mode.
Must Be connected to VSS
in Normal Working Mode
T1
I
Test Input. Enable Test Mode.
Must Be connected to VSS
in Normal Working Mode
T0
I
Test Input.
Must Be connected to VSS
in Normal Working Mode
T3
O
Test Output.
Must Be OPEN in Normal
Working Mode
STE2007
2 Driver Pin Description
Table 6.
PIN
Test Pin Description (continued)
Signal
Type
Description
Note
T4
O
Test Output.
Must Be OPEN in Normal
Working Mode
T5
O
Test Output.
Must Be OPEN in Normal
Working Mode
T6
O
Test Output.
Must Be OPEN in Normal
Working Mode
VREF_B
UFF
O
Analog Test Output
Must be left floating
9/62
STE2007
3 Display Driver Electrical Characteristics
3
Display Driver Electrical Characteristics
3.1
Absolute maximum ratings
Table 7.
Absolute maximum ratings
Symbol
Unit
Supply Voltage Range
- 0.5 to + 5
V
VDD
Supply Voltage Range
- 0.5 to + 5
V
VLCD
LCD Supply Voltage Range
- 0.5 to + 14.0
V
- 50 to +50
mA
-0.5 to VDDI + 0.5
V
ISS
Supply Current
Vi
Digital Inputs Voltage
Iin
DC Input Current
- 10 to + 10
mA
Iout
DC Output Current
- 10 to + 10
mA
Ptot
Total Power Dissipation (Tj = 85°C)
300
mW
Po
Power Dissipation per Output
30
mW
Tj
Operating Junction Temperature
-40 to + 85
°C
Storage Temperature
- 65 to 150
°C
±1750
V
±2000
V
All pins vs
VDDI (*)
All other
pins / pin
combination
10/62
Value
VDDI
Tstg
Note:
Parameter
ESD Maximum Withstanding Voltage Range
Test Condition: CDF-AEC-Q100-002- “Human Body Model”
Acceptance Criteria: “Normal Performance”
(*) ESD tests have been performed with VSS, VSS_LCD and VSS_CP shorted together
STE2007
3.2
3 Display Driver Electrical Characteristics
DC Characteristics
Table 8.
DC characteristics
Symbol
VDD,VDDCP
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Power Supply Voltage
Operating Voltage
2.4
3.6
V
VDDI
Power Supply Voltage(Logic)
I/O supply Voltage
1.6
3.6
V
VLCD
Booster Output
13.5
V
13.5
V
2
%
VLCD_SENSE Booster Sense Input
VLCD
I(VDDI)
LCD Supply Voltage Accuracy
Logic Supply Current
VLCD=10V; VDD=2.6V; Tamb =
25°C; No display Load;
fSCLK=0Hz
-2
Power Saver Mode ON
(Interfaces quiescent)
1
3
µA
Power Saver Mode OFF
(Interfaces quiescent)
6
20
µA
120
250
µA
90
180
µA
VDDI
V
0.3VDD
V
Write Mode
I(VDD+VDDCP) Analog Supply Current
VLCD=10V;Booster= 5X;
fSCLK=0Hz; VDD=2.4V
Refresh Rate=75Hz;
no display load;Tamb = 25°C
Logic Inputs
VIH
Logic High level input voltage
0.7VDD
VIL
Logic Low level input voltage
Vss
IIH
Logic High level input current
1
µA
IlL
Logic Low level input current
-1
µA
VDDI
V
0.2VDDl
V
I
I
Logic Outputs
VOH
Logic High level output voltage lOUT = -500µA; VDDI=1.6V
VOL
Logic Low level output voltage
lOUT = 500µA; VDDI=1.6V
0.8VDD
I
Vss
Note: 1 Tamb = -40 to 85°C, unless otherwise specified.
11/62
STE2007
3 Display Driver Electrical Characteristics
3.3
AC Characteristics
Table 9.
AC Operation - Internal Oscillator
Symbol
FFRAME
3.4
Parameter
Test Condition
Frame Frequency Default
VDDI= 1.6; VDD= 2.9V
Rafresh Rate = 75Hz
Tamb = -20°C to +70°C
Min.
Typ.
Max.
Unit
68
75
82
Hz
Typ.
MCU Tx Data Mode
Table 10.
AC Characteristics for Serial interface
Description
Signal
Chip Select
Symbol
tcss
tcsh
tchw
tsds
tsdh
tac
!CS
Input Serial Data Interface
SDAIN
Output Serial Data interface
SDAOUT
tod
tscyc
Serial clock input
tshw
SCLK
tslw
Notes
Min.
Data setup time
Data hold time
Access Time
Output Disable
Time
Serial clock cycle
Serial clock H
pulse width
Serial clock L
pulse width
Max.
Unit
60
100
50
100
100
0
125
100
ns
ns
ns
ns
ns
ns
25
100
ns
250
ns
100
ns
100
ns
Note: 1 The input signal rise and fall times must be within 10ns.
2 Every timing is specified on the basis of 30% and 70% of VDDI.
3 Tamb = -40 to 85°C, unless otherwise specified.
Figure 2.
MCU TxData timing
tcss
tchw
tchw
tcsh
!CS
tscyc
tslw
SCLK
tshw
tf
SDA/MCU TxData
12/62
tsds
tr
tsdh
STE2007
Table 11.
3 Display Driver Electrical Characteristics
Input Signals Change Time
Signal
Symbol
Inputs
tr,tf
3.4.1
Parameter
Minimum
Typical/
Maximum
Nominal
10
Unit / Notes
ns / to 30% & 70% levels
Driver TxData Mode
Table 12.
Timings based on 4 MHz SCLK Speed
Item
Data hold time
Access time
Output disable time
Data setup time
!CS pulse width high
Symbol
T1
T2
T3
T4
T5
Condition
Note 1
–
–
–
–
Rating
Units
Min.
Max.
100
10
25
100
250
125
100
100
–
ns
ns
ns
ns
ns
Note: 1 Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is Always 3-8ns
before SCLK pulse falling edge
2 The input signal rise and fall times must be within 10ns.
3 Every timing is specified on the basis of 30% and 70% of VDDI.
4 Tamb = -40 to 85°C, unless otherwise specified.
Table 13.
Timings based on 1 MHz SCLK Speed
Item
Data hold time *)
Access time
Output disable time
Data setup time
1CS pulse width high
Symbol
T1
T2
T3
T4
T5
Condition
–
–
–
–
–
Rating
Units
Min.
Max.
100
10
25
100
250
125
450
450
–
ns
ns
ns
ns
ns
Note: 1 The input signal rise and fall times must be within 10ns.
2 Every timing is specified on the basis of 30% and 70% of VDDI.
3 Tamb = -40 to 85°C, unless otherwise specified.
13/62
STE2007
3 Display Driver Electrical Characteristics
Figure 3.
Driver TxData Mode AC timing characteristics
Timing A
Timing B
SCLK
Command
MCU TxData
Command
Hi±Z
MCU Data direction
Tx
Rx
Tx
Driver TxData
Hi±Z
Status
Hi±Z
T1
Timing A
T2
SCLK
MCU TxData
Driver TxData
Driver SDA direction
in
out
!CS
T3
Timing B
T4
SCLK
MCU TxData
D/C
Driver TxData
Driver SDA direction
out
in
T5
!CS
1/2 SCLK
3.4.2
1/2 SCLK
Reset Timing
Table 14.
Reset Timing
Description
Signal
Symbol
Min.
Reset time
Reset low pulse width (for valid reset)
Reset rejection (for noise spike)
!RES
!RES
!RES
trs
trw
trj
2500
Note: 1 The input signal rise and fall times must be within 10ns.
2 Every timing is specified on the basis of 30% and 70% of VDDI.
3 Tamb = -40 to 85°C, unless otherwise specified.
14/62
Max.
Unit
2500
ns
1000
STE2007
3 Display Driver Electrical Characteristics
Figure 4.
trj
trw
!RES
trs
Internal circuit status
During reset
Normal operation
15/62
STE2007
4 INTERFACE
4
INTERFACE
4.1
3-lines 9 bit Serial Interface
STE2007 3-lines 9 bits serial interface is a bidirectional link between the display driver and the
host processor.
It consists of three lines:
–
SDAIN/SDAOUT Serial Data
–
SCLK Serial Clock
–
!CS Peripheral enable: - Active Low- Enables and Disables the serial interface
The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of
!RES, the serial interface is ready to receive data after the internal reset time. Serial data must
be input to SDA in the sequence D/!C, D7 to D0. STE2007 read data on SCLK rising edge. The
first bit of serial data D/!C is data/command flag. When D/!C =”1” D7 to D0 bits are display RAM
data or Command Parameters. When D/!C=”0” D7 to D0 bits identify a command
4.1.1
MCU TxData Mode (Write Mode)
STE2007 is always a slave device on the communication bus and receive the communication
clock on the SCLK pin from the master. Information are exchanged word-wide. Every word is
composed by 9 bit. The first bit is named D/!C and indicates whether the following byte is a
command (D/!C =0) or a Display Data Byte (D/!C =1).
During data transfer, the data line is sampled by the receiver unit on the SCLK rising edge.
The data/command received is transferred to DDRAM or Executed on the first falling edge after
the latching rising edge or on the !CS rising edge.
If !CS stays low after the last bit of a command/data byte, the serial interface expects the D/!C
bit of the next data byte on the next SCLK positive edge.
A reset pulse on !RES pin interrupts any transmission.
Figure 5.
!CS
SDA
D/C D7
SCLK
1
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0 D/C
9
10
D7
11
D6
12
D5
13
D4
14
4.1.1.1 Data/Command Transfer break
If the Host processor generates an break condition (!CS Line HIGH before having received Bit
D0) while transferring a Data byte to the Frame Memory or a Command identifier or a command
parameter, the not complete received byte is discarded, the communication is interrupted and
the interface is forced in reset state.
When !CS line becomes low again to start a new communication session STE2007 is ready to
receive the same byte interrupted re-transmitted or a new command identifier.
16/62
STE2007
Figure 6.
4 INTERFACE
3-lines SPI Data Transfer break condition
Break
!CS
SCL
SDA
D7
D6
D5
D4
D3
D/!C
COMMAND/PARAMETER
D7
D6
D5
D4
COMMAND/PARAMETER
LR0204
4.1.1.2 Data/Command Transfer pause
It is possible while transferring Frame Memory Data, Commands or Command Parameters to
insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS is
forced high after a whole byte received, the received byte is processed. Then STE2007 is
forced in a wait state ready to restart processing incoming data from the point where the
communication has been paused
If a new command identifier is transferred after a pause condition the previous communication
session is definitively closed.
Four are the possible conditions:
Figure 7.
–
Command-Pause-Command
–
Command-Pause-Parameter
–
Parameter-Pause-Command
–
Parameter-Pause-Parameter
3-lines SPI Data Transfer Pause
Pause
!CS
SCL
SDA
D3
D2
D1
D0
D/!C
COMMAND/PARAMETER
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND/PARAMETER
LR0203
4.1.2
Driver TxData Mode (Read Mode)
The Driver TxData–mode is a method to check the electrical interconnection between LCD
driver and baseband, to identify the driver and for VDD Intercfonnection electrical self testing.
17/62
STE2007
4 INTERFACE
Self Testing of the electrical contacts is based on the monitoring of VLCD. The improper
electrical contact on VDD can be noted from a too low level of VLCD.
The serial interface Driver TxData–mode is controlled by three input signals.
The serial data output (SDAOUT/Driver TxData) and serial clock input (SCLK) are enabled
when !CS is low after having received one Reading Command.
To access Driver TxData–mode a Reading command must be sent to STE2007 driver. The first
bit (D/C) is low to indicates next 8–bits are for command. The data is read to the driver on the
rising edge of SCLK (see section ”MCU TxData–mode”). After last command bit (bit 0) is read
SDAOUT becomes active (Low impedance) and MCU is able to read data from driver.
SDAOUT is forced in high impedence when !CS line is forced high or after the eight SCLK rising
edges from the last SCLK rising edge of teh reading command transfer (Figure 8).
After sending out all 8 bits the driver release automatically the bus and go back to the MCU
TxData–mode. MCU Txdata line changes from high–z to active low or high in the falling edge of
8th SCLK pulse. !CS must be set high and low again before !D/C writing can continue.
If !CS is forced high during the Driver TxDAta-mode, the Driver Tx data session is aborted and
SDAOUT is forced in high impedance Mode.
SDAOUT and SDAIN line can be short circuited in normal working conditions.
Figure 8.
AC timing characteristics
Timing A
Timing B
SCLK
Command
MCU TxData
Command
Hi±Z
MCU Data direction
Tx
Rx
Tx
Driver TxData
Hi±Z
Status
Hi±Z
T1
Timing A
T2
SCLK
MCU TxData
Driver TxData
Driver SDA direction
in
out
!CS
T3
Timing B
T4
SCLK
MCU TxData
D/C
Driver TxData
Driver SDA direction
out
in
T5
!CS
1/2 SCLK
18/62
1/2 SCLK
STE2007
4 INTERFACE
Figure 9.
Timing chart for start and stop of data reading from driver
Self Test command writing
SCLK
1
...
2
MCU TxData D/C='0'
0
...
7
Driver TxData
9
1
...
2
1
7
6
...
MCU TxData begins
D/C writing
1
8
7
High Z
...
0
High Z
!CS
4.2
8
Reading of status
...
2
D/C
1
7
0
...
Driver TxData begins
MCU TxData begins
4-Line SPI
STE2007 4-lines serial interface is a bidirectional link between the display driver and the host
processor.
It consists of four lines:
–
SDA Serial Data
–
SCL Serial Clock
–
!CS Peripheral enable: - Active Low- Enables and Disables the serial interface
–
Mode selection (D/!C).
The serial interface is active only if the !CS line is low. If !CS is low after the positive edge of
!RES, the serial interface is ready to receive data after the internal reset time.
4.2.1
MCU TxData Mode (Write Mode)
STE2007 is always a slave device on the communication bus and receive the communication
clock on the SCL pin from the master. Information are exchanged byte-wide. During data
transfer, the data line is sampled by the receiver unit on the SCL rising edge.
D/!C line status set whether the byte is a command (D/!C =0) or a data (D/!C =1); D/!C line is
read on the eighth SCL clock pulse during every byte transfer.
If !CS stays low after the last bit of a command/data byte, the serial interface expects the MSB
of the next data byte on the next SCL positive edge.
If !CS line is forced high in the middle of a data transfer, not complete Data bytes and
Commands bytes are discarded.
A reset pulse on !RES pin interrupts any transmission.
19/62
STE2007
4 INTERFACE
Figure 10. 4-lines SPI Commands Transfe
!CS
D/!C
SCL
SDA
(input)
SDA
(output)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D0
D6
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
COMMAND
COMMAND
COMMAND
COMMAND
LR0189
Figure 11. 4-lines SPI Video Data Write Cycle
!CS
D/!C
SCL
SDA
(input)
SDA
(output)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D0
D6
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
COMMAND
DATA to VIDEO RAM
DATA to VIDEO RAM
DATA to VIDEO RAM
LR0190
4.2.1.1 Data/Command Transfer break
If the Host processor generates an break condition (!CS Line HIGH before having received Bit
D0) while transferring a Data byte to the Frame Memory or a Command identifier or a command
parameter, the not complete received byte is discarded, the communication is interrupted and
the interface is forced in reset state.
When !CS line becomes low again to start a new communication session STE2007 is ready to
receive the same byte interrupted re-transmitted or a new command identifier.
Figure 12. 4-lines SPI Data Transfer break condition
Break
!CS
D/!C
SCL
SDA
D7
D6
D5
D4
COMMAND/PARAMETER
D3
D7
D6
D5
D4
D3
COMMAND/PARAMETER
LR0192
4.2.1.2 Data/Command Transfer pause
It is possible while transferring Frame Memory Data, Commands or Command Parameters to
insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS is
forced high after a whole byte received, the received byte is processed. Then STE2007 is
forced in a wait state ready to restart processing incoming data from the point where the
communication has been paused
20/62
STE2007
4 INTERFACE
If a new command identifier is transferred after a pause condition the previous communication
session is definitively closed.
Four are the possible conditions:
–
Command-Pause-Command
–
Command-Pause-Parameter
–
Parameter-Pause-Command
–
Parameter-Pause-Parameter
Figure 13. 4-lines SPI Data Transfer Pause
Pause
!CS
D/!C
SCL
SDA
D3
D2
D1
D0
D7
D6
D5
COMMAND/PARAMETER
D4
D3
D2
D1
D0
COMMAND/PARAMETER
LR0191
4.2.2
Driver TxData Mode (Read Mode)
Throughout SDA line is possible to read some registers value (ID Numbers, Status byte,
temperature).
SDA (output Driver) is in High impedance in steady state and during data write.
Figure 14. 4-lines SPI 8Bit Read Cycle
DATA
Read Command
Next Command
!CS
D!C
SCL
SDA
(Input)
D7
D6
D5
D4
High Z
SDA
(Output)
D3
D2
D1
High Z
D0
D7
D6
D5
D4
D3
D7
D2
D1
D6
D5
D4
D3
D2
D1
D0
D0
LR0255
MCU Data Tx Start
4.3
LCD Driver Data Tx Start
MCU Data Tx Start
I2C Bus
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different ICs. It consists of two lines: one bidirectional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines
must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
21/62
STE2007
4 INTERFACE
–
Data transfer may be initiated only when the bus is not busy.
–
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as a Start or
Stop Data Transfer condition (see below).
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is
High, define the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit of
data.
Each data transfer starts with a start condition and terminated with a stop condition. The
number of data bytes transferred between the start and the stop conditions is not limited. The
information is transmitted byte-wide and each receiver acknowledges with the ninth bit.
By definition, a device that gives out a message is called "transmitter", the receiving device that
gets the signals is called "receiver". The device that controls the message is called "master".
The devices that are controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge
bit is a low level put on the bus by the receiver, whereas the master generates an extra
acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each
byte. Also, a master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to pull
down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time
must be taken into account. A master receiver must signal an end-of-data to the slave
transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave the data line High to enable the master to
generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.
Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous
in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the
SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the
bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during
the acknowledge cycle the STE2007 will not be able to create a valid logic 0 level. By splitting
the SDA input from the output the device could be used in a mode that ignores the
acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary
to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a
valid LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2007 is able to detect the
special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in Hsmode without detecting the master code.
22/62
STE2007
4 INTERFACE
Figure 15. Bit transfer and START,STOP conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
D00IN1151
Figure 16. Acknowledgment on the I2C-bus
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
D00IN1152
4.3.1
Communication Protocol
The STE2007 is an I2C slave. The access to the device is bi-directional since data write and
status read are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits
(01111). The two least significant bit of the slave address are set by connecting the SA0 and
SA1 inputs to a logic 0 or to a logic 1.
4.3.2
Starting the Communication
To start the communication between the bus master and the slave LCD driver, the master must
initiate a START condition. Following this, the master sends an 8-bit byte, on the SDA bus line
(Most significant bit first). This consists of the 7-bit Device Address Code, and the 1-bit Read/
Write Designator (R/W). The R/W bit has to be set to logic 1 to logic 0 according to the type of
communication (read or write).
All slaves with the corresponding address acknowledge in parallel, all the others will ignore the
I2C-bus transfer.
STE2007
SLAVE ADDRESS
ADDRESS BYTE
S S R
0 1 1 1 1 A A /
1 0 W
READ or WRITE
DESIGNATOR
23/62
STE2007
4 INTERFACE
4.3.3
MCU TxData Mode (Write Mode)
If the R/W bit is set to logic 0 the STE2007 is set to be a receiver and the master can send
commands or data.
After the communication has started and slaves have acknowledged, the master sends a
control byte defined as follows and waits for its acknowledgement:
CONTROL BYTE
Co DC
0
0
0
0
0
0
The Co bit is the control byte MSB and defines if after this control byte will follow a single byte
sequence (Co = 1) or a multiple bytes sequence (Co = 0). The D/C bit defines whether the
following byte (if Co = 1) or the following stream of bytes (if Co = 0) are command (D/C = 0) or
DDRAM data (D/C = 1).
Depending on state of flags Co and D/C, four writing sequences are possible:
SINGLE COMMAND BYTE SEQUENCE (Co = 1, D/C = 0): a single byte interpreted as a
command will follow the control byte;
SINGLE DATA BYTE SEQUENCE (Co = 1, D/C = 1): a single byte interpreted as a data to be
written in DDRAM will follow the control byte;
MULTIPLE COMMAND BYTES SEQUENCE (Co = 0, D/C = 0): a stream of bytes will follow the
control byte, with each single byte interpreted as a command;
MULTIPLE DATA BYTES SEQUENCE (Co = 0, D/C = 1): a stream of bytes will follow the
control byte, with each byte interpreted as a data byte to be written in DDRAM.
Every single byte of a sequence must be acknowledged by all addressed units.
A multiple data sequence is terminated only by sending a STOP condition on the I2C bus.
When a sequence is terminated, another sequence of any type can follow or a I2C STOP
condition can be sent to close the communication.
In a single or multiple data bytes sequence, every data byte received is stored in the DDRAM at
the location specified by the current values of data pointers. Data pointers are automatically
updated after each single data byte written.
24/62
STE2007
4.3.4
4 INTERFACE
Driver TxData Mode (Read Mode)
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the
D/C bit during the last write access, is set to a logic 0, the byte read is the status byte.
Figure 17. Communication Protocol
WRITE MODE
COMMUNICATION
START
STE2007 ACK
I2C START 0
COND
1
1
1
1
SINGLE COMMAND
SEQUENCE
STE2007 ACK
1 0 0 0 0 0 0 0 A
MULTIPLE COMMAND
SEQUENCE
STE2007 ACK
Control Byte
SINGLE DATA
SEQUENCE
A
Last Command Byte
STE2007 ACK
STE2007 ACK
DATA Byte
A
Data Byte
STE2007 ACK
0 1 0 0 0 0 0 0 A
STE2007 ACK
DATA Byte
Control Byte
COMMUNICATION
STOP
STE2007 ACK
COMMAND Byte
A
First Command Byte
Control Byte
MULTIPLE DATA
SEQUENCE
STE2007 ACK
COMMAND Byte
1 1 0 0 0 0 0 0 A
Co D/C
A
Command Byte
0 0 0 0 0 0 0 0 A
Co D/C
STE2007 ACK
COMMAND Byte
Control Byte
Co D/C
A
R/W
SLAVE ADDRESS
Co D/C
0
SA1 SA2
A
STE2007 ACK
DATA Byte
A
Last Data Byte
First Data Byte
I2C STOP
COND
READ MODE
STE2007 ACK
STATUS BYTE READ
SEQUENCE
I2C START
0
COND
1
1
1
1
SA1 SA2
0 A
MASTER ACK
STATUS Byte
A
I2C START
COND
R/W
SLAVE ADDRESS
LR0008d
25/62
STE2007
4 INTERFACE
4.4
Reading Mode
STE2007 features a reading Command to transmitt data from the LCD driver to Host
Processor. After the reading command STE2007 transfers 8 bits to the Host controller:
–
4.4.1
Identification Byte (Command Code DBhex)
IIdentification byte
Identification byte is an 8 Bit code that identify the module revision Number.
Table 15.
Bit nr
ID byte format
D7(MSB) D6
0
0
D5
D4
D3
D2
D1
D0(LSB)
IDB PAD
IDA PAD
0
0
0
0
Figure 18.
STE2007
Power IC
VDDCP
VDD
VDDI
VSS
VSSCP
VDD
VDDI
GND
ASIC(MCU)
Command decoder
MCU TxData
8 bit register
RESET
Multi
plexer
SDA
XCS
ID
test
SCLK
Driver TxData
Auto
return
VLCD
Voltage booster
BaseBand side
LCD Power
Supply circuit
Driver side
Figure 19.
Identification Information
Send rading command (DBh)
Read status(ID data)
Send reset command
26/62
Command:E2H
STE2007
5 Display Data RAM (DDRAM)
5
Display Data RAM (DDRAM)
5.1
DDRAM and Page/column address circuit
The DDRAM stores pixel data for LCD. It is a 68–row (8 page by 8 bits +4) by 96–column
addressable array. D7 to D0 display data from MCU corresponds to the LCD common direction.
”0” bit in DDRAM is a OFF–dot on display and ”1” bit in DDRAM is displayed as ON–dot on
display.
Figure 20. DDRAM vs. display on LCD
D0
0
1 1
1
1
COM0
D1
1
0 0
0
0
COM1
D2
0
0 0
0
1
COM2
D3
0
0 1
1
0
COM3
D4
±±
1
1 0
0
1
COM4
±±
DDRAM
Display on LCD
Each pixel can be selected when page address and column address are specified. The MCU
issues Page address set command to change the page and access to another page. In
DDRAM page address 8 (D3,D2,D1,D0=1,0,0,0) only display data D0,D1,D2 & D3 are valid.
The DDRAM column address is specified by Column address set command.
The specified column address is automatically incremented by +1 when a Display data write
command is entered. After the last column address (5Fh), column address returns to 00h and
page address incremented by +1. After the very last address (column=5Fh, page=8h), both
column address and page address return to 00h (column address=00h, page address=0h).
Figure 21. Column address in normal mode
Data
LSBit D0
D1
D2
D3
D4
D5
D6
MSBit D7
Data for page address 0H to 07H
0H
1H
2H
3H
Page address 4H
5H
6H
7H
8H
0
96
192
288
384
480
576
672
768
00H
1
97
193
289
385
481
577
673
769
01H
2
98
194
290
386
482
578
674
770
02H
94
190
286
382
478
574
670
766
862
5EH
95
191
287
383
479
575
671
767
863
5FH
Column address
D0
D1
D2
D3
Data for page address 8H
27/62
STE2007
5 Display Data RAM (DDRAM)
Figure 22. Column address in reversed mode
Data for page address 0H to 07H
95
94
191
287
383
479
575
671
767
863
190
286
382
478
574
670
766
862
98
194
290
386
482
578
674
770
5FH 5EH
97
193
289
385
481
577
673
769
0H
96 1H
192 2H
288 3H
384 4H
480 5H
576 6H
672 7H
768 8H
Data
D0 LSBit
D1
D2
D3
D4
D5
D6
D7 MSBit
Page address
02H 01H 00H
Column address
D0
D1
D2
D3
Data for page address 8H
Data can be written to the DDRAM at the same time as data is being displayed, without causing
the LCD to flicker.
Segment driver direction command can be used to reverse the relationship between the
DDRAM column address and segment output. This function is achieved writing data into
DDRAM in reverse order (from Right to left).
Table 16.
5.2
Column address direction
Column
address
00H
Normal
Direction
SEG0
Reverse
Direction
SEG95
01H
02H
5DH
5EH
5FH
5DH
SEG1
SEG2
______
SEG93
SEG94
SEG95
SEG94
SEG93
______
SEG2
SEG1
SEG0
Line address circuit
The line address circuit specifies the line address relating to the COM output when the contents
of the DDRAM are displayed. The display start line that is normally the top line of the display,
can be specified by Display start line address set command.
STE2007 features Four different Multiplexing Mode to fine tune the duty ratio on the display
size:
28/62
–
68 Lines Display
–
65 Lines Display
–
49 Lines Display
–
33 Lines Display
STE2007
5 Display Data RAM (DDRAM)
Figure 23. 68–line Mode
ICONMODE="0"
ICONMODE="1"
Page address
D3 D2 D1 D0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
D
a
t
a
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
Column address
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
59H 5AH 5BH 5CH 5DH 5EH 5FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Start
COM Output
Normal Reverse
direction direction
COM66
COM0
COM65
COM1
COM64
COM2
COM3
COM63
COM4
COM62
COM5
COM61
COM6
COM60
COM7
COM59
COM8
COM58
COM9
COM57
COM10 COM56
COM11 COM55
COM12 COM54
COM13 COM53
COM14 COM52
COM15 COM51
COM16 COM50
COM17 COM49
COM18 COM48
COM19 COM47
COM20 COM46
COM21 COM45
COM22 COM44
COM23 COM43
COM24 COM42
COM25 COM41
COM26 COM40
COM27 COM39
COM28 COM38
COM29 COM37
COM30 COM36
COM31 COM35
COM32 COM34
COM33 COM33
COM34 COM32
COM35 COM31
COM36 COM30
COM37 COM29
COM38 COM28
COM39 COM27
COM40 COM26
COM41 COM25
COM42 COM24
COM43 COM23
COM44 COM22
COM45 COM21
COM46 COM20
COM47 COM19
COM48 COM18
COM49 COM17
COM50 COM16
COM51 COM15
COM52 COM14
1
COM53 COM13
COM54 COM12
COM55 COM1
COM56 COM10
COM57 COM9
COM58 COM8
COM59 COM7
COM60 COM6
COM61 COM5
COM62 COM4
COM63 COM3
COM64 COM2
COM65 COM1
COM66 COM0
COMS
COMS
Display start line does not access 65th, 66th, 67th, 68th line
SEG
Output
Normal
Direction
Reverse
Direction
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Start
COM Output
Normal Reverse
direction direction
COM0
COMS
COM66
COM1
COM65
COM2
COM3
COM64
COM4
COM63
COM5
COM62
COM6
COM61
COM7
COM60
COM8
COM59
COM9
COM58
COM10 COM57
COM11 COM56
COM12 COM55
COM13 COM54
COM14 COM53
COM15 COM52
COM16 COM51
COM17 COM50
COM18 COM49
COM19 COM48
COM20 COM47
COM21 COM46
COM22 COM45
COM23 COM44
COM24 COM43
COM25 COM42
COM26 COM41
COM27 COM40
COM28 COM39
COM29 COM38
COM30 COM37
COM31 COM36
COM32 COM35
COM33 COM34
COM34 COM33
COM35 COM32
COM36 COM31
COM37 COM30
COM38 COM29
COM39 COM28
COM40 COM27
COM41 COM26
COM42 COM25
COM43 COM24
COM44 COM23
COM45 COM22
COM46 COM21
COM47 COM20
COM48 COM19
COM49 COM18
COM50 COM17
COM51 COM16
COM52 COM15
COM53 COM14
COM54 COM13
COM55 COM12
COM56 COM11
COM57 COM10
COM58 COM9
COM59 COM8
COM60 COM7
COM61 COM6
COM62 COM5
COM63 COM4
COM64 COM3
COM65 COM2
COM66 COM1
COM0
COMS
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
95
S
E
G
0
29/62
STE2007
5 Display Data RAM (DDRAM)
Figure 24. 65–line Mode
ICONMODE="0"
ICONMODE="1"
D
a
D3 D2 D1 D0 at
Page address
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Column address
SEG
Output
30/62
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
Normal
Direction
Reverse
Direction
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
59H 5AH 5BH 5CH 5DH 5EH 5FH
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
S
E
G
95
S
E
G
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Start
COM Output
Normal Reverse
direction direction
COM0
COM63
COM1
COM62
COM2
COM61
COM3
COM60
COM4
COM59
COM5
COM58
COM6
COM57
COM7
COM56
COM8
COM55
COM9
COM54
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM62 COM1
COM63 COM0
COM64 COM64
Display start line does not access 65th, 66th, 67th, 68th line
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Start
COM Output
Normal Reverse
direction direction
COM64
COM0
COM1
COM63
COM2
COM62
COM3
COM61
COM4
COM60
COM5
COM59
COM6
COM58
COM7
COM57
COM8
COM56
COM9
COM55
COM10 COM54
COM11 COM53
COM12 COM52
COM13 COM51
COM14 COM50
COM15 COM49
COM16 COM48
COM17 COM47
COM18 COM46
COM19 COM45
COM20 COM44
COM21 COM43
COM22 COM42
COM23 COM41
COM24 COM40
COM25 COM39
COM26 COM38
COM27 COM37
COM28 COM36
COM29 COM35
COM30 COM34
COM31 COM33
COM32 COM32
COM33 COM31
COM34 COM30
COM35 COM29
COM36 COM28
COM37 COM27
COM38 COM26
COM39 COM25
COM40 COM24
COM41 COM23
COM42 COM22
COM43 COM21
COM44 COM20
COM45 COM19
COM46 COM18
COM47 COM17
COM48 COM16
COM49 COM15
COM50 COM14
COM51 COM13
COM52 COM12
COM53 COM11
COM54 COM10
COM55 COM9
COM56 COM8
COM57 COM7
COM58 COM6
COM59 COM5
COM60 COM4
COM61 COM3
COM62 COM2
COM63 COM1
COM64 COM0
STE2007
5 Display Data RAM (DDRAM)
Figure 25. 49–line Mode
ICONMODE="0"
ICONMODE="1"
D
a
D3 D2 D1 D0 at
Page address
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
Column address
SEG
Output
Line
Address
Normal
Direction
Reverse
Direction
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
59H 5AH 5BH 5CH 5DH 5EH 5FH
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Start
COM Output
Normal Reverse
direction direction
COM0
COM47
COM1
COM46
COM2
COM45
COM3
COM44
COM4
COM43
COM5
COM42
COM6
COM41
COM7
COM40
COM8
COM39
COM9
COM38
COM10 COM37
COM11 COM36
COM12 COM35
COM13 COM34
COM14 COM33
COM15 COM32
COM16 COM31
COM17 COM30
COM18 COM29
COM19 COM28
COM20 COM27
COM21 COM26
COM22 COM25
COM23 COM24
COM24 COM23
COM25 COM22
COM26 COM21
COM27 COM20
COM28 COM19
COM29 COM18
COM30 COM17
COM31 COM16
COM32 COM15
COM33 COM14
COM34 COM13
COM35 COM12
COM36 COM11
COM37 COM10
COM38 COM9
COM39 COM8
COM40 COM7
COM41 COM6
COM42 COM5
COM43 COM4
COM44 COM3
COM45 COM2
COM46 COM1
COM47 COM0
COM64
COM64
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Start
COM Output
Normal Reverse
direction direction
COM0
COM48
COM47
COM1
COM46
COM2
COM45
COM3
COM44
COM4
COM43
COM5
COM42
COM6
COM41
COM7
COM40
COM8
COM39
COM9
COM10 COM38
COM11 COM37
COM12 COM36
COM13 COM35
COM14 COM34
COM15 COM33
COM16 COM32
COM17 COM31
COM18 COM30
COM19 COM29
COM20 COM28
COM21 COM27
COM22 COM26
COM23 COM25
COM24 COM24
COM25 COM23
COM26 COM22
COM27 COM21
COM28 COM20
COM29 COM19
COM30 COM18
COM31 COM17
COM32 COM16
COM33 COM15
COM34 COM14
COM35 COM13
COM36 COM12
COM37 COM11
COM38 COM10
COM39 COM9
COM40 COM8
COM41 COM7
COM42 COM6
COM43 COM5
COM44 COM4
COM45 COM3
COM46 COM2
COM47 COM1
COM48 COM0
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
95
S
E
G
0
31/62
STE2007
5 Display Data RAM (DDRAM)
Figure 26. 33–line Mode
ICONMODE="0"
ICONMODE="1"
D
a
D3 D2 D1 D0 at
Page address
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
Column address
SEG
Output
5.3
Line
Address
Normal
Direction
Reverse
Direction
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
59H 5AH 5BH 5CH 5DH 5EH 5FH
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Start
COM Output
Normal Reverse
direction direction
COM0
COM31
COM1
COM30
COM2
COM29
COM3
COM28
COM4
COM27
COM5
COM26
COM6
COM25
COM7
COM24
COM8
COM23
COM9
COM22
COM10 COM21
COM11 COM20
COM12 COM19
COM13 COM18
COM14 COM17
COM15 COM16
COM16 COM15
COM17 COM14
COM18 COM13
COM19 COM12
COM20 COM11
COM21 COM10
COM22 COM9
COM23 COM8
COM24 COM7
COM25 COM6
COM26 COM5
COM27 COM4
COM28 COM3
COM29 COM2
COM30 COM1
COM31 COM0
COM64
COM64
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Start
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
95
S
E
G
0
Partial Display
STE2007 feature four configuration for Partial Display function:
–
33 Line Partial Display
–
25 Line Partial display
–
16 Line Partial Display
–
9 Line Partial Display
Partial display Area location on the screen is defined by Image Location Parameter.
Image Location + Partial display area > Multiplexing rate.
32/62
COM Output
Normal Reverse
direction direction
COM32
COM0
COM31
COM1
COM30
COM2
COM29
COM3
COM28
COM4
COM27
COM5
COM26
COM6
COM25
COM7
COM24
COM8
COM23
COM9
COM10 COM22
COM11 COM21
COM12 COM20
COM13 COM19
COM14 COM18
COM15 COM17
COM16 COM16
COM17 COM15
COM18 COM14
COM19 COM13
COM20 COM12
COM21 COM11
COM22 COM10
COM23 COM9
COM24 COM8
COM25 COM7
COM26 COM6
COM27 COM5
COM28 COM4
COM29 COM3
COM30 COM2
COM31 COM1
COM32 COM0
STE2007
5 Display Data RAM (DDRAM)
Figure 27.
Display
Display
Image Location + Partial display area width <= Multiplexing rate
Image Location + Partial display area width > Multiplexing rate
When Partial Display Mode is enabled the user has to Update the Operative Voltage, Bias Ratio
and Charge Pump Setting to match the new working conditions.
5.3.1
33 Line Partial Display Mode
Partial Display Area is composed of 33 Lines. Memory vs. Row Drivers Mapping is defined
according to the following parameters:
–
Multiplexing Value
–
IL[2:0]
Figure 28. Example: Partial Display 33 lines & MUX65
ICONMODE="0"
ICONMODE="1"
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
Column address
SEG
Output
Normal
Direction
Reverse
Direction
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
59H 5AH 5BH 5CH 5DH 5EH 5FH
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display Area (32 +1)
0
Line
Address
COM Output
Normal Reverse
direction direction
COM0
COM63
COM1
COM62
COM2
COM61
COM3
COM60
COM4
COM59
COM5
COM58
COM6
COM57
COM7
COM56
COM8
COM55
COM9
COM54
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM62 COM1
COM63 COM0
COMS0 COMS0
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display Area (33)
D
a
D3 D2 D1 D0 at
Page address
COM Output
Normal Reverse
direction direction
COMS0
COM0
COM1
COM63
COM2
COM62
COM3
COM61
COM4
COM60
COM5
COM59
COM6
COM58
COM7
COM57
COM8
COM56
COM9
COM55
COM10 COM54
COM11 COM53
COM12 COM52
COM13 COM51
COM14 COM50
COM15 COM49
COM16 COM48
COM17 COM47
COM18 COM46
COM19 COM45
COM20 COM44
COM21 COM43
COM22 COM42
COM23 COM41
COM24 COM40
COM25 COM39
COM26 COM38
COM27 COM37
COM28 COM36
COM29 COM35
COM30 COM34
COM31 COM33
COM32 COM32
COM33 COM31
COM34 COM30
COM35 COM29
COM36 COM28
COM37 COM27
COM38 COM26
COM39 COM25
COM40 COM24
COM41 COM23
COM42 COM22
COM43 COM21
COM44 COM20
COM45 COM19
COM46 COM18
COM47 COM17
COM48 COM16
COM49 COM15
COM50 COM14
COM51 COM13
COM52 COM12
COM53 COM11
COM54 COM10
COM55 COM9
COM56 COM8
COM57 COM7
COM58 COM6
COM59 COM5
COM60 COM4
COM61 COM3
COM62 COM2
COM63 COM1
COMS0 COM0
Display start line does not access 65th, 66th, 67th, 68th line
S
E
G
95
S
E
G
0
33/62
STE2007
5 Display Data RAM (DDRAM)
Figure 29. Example: Partial Display 33 lines & MUX68
ICONMODE="1"
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
Column address
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
59H 5AH 5BH 5CH 5DH 5EH 5FH
IL[2:0]
Start
COM Output
Normal Reverse
direction direction
COM66
COM0
COM65
COM1
COM64
COM2
COM3
COM63
COM4
COM62
COM5
COM61
COM6
COM60
COM7
COM59
COM8
COM58
COM9
COM57
COM10 COM56
COM11 COM55
COM12 COM54
COM13 COM53
COM14 COM52
COM15 COM51
COM16 COM50
COM17 COM49
COM18 COM48
COM19 COM47
COM20 COM46
COM21 COM45
COM22 COM44
COM23 COM43
COM24 COM42
COM25 COM41
COM26 COM40
COM27 COM39
COM28 COM38
COM29 COM37
COM30 COM36
COM31 COM35
COM32 COM34
COM33 COM33
COM34 COM32
COM35 COM31
COM36 COM30
COM37 COM29
COM38 COM28
COM39 COM27
COM40 COM26
COM41 COM25
COM42 COM24
COM43 COM23
COM44 COM22
COM45 COM21
COM46 COM20
COM47 COM19
COM48 COM18
COM49 COM17
COM50 COM16
COM51 COM15
COM52 COM14
1
COM53 COM13
COM54 COM12
COM55 COM1
COM56 COM10
COM57 COM9
COM58 COM8
COM59 COM7
COM60 COM6
COM61 COM5
COM62 COM4
COM63 COM3
COM64 COM2
COM65 COM1
COM66 COM0
COMS
COMS
Display start line does not access 65th, 66th, 67th, 68th line
SEG
Output
34/62
Normal
Direction
Reverse
Direction
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
S
E
G
95
S
E
G
0
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display Area (33)
0
D
a
t
a
Partial Display Area (32 +1)
Page address
D3 D2 D1 D0
ICONMODE="0"
COM Output
Normal Reverse
direction direction
COM0
COMS
COM66
COM1
COM65
COM2
COM3
COM64
COM4
COM63
COM5
COM62
COM6
COM61
COM7
COM60
COM8
COM59
COM9
COM58
COM10 COM57
COM11 COM56
COM12 COM55
COM13 COM54
COM14 COM53
COM15 COM52
COM16 COM51
COM17 COM50
COM18 COM49
COM19 COM48
COM20 COM47
COM21 COM46
COM22 COM45
COM23 COM44
COM24 COM43
COM25 COM42
COM26 COM41
COM27 COM40
COM28 COM39
COM29 COM38
COM30 COM37
COM31 COM36
COM32 COM35
COM33 COM34
COM34 COM33
COM35 COM32
COM36 COM31
COM37 COM30
COM38 COM29
COM39 COM28
COM40 COM27
COM41 COM26
COM42 COM25
COM43 COM24
COM44 COM23
COM45 COM22
COM46 COM21
COM47 COM20
COM48 COM19
COM49 COM18
COM50 COM17
COM51 COM16
COM52 COM15
COM53 COM14
COM54 COM13
COM55 COM12
COM56 COM11
COM57 COM10
COM58 COM9
COM59 COM8
COM60 COM7
COM61 COM6
COM62 COM5
COM63 COM4
COM64 COM3
COM65 COM2
COM66 COM1
COM0
COMS
STE2007
5.3.2
5 Display Data RAM (DDRAM)
25 Line Partial Display Mode
Partial Display Area is composed of 25 Lines. Memory vs. Row Drivers Mapping is defined
according to the following parameters:
–
Multiplexing Value
–
IL[2:0]
Figure 30. Example: Partial Display 25 lines & MUX65
ICONMODE="0"
ICONMODE="1"
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Column address
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
59H 5AH 5BH 5CH 5DH 5EH 5FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display Area
(24 +1)
0
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
COM Output
Normal Reverse
direction direction
COM0
COM63
COM1
COM62
COM2
COM61
COM3
COM60
COM4
COM59
COM5
COM58
COM6
COM57
COM7
COM56
COM8
COM55
COM9
COM54
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM62 COM1
COM63 COM0
COM64 COM64
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display Area
(25)
D
a
D3 D2 D1 D0 at
Page address
COM Output
Normal Reverse
direction direction
COM64
COM0
COM1
COM63
COM2
COM62
COM3
COM61
COM4
COM60
COM5
COM59
COM6
COM58
COM7
COM57
COM8
COM56
COM9
COM55
COM10 COM54
COM11 COM53
COM12 COM52
COM13 COM51
COM14 COM50
COM15 COM49
COM16 COM48
COM17 COM47
COM18 COM46
COM19 COM45
COM20 COM44
COM21 COM43
COM22 COM42
COM23 COM41
COM24 COM40
COM25 COM39
COM26 COM38
COM27 COM37
COM28 COM36
COM29 COM35
COM30 COM34
COM31 COM33
COM32 COM32
COM33 COM31
COM34 COM30
COM35 COM29
COM36 COM28
COM37 COM27
COM38 COM26
COM39 COM25
COM40 COM24
COM41 COM23
COM42 COM22
COM43 COM21
COM44 COM20
COM45 COM19
COM46 COM18
COM47 COM17
COM48 COM16
COM49 COM15
COM50 COM14
COM51 COM13
COM52 COM12
COM53 COM11
COM54 COM10
COM55 COM9
COM56 COM8
COM57 COM7
COM58 COM6
COM59 COM5
COM60 COM4
COM61 COM3
COM62 COM2
COM63 COM1
COM64 COM0
Display start line does not access 65th, 66th, 67th, 68th line
IMAGE lOCATION (IL[2:0]) + Partial display Area Width (19hex) <= Multiplexing Rate (40hex)
SEG
Output
Normal
Direction
Reverse
Direction
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
S
E
G
95
S
E
G
0
35/62
STE2007
5 Display Data RAM (DDRAM)
5.3.3
17 Line Partial Display Mode
Partial Display Area is composed of 17 Lines. Memory vs. Row Drivers Mapping is defined
according to the following parameters:
–
Multiplexing Value
–
IL[2:0]
Figure 31. Partial Display 17 Lines
ICONMODE="0"
ICONMODE="1"
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
Column address
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
59H 5AH 5BH 5CH 5DH 5EH 5FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display
Area (16+1)
0
Line
Address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
COM Output
Normal Reverse
direction direction
COM0
COM63
COM1
COM62
COM2
COM61
COM3
COM60
COM4
COM59
COM5
COM58
COM6
COM57
COM7
COM56
COM8
COM55
COM9
COM54
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM62 COM1
COM63 COM0
COM64 COM64
Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11hex) <= Multiplexing Rate (40hex)
SEG
Output
36/62
Normal
Direction
Reverse
Direction
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
S
E
G
95
S
E
G
0
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display
Area (17)
D
a
D3 D2 D1 D0 at
Page address
COM Output
Normal Reverse
direction direction
COM64
COM0
COM1
COM63
COM2
COM62
COM3
COM61
COM4
COM60
COM5
COM59
COM6
COM58
COM7
COM57
COM8
COM56
COM9
COM55
COM10 COM54
COM11 COM53
COM12 COM52
COM13 COM51
COM14 COM50
COM15 COM49
COM16 COM48
COM17 COM47
COM18 COM46
COM19 COM45
COM20 COM44
COM21 COM43
COM22 COM42
COM23 COM41
COM24 COM40
COM25 COM39
COM26 COM38
COM27 COM37
COM28 COM36
COM29 COM35
COM30 COM34
COM31 COM33
COM32 COM32
COM33 COM31
COM34 COM30
COM35 COM29
COM36 COM28
COM37 COM27
COM38 COM26
COM39 COM25
COM40 COM24
COM41 COM23
COM42 COM22
COM43 COM21
COM44 COM20
COM45 COM19
COM46 COM18
COM47 COM17
COM48 COM16
COM49 COM15
COM50 COM14
COM51 COM13
COM52 COM12
COM53 COM11
COM54 COM10
COM55 COM9
COM56 COM8
COM57 COM7
COM58 COM6
COM59 COM5
COM60 COM4
COM61 COM3
COM62 COM2
COM63 COM1
COM64 COM0
STE2007
5.3.4
5 Display Data RAM (DDRAM)
9 Line Partial Display Mode
Partial Display Area is composed of 9 Lines. Memory vs. Row Drivers Mapping is defined
according to the following parameters:
–
Multiplexing Value
–
IL[2:0]
Figure 32. Partial Display 9 Lines
ICONMODE="0"
ICONMODE="1"
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
Column address
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Page 8
00H 01H 02H 03H 04H 05H 06H
59H 5AH 5BH 5CH 5DH 5EH 5FH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display
Area (8+1)
0
Line
Address
COM Output
Normal Reverse
direction direction
COM0
COM63
COM1
COM62
COM2
COM61
COM3
COM60
COM4
COM59
COM5
COM58
COM6
COM57
COM7
COM56
COM8
COM55
COM9
COM54
COM10 COM53
COM11 COM52
COM12 COM51
COM13 COM50
COM14 COM49
COM15 COM48
COM16 COM47
COM17 COM46
COM18 COM45
COM19 COM44
COM20 COM43
COM21 COM42
COM22 COM41
COM23 COM40
COM24 COM39
COM25 COM38
COM26 COM37
COM27 COM36
COM28 COM35
COM29 COM34
COM30 COM33
COM31 COM32
COM32 COM31
COM33 COM30
COM34 COM29
COM35 COM28
COM36 COM27
COM37 COM26
COM38 COM25
COM39 COM24
COM40 COM23
COM41 COM22
COM42 COM21
COM43 COM20
COM44 COM19
COM45 COM18
COM46 COM17
COM47 COM16
COM48 COM15
COM49 COM14
COM50 COM13
COM51 COM12
COM52 COM11
COM53 COM10
COM54 COM9
COM55 COM8
COM56 COM7
COM57 COM6
COM58 COM5
COM59 COM4
COM60 COM3
COM61 COM2
COM62 COM1
COM63 COM0
COM64 COM64
Line
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
IL[2:0]
Start
Partial Display
Area (9)
D
Page address
a
D3 D2 D1 D0 at
COM Output
Normal Reverse
direction direction
COM64
COM0
COM1
COM63
COM2
COM62
COM3
COM61
COM4
COM60
COM5
COM59
COM6
COM58
COM7
COM57
COM8
COM56
COM9
COM55
COM10 COM54
COM11 COM53
COM12 COM52
COM13 COM51
COM14 COM50
COM15 COM49
COM16 COM48
COM17 COM47
COM18 COM46
COM19 COM45
COM20 COM44
COM21 COM43
COM22 COM42
COM23 COM41
COM24 COM40
COM25 COM39
COM26 COM38
COM27 COM37
COM28 COM36
COM29 COM35
COM30 COM34
COM31 COM33
COM32 COM32
COM33 COM31
COM34 COM30
COM35 COM29
COM36 COM28
COM37 COM27
COM38 COM26
COM39 COM25
COM40 COM24
COM41 COM23
COM42 COM22
COM43 COM21
COM44 COM20
COM45 COM19
COM46 COM18
COM47 COM17
COM48 COM16
COM49 COM15
COM50 COM14
COM51 COM13
COM52 COM12
COM53 COM11
COM54 COM10
COM55 COM9
COM56 COM8
COM57 COM7
COM58 COM6
COM59 COM5
COM60 COM4
COM61 COM3
COM62 COM2
COM63 COM1
COM64 COM0
Display start line does not access 65th, 66th, 67th, 68th line
Image Location (1L[2:0]) + Partial display Area Width (11hex) <= Multiplexing Rate (40hex)
SEG
Output
Normal
Direction
Reverse
Direction
S
E
G
0
S
E
G
95
S
E
G
1
S
E
G
94
S
E
G
2
S
E
G
93
S
E
G
3
S
E
G
92
S
E
G
4
S
E
G
91
S
E
G
5
S
E
G
90
S
E
G
6
S
E
G
89
S
E
G
89
S
E
G
6
S
E
G
90
S
E
G
5
S
E
G
91
S
E
G
4
S
E
G
92
S
E
G
3
S
E
G
93
S
E
G
2
S
E
G
94
S
E
G
1
S
E
G
95
S
E
G
0
37/62
STE2007
5 Display Data RAM (DDRAM)
5.4
Command Parameters Default Configuration
Table 17.
STATUS
After Power On
After HW Reset
After SW Reset
Driver Status
MCU TxData–
mode
MCU TxData–
mode
MCU TxData–
mode
Power Saver Mode
Power Saver
Mode
Power Saver
Mode
Power Saver
Mode
DISPLAY MODE
All Pixel On
All Pixel On
All Pixel On
INVERSION
OFF
OFF
OFF
Display
OFF
OFF
OFF
Frame Memory
Random
No Change
No Change
Page Address
0hex
0hex
0hex
Columns Address
0hex
0hex
0hex
Display Start line
0hex
0hex
0hex
Segment drivers Direction
Normal
Normal
Normal
Common Drivers Direction
Normal
Normal
Normal
VOR - Voltage Range
4hex
4hex
4hex
Electronic Volume
90hex
90hex
90hex
Power Control Register
Booster OFF
Booster OFF
Booster OFF
ID byte
0hex
0hex
0hex
Charge Pump
5x
5x
5x
Bias Ratio
1/10
1/10
1/10
VLCD Temeprature Comp.
0ppm
0ppm
0ppm
N-Line Inversion
Frame Inv.
Frame Inv.
Frame Inv.
Multiplexing Rate
1/68
1/68
1/68
Refresh Rate
80Hz
80Hz
80Hz
Image Location
0hex
0hex
0hex
Icon Mode
Disabled
Disabled
Disabled
38/62
Description
IDA/IDB Pads
STE2007
6 Instruction Setups
6
Instruction Setups
6.1
Initialization (Power ON Sequence)
Power ON
Reset status
V0-Voltage Range (**H)
Electronic volume (**H)
Power saver OFF (Display all points OFF (A4H))
Power control set (2FH)
6.2
Display Data Writing Sequence
Page address set (B*H)
Column address set Upper 3-bit address (1*H)
Column address set Lower 4-bit address (0*H)
Display data write
This command is needed only at 1st time after
initialization.
Display ON (AFH)
6.3
Power OFF
Optional Status
!RES Pin="Low Level"
min.20ms
VDD - GND Power OFF
VDDI - GND Power OFF
Power Saver Status or Booster OFF Status
!RES Pin="Low Level" min. 0ms
VDD - GND Power OFF
VDDI - GND Power OFF
39/62
STE2007
7 Power ON/Power OFF timing Sequence
7
Power ON/Power OFF timing Sequence
In Figure 33 is the timing diagram for power on/power down sequences.
Figure 33. Timing for phone’s power on sequence when VDD,VDDCP Up before VDDI
tp1 > 0
tp1 > 0
VDDI
VDD
tpi >0µs
tpi >0µs
Inputs
Outputs
High-Z
High-Z
tcs >0µs
tcs >0µs
!CS
tPWROFF1 >0 ms
tPWROFF2 >20ms
tp2 >0µs
!RES
trs = max. 5µs
INTERNAL
RESET
Trs = max. 5µs
Reset State
Reset State
XCS,SDAIN,XRES can become ”High” simultaneously with VDDI (tcs>0,tpi>0;tp2>0).
trs= max 5000ns (Internal Reset Time- see AC Characteristics Paragraph)
tPWROFF1>0ms must be considered when driver is in Power Saver or Booster OFF status
tPWROFF2>20ms must be considered when driver is in Normal Working Condition
VDDI, VDD and VDD_CP can come up/go down in any sequence
VDDI can be Up with VDD, VDDCP down and viceversa. If only one supply rail is up, the driver
is forced in reset state.
If VDD is high after VDDI all timing referred to VDDI must be referred to VDD (Fig. 24)
Figure 34. Timing for phone’s power on sequence when VDDI Up before VDD
tp1 < 0
tp1 < 0
VDDI
VDD
tpi >0µs
tpi >0µs
SDAIN
SDAOUT
High-Z
High-Z
tcs >0µs
tcs >0µs
!CS
tPWROFF1 >0 ms
tPWROFF2 >20ms
tp2 >0µs
!RES
trs = max. 5µs
INTERNAL
RESET
40/62
Reset State
Trs = max. 5µs
Reset State
STE2007
Table 18.
7 Power ON/Power OFF timing Sequence
Instruction Set
Code
Command
Function
(D/C) D7
D6
D5
D4
D3
D2
D1
D0 Hex
Display ON/OFF
0
1
0
1
0
1
1
1
0
1
AE LCD display
AF 0: OFF, 1: ON
Display normal/
reverse
0
1
0
1
0
0
1
1
0
1
A6 LCD display
A7 0: normal, 1: reverse
Display all points ON/
OFF
0
1
0
1
0
0
1
0
0
1
A4 LCD display
A5 0: normal display, 1: all points ON
Page address set
0
1
0
1
1
Column address set
upper 3–bit address
0
0
0
0
1
Column address set
lower 4–bit address
0
0
0
0
0
Display start line
address set
0
0
1
address
*
Sets the DDRAM page address
address
Sets the DDRAM column address
Segment driver
direction
0
1
0
address
Sets the DDRAM display start line
address
address
1
0
0
0
0
1
0
0
0
1
Sets the correspondence between
A0 the DDRAM column address and
A1 the SEG driver output.
0:Normal, 1: reverse
*
Sets the correspondence between
the DDRAM line address and the
COM driver output.
0: normal, 1: reverse
Common driver
direction select
0
Display data write
1
Self Test/Identification
data reading
0
1
1
0
1
1
Power control set
0
0
0
1
0
1
Operating
mode
Sets the on–chip power supply
circuit operating mode
VO-Range
0
0
0
1
0
0
VO-Range
Sets the electronic volume value
Electronic volume
0
1
0
0
Power saver
–
–
–
–
–
–
–
–
–
Reset
0
1
1
1
0
0
0
1
0
E2 Internal reset
NOP
0
1
1
1
0
0
0
1
1
E3 Non–operation
0
1
1
1
0
0
0
0
1
E1
1
1
0
*
*
Write data
Writes to the DDRAM
0
1
1
DB Identification byte
Electronic volume value
Sets the electronic volume value
Compound command of Display
OFF and Display-all-points-ON
VOP
Sets the VLCD
0
0
VOP[7:0]
0
0
1
1
1
Termal Compensation
0
*
*
*
*
*
0
0
0
38
SET VLCD Slope in temperature
Thermal
Comp
41/62
STE2007
7 Power ON/Power OFF timing Sequence
Table 18.
Instruction Set (continued)
Code
Command
Function
(D/C) D7
D6
D5
D4
D3
D2
D1
D0 Hex
0
0
0
1
1
1
1
0
0
*
*
*
*
*
*
Charge
Pump
0
1
1
1
0
1
1
1
0
*
*
*
*
*
*
Refersh
Rate
0
0
0
1
1
0
Bias Ratio
0
1
0
1
0
1
0
*
*
F1
0
1
1
0
1
0
0
1
0
1
0
1
0
*
*
*
*
*
0
1
1
1
1
1
0
0
Ico
n
0
1
0
1
0
1
0
0
1
0
*
*
*
*
*
*
*
*
A9 Reserved for STM (STM Test
Mode)
STM TEST MODE2
0
1
0
1
0
1
0
1
0
AA
Reserved for STM (STM Test
Mode)
STM TEST MODE3
0
1
0
1
0
1
0
1
1
AB
Reserved for STM (STM Test
Mode)
STM TEST MODE4
0
1
0
1
0
1
0
0
0
A8
Reserved for STM (STM Test
Mode)
STM TEST MODE5
0
1
1
1
1
1
1
1
1
FF
Reserved for STM (STM Test
Mode)
STM TEST MODE6
0
1
1
1
1
1
1
0
0
FC
Reserved for STM (STM Test
Mode)
STM TEST MODE7
0
1
1
1
1
1
1
1
0
FE
Reserved for STM (STM Test
Mode)
STM TEST MODE8
0
1
1
1
1
1
1
0
1
FD
Reserved for STM (STM Test
Mode)
Charge Pump
Refresh Rate
Bias ratio
1
0
1
1
1
3D
Sets the Charge Pump Mux Factor
EF Sets the Display Refresh
Frequency
Sets the VLCD
AD
N-line Inversion
Number of Lines
N-Line Inversion
Mux Rate
1
0
0
Image Location
Icon Mode
IL[2:0]
STM TEST MODE1
* = Disabled bits.
42/62
AC SET Initial Row on Display
STE2007
8 Commands
8
Commands
8.1
Display ON/OFF
This command turns the display ON and OFF
Table 19.
Display ON/OFF
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
1
0
1
0
1
1
1
0
AE
Display OFF
1
AF
Display ON
0
When the Display OFF command is executed in the Display all points ON mode, Power saver
mode is entered. See the section on the Power saver for details.
8.2
Display normal/reverse
This command can reverse the lit and unlit without overwriting the contents of
the DDRAM.
Table 20.
Display normal/reverse
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
1
0
1
0
0
1
1
0
A6
Normal:DDRAM Data ”H”=LCD ON
voltage
1
A7
Reverse:DDRAM Data ”L”=LCD ON
voltage
0
8.3
Display all points ON/OFF
This command makes it possible to force all display points ON regardless of the content of the
DDRAM. Even when this is done, the DDRAM contents are maintained. This command takes
priority over the Display normal/reverse command.
Table 21.
Display all points ON/OFF
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
1
0
1
0
0
1
0
0
A4
Normal Display Mode
1
A5
Display All Points ON
0
When the Display all points ON command is executed when in the Display OFF mode, Power
saver mode is entered. See the section on the Power Saver for details.
43/62
STE2007
8 Commands
8.4
Page address set
This command specifies the page address of the DDRAM.
Specifying the page address and column address enables to access a desired bit of the
DDRAM. After the last column address (5FH), page address is incremented by +1. After the
very last address (column = 5FH, page = 8H), page address return to 0H.
Table 22.
Page address set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
1
0
1
1
0
0
0
0
B0
0H
0
0
0
0
1
B1
1H
0
0
0
1
0
B2
2H
:
:
B8
8H
0
:
0
1
8.5
0
0
0
Column address set
This command specifies the column address of the DDRAM. The column address is split into
two sections (the upper 3–bits and lower 4–bits) when it is set.
Each time the DDRAM is accessed, the column address automatically increments by +1,
imaging it possible for the MCU to continuously access to the display data. After the last column
address (5FH), column address returns to 00H.
Table 23.
Column address set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
0
0
0
1
*
A6
A5
A4
Upper bit address
0
A3
A2
A1
A0
Lower bit address
* Disabled bit
(D/C)
A6
A5
A4
A3
A2
A1
A0
Column address
0
0
0
0
0
0
0
0
00H
0
0
0
0
0
0
0
1
01H
0
0
0
0
0
0
1
0
02H
.
.
.
.
0
1
0
1
1
1
1
0
5EH
0
1
0
1
1
1
1
1
5FH
44/62
STE2007
8.6
8 Commands
Display start line address set
This command is used to specify the display start line address of the DDRAM.
If the display start line address is changed dynamically using this command, then screen
scrolling, page swapping can be performed.
Table 24.
Display start line address set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
0
1
0
0
0
0
0
0
40
0H
0
0
1
0
0
0
0
0
1
41
1H
0
0
1
0
0
0
0
1
0
42
2H
:
:
:
0
0
1
1
1
1
1
1
0
7E
3EH
0
0
1
1
1
1
1
1
1
7F
3FH
Display start line assress con be used in partial dispaly mode to relocate the partial display
window on the screen.
Display start line + Partial Display area with must be smaller or equal to the number of line
selected.
8.7
Segment driver direction select
This command can reverse the correspondence between the DDRAM column address and the
segment driver output.
Table 25.
Segment driver direction select
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
1
0
1
0
0
0
0
0
A0
Normal
0
1
A1
Reverse
8.8
Common driver direction select
This command can reverse the correspondence between the DDRAM line address and the
common driver output.
Table 26.
Common driver direction select
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0
1
1
0
0
0
*
*
*
Normal
1
*
*
*
Reverse
* Disabled bit
45/62
STE2007
8 Commands
8.9
Display data write
This command writes 8–bit data to the specified DDRAM address. Since the column address is
automatically incremented by +1 after each write, the MCU can continuously write multiple–
word data.
Table 27.
Display data write
(D/C)
D7
D6
D5
D4
1
D3
D2
D1
D0
Write Data
8.10
Data reading from driver (Driver TxData–mode)
These commands set SDAOUT to Driver TxData–mode and enable to read the identification
byte.
Table 28.
ID Byte
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Setting
0
1
1
0
1
1
0
1
1
DB
Reads ID byte
0
0
0
IDB
IDA
0
0
0
0
8.11
Pad Default
Power Control Set
This command sets the on–chip power supply function ON/OFF.
Table 29.
Power Control Set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
0
0
0
1
0
1
0
0
0
28
0
0
0
1
29
0
0
1
0
2A
0
0
1
1
2B
0
1
0
0
2C
0
1
0
1
2D
0
1
1
0
2E
0
1
1
1
2F
46/62
Setting
Booster : OFF
Voltage Regulator:OFF
Voltage Follower : OFF
Booster : ON
Voltage regulator : ON
Voltage follower : ON
STE2007
8.12
8 Commands
VLCD set
The LCD Voltage VLCD at reference temperature (TA = 25°C) can be set using the Voltage
Range V0R, Electronic Volume EV and VOP registers content according to the following
formula:
VLCD (T=TA) = ( V0P[7:0] + EV[4:0] - 16 + 32 · V0R[2:0]) · B + VLCDMIN
with the following values:
Symbol
Value
Unit
Note
B
0.04
V
Single Voltage Step
VLCDMIN
3
V
TA
25
°C
Room Temperature
For information on VLCD thermal compensation see PAR. 8.18 .
Figure 35.
Vout
13.20V
EV[3:0]
1Fh
12h
10h
11h
B
00h
VOP[7:0]*B+V-OR
3V
00h
FFh
Figure 36.
V0R[2:0]
EV[4:0]
Thermal
Compensation
DAC
VOUT
Step: 40mV
Range 3V-13.20V
8.12.1 V0R - Voltage Range Set
This command sets a value of the Voltage Range.
Table 30.
V0R – Voltage Range
(D/C)
D7
D6
D5
D4
D3
0
0
0
1
0
0
D2
D1
D0
V0R - Voltage Range
Setting
Command Identifier + Data Field
47/62
STE2007
8 Commands
Table 31.
V0R
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
V0R
Value
32 · V0R · B + VLCDMIN
0
0
0
1
0
0
0
0
0
20
0
3.00 V
0
0
0
1
21
1
4.28 V
0
0
1
0
22
2
5.56 V
0
0
1
1
23
3
6.84 V
0
1
0
0
24
4
8.12 V (Default)
0
1
0
1
25
5
9.40 V
0
1
1
0
26
6
10.68 V
0
1
1
1
27
7
11.96 V
8.12.2 VOP Set
Contrast Setting Adjustment .
Table 32.
VOP Set
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
1
1
1
0
0
0
0
1
E1
Command Identifier
0
VOP7 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0
Table 33.
Data Field
VOP
VOP7 VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0
HEX
VOP Adjustment
0
0
0
0
0
0
0
0
00
0 Step (Default)
0
0
0
0
0
0
0
1
01
+1 Step
0
0
0
0
0
0
1
0
02
+2 Step
:
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1
7F
+127 Step
1
0
0
0
0
0
0
0
80
0 Step
1
0
0
0
0
0
0
1
81
-1 Step
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
0
1
FD
-125 Step
1
1
1
1
1
1
1
0
FE
-126 Step
1
1
1
1
1
1
1
1
FF
-127 Step
48/62
STE2007
8 Commands
8.12.3 Electronic volume
This command sets a value of electronic volume EV for the VLCD voltage regulator, to adjust
the contrast of LCD panel display (End User).
Table 34.
Electronic volume
(D/C)
D7
D6
D5
0
1
0
0
Table 35.
D4
D3
D2
D1
D0
Setting
Electronic Volume Value
Command Identifier + Data Field
EV
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Hex
EV Value
VLCD voltage
0
1
0
0
0
0
0
0
0
80
0 Step
low
0
0
0
0
0
1
81
1 Step
0
0
0
0
1
0
82
2 Step
:
:
90
16 Step (Default)
:
:
:
:
0
1
0
:
0
0
0
:
0
1
1
1
1
0
9E
30 Step
0
1
1
1
1
1
9F
31 Step
8.13
:
:
high
Power saver mode
If the display all points ON command is executed when the display is in display OFF mode,
power saver mode is entered. This mode stops every operation of the LCD display system.
Figure 37. Power saver mode
Power saver (Display OFF & Display all points ON
Power saver mode
Command
Effect
Powersaver OFF (Display all points OFF)
Power saver mode canceled
The internal states in power saver mode are as follows:
–
The oscillation circuit is stopped
–
The LCD power supply circuit is stopped
–
The LCD driver circuit is stopped and segment/common driver outputs to the Vss
level
49/62
STE2007
8 Commands
–
8.14
The display data and operation mode before execution of the Power saver are held,
and the MCU can access to the DDRAM and internal registers.
Reset
When this command is issued, the driver is initialized.This command doesn’t change DDRAM
content.
Table 36.
Reset
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
1
1
1
0
0
0
1
0
E2
Command Identifier
8.15
NOP
Non–operation command.
Table 37.
NOP
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
1
1
1
0
0
0
1
1
E3
Command Identifier
8.16
Image Location
Image Location Command
Table 38.
Image Location
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
1
0
1
0
1
1
0
0
AC
Command Identifier
0
*
*
*
*
*
IL2
IL1
IL0
Table 39.
Data Field
Image Location
IL2
IL1
IL0
Function
0
0
0
0 Lines
0
0
1
8 Lines
0
1
0
16 Lines
0
1
1
24 Lines
1
0
0
32 Lines
1
0
1
48 Lines
1
1
0
56 Lines
1
1
1
64 Lines
50/62
STE2007
8.17
8 Commands
Bias Ratio
It is possible to select different Bias Ratio.
Table 40.
Bias Ratio
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
0
0
1
1
0
BR2
BR1
BR0
Command Identifier + Data Field
Table 41.
BIAS Ratio
BR2
BR1
BR0
Function
0
0
0
Bias Ratio =1/10 - 81 Lines
0
0
1
Bias Ratio = 1/9 - 65 Lines
0
1
0
Bias Ratio =1/8 - 49 Lines
0
1
1
Bias Ratio = 1/7 - 33 Lines
1
0
0
Bias Ratio =1/6 - 25 Lines
1
0
1
Bias Ratio = 1/5 - 17 Lines
1
1
0
Bias Ratio =1/4 - 9 Lines
1
1
1
Not Used
Table 42.
Bias levels Generator
BR=000
BR=001
BR=010
BR=011
VLCD
VLCD
VLCD
VLCD
R
R
R
R
5R
R
R
R
R
VSS
VSS
BR=100
BR=101
BR=110
VLCD
VLCD
VLCD
R
R
3
·VLCD
5
1R
4R
R
1
·VLCD
5
R
VSS
2
·VLCD
4
R
1
·VLCD
6
R
2
·VLCD
4
2
·VLCD
5
2
·VLCD
6
R
3
·VLCD
4
R
4
·VLCD
6
2R
VSS
R
4
·VLCD
5
5
·VLCD
6
R
1
·VLCD
7
1
·VLCD
8
VSS
R
2
·VLCD
7
2
·VLCD
8
1
·VLCD
9
R
R
3R
4R
1
·VLCD
10
5
·VLCD
7
6
·VLCD
8
2
·VLCD
9
R
R
R
7
·VLCD
9
2
·VLCD
10
6
·VLCD
7
7
·VLCD
8
R
8
·VLCD
10
6R
R
R
8
·VLCD
9
9
·VLCD
10
1
·VLCD
4
R
VSS
VSS
51/62
STE2007
8 Commands
8.18
Temperature Compensation
Its is possible to select different VLCD temperature compensation Coefficients.
Table 43.
VLCD Temperature Compensation
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
0
0
1
1
1
0
0
0
38
Command Identifier
0
*
*
*
*
*
Thermal
Compensation
TC
Data Field
Temperature Compensation Formula:
VLCD(T) = VLCD(TA) · [1 + (T(°C) - TA) · TC]
TC = Temperature Compensation Coefficients
T(°C) = Temperature
VLCD(TA) = LCD Voltage at TA Temperature (Room Temperature)
Table 44.
TC
TC2
TC1
TC0
TC Value
0
0
0
TC= 0 PPM
0
0
1
TC= -300 PPM
0
1
0
TC= -600 PPM
0
1
1
TC= -900 PPM
1
0
0
TC= -1070 PPM
1
0
1
TC= -1200 PPM
1
1
0
TC= -1500 PPM
1
1
1
TC= -1800 PPM
8.19
Charge Pump Multiplication Factor
It is possible to select different Charge Pump Multiplication Factors.
Table 45.
Charge Pump Setting
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
0
0
1
1
1
1
0
1
3D
Command Identifier
0
*
*
*
*
*
*
CP1
CP0
52/62
Data Field
STE2007
8 Commands
Table 46.
Charge Pump Multiplication Factor
CP1
CP0
Function
0
0
5x
0
1
4x
1
0
3x
1
1
Not Used
8.20
Refresh Rate
It is possible to select different Refresh Rate.
Table 47.
Refresh Rate
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
1
1
1
0
1
1
1
1
EF
Command Identifier
0
*
*
*
*
*
*
RR1
RR0
Table 48.
Data Field
Refresh Rate
RR1
RR0
Function
0
0
1
1
0
1
0
1
80 Hz
75 Hz
70 Hz
65 hz
8.21
Icon Mode
Icon Mode
Table 49.
–
0: Icon Mode Disabled
–
1: Icon Mode Enabled
Icon Mode
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
1
1
1
1
0
0
ICON
Command Identifier
8.22
N- Line Inversion
N-line Inversion Function.
Table 50.
N-Line Inversion
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
HEX
Function
0
1
0
1
0
1
1
0
1
AD
Command Identifier
0
*
*
F1
NL4
NL3
NL2
NL1
NL0
Data Field
53/62
STE2007
8 Commands
Table 51.
N-Line
F1
NL4
NL3
NL2
NL1
NL0
Function
N row
*
0
0
0
0
0
N-line inversion disabled (default)
0
*
*
*
*
*
XOR function disabled
1
*
*
*
*
*
XOR function enabled
*
0
0
0
0
1
N-line inversion enabled
2
*
0
0
0
1
0
N-line inversion enabled
3
:
:
:
:
:
:
:
:
*
1
1
1
1
1
N-line inversion enabled
32
8.23
The XOR function defines the polarity
as the result of the logical XOR
between the N-Line and the frame
polarity.
Number of Lines
Multiplexing Rate setting command.
Table 52.
Number of Lines
(D/C)
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
1
0
1
0
M2
M1
M0
Command Identifier + Data Field
Table 53.
Multiplexing Rate
M2
M1
M0
Function
0
0
0
68 Lines (Default)
0
0
1
65 Lines
0
1
0
49 Lines
0
1
1
33 Lines
1
0
0
33 Lines Partial Display
1
0
1
25 Lines Partial Display
1
1
0
17 Lines Partial Display
1
1
1
9 Lines Partial Display
54/62
STE2007
9
Table 54.
9 Chip Mechanical Drawing
Chip Mechanical Drawing
Mechanical Dimensions
Parameter
Dimensions
Wafer Thickness
500µm
Die Size (X x Y)
5.92 mm x 1.29 mm
Bumps Size on Columns and Segments Side
28µm X 89 µm X 15
Pad Size on Columns and Segments Side
Bumps Pitch on Columns and Segments Side
Bumps Size on Interfaces Side
Pad Size on Interfaces Side
35µm X 96µm
45µm
55µm X 73µm X 15
64 µm X 82 µm
Bumps Pitch on Interfaces Side
72µm
Spacing between Bumps
17µm
55/62
STE2007
9 Chip Mechanical Drawing
Table 55.
Pad Coordinates
Table 55.
Pad Coordinates (continued)
NAME
PAD
X (µm)
Y(µm)
NAME
PAD
X(µm)
Y(µm)
R16
1
-2632.5
-514.35
C19
29
-1372.5
-514.35
R14
2
-2587.5
-514.35
C20
30
-1327.5
-514.35
R12
3
-2542.5
-514.35
C21
31
-1282.5
-514.35
R10
4
-2497.5
-514.35
C22
32
-1237.5
-514.35
R8
5
-2452.5
-514.35
C23
33
-1192.5
-514.35
R6
6
-2407.5
-514.35
C24
34
-1147.5
-514.35
R4
7
-2362.5
-514.35
C25
35
-1102.5
-514.35
R2
8
-2317.5
-514.35
C26
36
-1057.5
-514.35
R0
9
-2272.5
-514.35
C27
37
-1012.5
-514.35
C0
10
-2227.5
-514.35
C28
38
-967.5
-514.35
C1
11
-2182.5
-514.35
C29
39
-922.5
-514.35
C2
12
-2137.5
-514.35
C30
40
-877.5
-514.35
C3
13
-2092.5
-514.35
C31
41
-832.5
-514.35
C4
14
-2047.5
-514.35
C32
42
-787.5
-514.35
C5
15
-2002.5
-514.35
C33
43
-742.5
-514.35
C6
16
-1957.5
-514.35
C34
44
-697.5
-514.35
C7
17
-1912.5
-514.35
C35
45
-652.5
-514.35
C8
18
-1867.5
-514.35
C36
46
-607.5
-514.35
C9
19
-1822.5
-514.35
C37
47
-562.5
-514.35
C10
20
-1777.5
-514.35
C38
48
-517.5
-514.35
C11
21
-1732.5
-514.35
C39
49
-472.5
-514.35
C12
22
-1687.5
-514.35
C40
50
-427.5
-514.35
C13
23
-1642.5
-514.35
C41
51
-382.5
-514.35
C14
24
-1597.5
-514.35
C42
52
-337.5
-514.35
C15
25
-1552.5
-514.35
C43
53
-292.5
-514.35
C16
26
-1507.5
-514.35
C44
54
-247.5
-514.35
C17
27
-1462.5
-514.35
C45
55
-202.5
-514.35
C18
28
-1417.5
-514.35
C46
56
-157.5
-514.35
56/62
STE2007
Table 55.
9 Chip Mechanical Drawing
Pad Coordinates (continued)
Table 55.
Pad Coordinates (continued)
NAME
PAD
X(µm)
Y(µm)
NAME
PAD
X(µm)
Y(µm)
C47
57
-112.5
-514.35
C75
85
1327.5
-514.35
C48
58
112.5
-514.35
C76
86
1372.5
-514.35
C49
59
157.5
-514.35
C77
87
1417.5
-514.35
C50
60
202.5
-514.35
C78
88
1462.5
-514.35
C51
61
247.5
-514.35
C79
89
1507.5
-514.35
C52
62
292.5
-514.35
C80
90
1552.5
-514.35
C53
63
337.5
-514.35
C81
91
1597.5
-514.35
C54
64
382.5
-514.35
C82
92
1642.5
-514.35
C55
65
427.5
-514.35
C83
93
1687.5
-514.35
C56
66
472.5
-514.35
C84
94
1732.5
-514.35
C57
67
517.5
-514.35
C85
95
1777.5
-514.35
C58
68
562.5
-514.35
C86
96
1822.5
-514.35
C59
69
607.5
-514.35
C87
97
1867.5
-514.35
C60
70
652.5
-514.35
C88
98
1912.5
-514.35
C61
71
697.5
-514.35
C89
99
1957.5
-514.35
C62
72
742.5
-514.35
C90
100
2002.5
-514.35
C63
73
787.5
-514.35
C91
101
2047.5
-514.35
C64
74
832.5
-514.35
C92
102
2092.5
-514.35
C65
75
877.5
-514.35
C93
103
2137.5
-514.35
C66
76
922.5
-514.35
C94
104
2182.5
-514.35
C67
77
967.5
-514.35
C95
105
2227.5
-514.35
C68
78
1012.5
-514.35
R1
106
2272.5
-514.35
C69
79
1057.5
-514.35
R3
107
2317.5
-514.35
C70
80
1102.5
-514.35
R5
108
2362.5
-514.35
C71
81
1147.5
-514.35
R7
109
2407.5
-514.35
C72
82
1192.5
-514.35
R9
110
2452.4
-514.35
C73
83
1237.5
-514.35
R11
111
2497.5
-514.35
C74
84
1282.5
-514.35
R13
112
2542.5
-514.35
57/62
STE2007
9 Chip Mechanical Drawing
Table 55.
Pad Coordinates (continued)
Table 55.
Pad Coordinates (continued)
NAME
PAD
X(µm)
Y(µm)
NAME
PAD
X(µm)
Y(µm)
R15
113
2587.5
-514.35
TEST4
141
2304.0
517.5
R17
114
2632.5
-514.35
VSS_AUX
142
1944.0
517.5
R19
115
2831.85
-450.0
VSS_AUX
143
1872.0
517.5
R21
116
2831.85
-405.0
VSS_AUX
144
1800.0
517.5
R23
117
2831.85
-360.0
VSS_AUX
145
1728.0
517.5
R25
118
2831.85
-315.0
N_RES
146
1584.0
517.5
R27
119
2831.85
-270.0
N_CS
147
1512.0
517.5
R29
120
2831.85
-225.0
T2
148
1368.0
517.5
R31
121
2831.85
-180.0
T1
149
1296.0
517.5
R33
122
2831.85
-135.0
T0
150
1224.0
517.5
R35
123
2831.85
-90.0
VSS
151
1152.0
517.5
R37
124
2831.85
-45.0
VSS
152
1080.0
517.5
R39
125
2831.85
0.0
VSS
153
1008.0
517.5
R41
126
2831.85
45.0
VSS_LCD
154
936.0
517.5
R43
127
2831.85
90.0
VSS_LCD
155
864.0
517.5
R45
128
2831.85
135.0
VSS_LCD
156
792.0
517.5
R47
129
2831.85
180.0
VSS_CP
157
720.0
517.5
R49
130
2831.85
225.0
VSS_CP
158
648.0
517.5
R51
131
2831.85
270.0
VSS_CP
159
576.0
517.5
R53
132
2831.85
315.0
DC
160
432.0
517.5
R55
133
2831.85
360.0
SDAOUT
161
360.0
517.5
R57
134
2831.85
405.0
SDIN
162
288.0
517.5
R59
135
2831.85
450.0
SDOUT
163
216.0
517.5
R61
136
2632.5
514.35
SCLK
164
144.0
517.5
R63
137
2587.5
514.35
VREF_BUFF
165
72.0
517.5
R65
138
2542.0
514.35
VSS_AUX
166
-72.0
517.5
R67
139
2497.5
514.35
SEL1
167
-144.0
517.5
TEST3
140
2376.0
517.5
SEL0
168
-216.0
517.5
58/62
STE2007
Table 55.
9 Chip Mechanical Drawing
Pad Coordinates (continued)
Table 55.
Pad Coordinates (continued)
NAME
PAD
X(µm)
Y(µm)
NAME
PAD
X(µm)
Y(µm)
SA1
169
-288.0
517.5
R62
197
-2587.5
514.35
SA0
170
-360.0
517.5
R60
198
-2632.5
514.35
IDB
171
-432.0
517.5
R58
199
-2831.85
450.0
IDA
172
-504.0
517.5
R56
200
-2831.85
405.0
OSC_IN
173
-576.0
517.5
R54
201
-2831.85
360.0
VDDI
174
-720.0
517.5
R52
202
-2831.85
315.0
VDDI
175
-792.0
517.5
R50
203
-2831.85
270.0
VDDI
176
-864.0
517.5
R48
204
-2831.85
225.0
VDDI
177
-936.0
517.5
R46
205
-2831.85
180.0
VDDI
178
-1008.0
517.5
R44
206
-2831.85
135.0
VDDI
179
-1080.0
517.5
R42
207
-2831.85
90.0
VDD
180
-1224.0
517.5
R40
208
-2831.85
45.0
VDD
181
-1296.0
517.5
R38
209
-2831.85
0.0
VDD
182
-1368.0
517.5
R36
210
-2831.85
-45.0
VDD
183
-1440.0
517.5
R34
211
-2831.85
-90.0
VDD
184
-1512.0
517.5
R32
212
-2831.85
-135.0
VDD
185
-1584.0
517.5
R30
213
-2831.85
-180.0
VDD_CP
186
-1656.0
517.5
R28
214
-2831.85
-225.0
VDD_CP
187
-1728.0
517.5
R26
215
-2831.85
-270.0
VLCD_SNS
188
-1872.0
517.5
R24
216
-2831.85
-315.0
VLCD
189
-1944.0
517.5
R22
217
-2831.85
-360.0
VLCD
190
-2016.0
517.5
R20
218
-2831.85
-405.0
VLCD
191
-2088.0
517.5
R18
219
-2831.85
-450.0
VLCD
192
-2160.0
517.5
TEST4
193
-2304.0
517.5
TEST5
194
-2376.0
517.5
R66
195
-2497.5
514.35
R64
196
-2542.5
514.35
59/62
STE2007
9 Chip Mechanical Drawing
Table 56.
Alignment marks coordinates
MARKS
X
Y
Mark1
-2834.55
517.05
Mark2
2834.55
517.05
Mark3
-2834.55
-517.05
Mark4
2834.55
-517.05
Mark5
2205.0
517.05
60/62
Figure 38. Alignment marks dimensions
35 µm
85 µm
STE2007
10
10 Revision history
Revision history
Date
Revision
9-Nov-2005
1
Changes
Initial release.
61/62
STE2007
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62/62