PSMN3R5-30YL N-channel TrenchMOS logic level FET Rev. 01 — 14 October 2008 Preliminary data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for logic level gate drive sources 1.3 Applications Class-D amplifiers Motor control DC-to-DC converters Server power supplies 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1; Ptot total power dissipation Min Typ Max Unit - - 30 V - - 100 A Tmb = 25 °C; see Figure 2 - - 74 W VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure 14; see Figure 15 - 5 - nC VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 12 - 2.2 3.5 mΩ [1] Dynamic characteristics QGD gate-drain charge Static characteristics RDSon [1] drain-source on-state resistance Continuous current is limited by package. PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G S mbb076 1 2 3 4 SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number Package Name Description PSMN3R5-30YL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads Version SOT669 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 30 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage V ID drain current -20 20 VGS = 10 V; Tmb = 100 °C; see Figure 1; [1] - 79 A VGS = 10 V; Tmb = 25 °C; see Figure 1; [1] - 100 A IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 - 447 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 74 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C - 100 A - 447 A - 54 mJ Source-drain diode IS source current Tmb = 25 °C; ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C [1] Avalanche ruggedness EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 30 V; drain-source avalanche RGS = 50 Ω; unclamped energy [1] Continuous current is limited by package. PSMN3R5-30YL_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 2 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac712 120 ID (A) 100 03aa15 120 Pder (%) (1) 80 80 60 40 40 20 0 0 0 Fig 1. 50 100 150 Tmb (°C) 200 Continuous drain current as a function of mounting base temperature 0 50 100 150 200 Tmb (°C) Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aac731 103 Limit RDSon = VDS / ID ID (A) 102 10 μ s 100 μs 10 DC 1 ms 10 ms 1 100 ms 10-1 10-1 Fig 3. 1 10 VDS (V) 102 Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN3R5-30YL_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 3 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-mb) thermal resistance from see Figure 4 junction to mounting base Min Typ Max Unit - 0.6 1.68 K/W 003aac717 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 δ= P 0.05 tp T 0.02 t tp 10 10-6 Fig 4. T single shot -2 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN3R5-30YL_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 4 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon RG drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 10; see Figure 11 1.3 1.7 2.15 V ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 10 0.65 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10 - - 2.45 V VDS = 30 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 30 V; VGS = 0 V; Tj = 150 °C - - 100 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 15 A; Tj = 25 °C; see Figure 12 - 3.18 5.6 mΩ VGS = 10 V; ID = 15 A; Tj = 150 °C; see Figure 13 - - 6 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 12 - 2.2 3.5 mΩ f = 1 MHz - 0.53 - Ω ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14; see Figure 15 - 19 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 37 - nC ID = 10 A; VDS = 12 V; VGS = 10 V; see Figure 14; see Figure 15 - 41 - nC ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14; see Figure 15 - 6 - nC - 4 - nC drain leakage current gate leakage current drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gate-source charge QGS(th-pl) post-threshold gate-source charge - 2 - nC QGD gate-drain charge - 5 - nC VGS(pl) gate-source plateau voltage VDS = 12 V; see Figure 14; see Figure 15 - 2.4 - V Ciss input capacitance - 2458 - pF Coss output capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 532 - pF Crss reverse transfer capacitance - 252 - pF td(on) turn-on delay time - 33 - ns tr rise time - 50 - ns td(off) turn-off delay time - 45 - ns tf fall time - 18 - ns VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; RG(ext) = 4.7 Ω PSMN3R5-30YL_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 5 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 - 0.88 1.2 V trr reverse recovery time - [tbd] 37 ns Qr recovered charge IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V - [tbd] 31 nC 003aac709 80 003aac710 100 10 ID (A) ID (A) 3 VGS (V) = 4.5 80 60 2.8 60 40 40 2.6 20 2.4 Tj = 150 °C 20 25 °C 2.2 0 0 0 Fig 5. 1 2 0 3 V (V) 4 GS Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aac711 6 Fig 6. 2 4 6 8 10 VDS (V) Output characteristics: drain current as a function of drain-source voltage; typical values 003aac716 4000 Ciss C (pF) RDSon (mΩ) 3000 4 2000 Crss 1000 2 0 2 Fig 7. 4 6 8 VGS (V) 10 Drain-source on-state resistance as a function of gate-source voltage; typical values 0 Fig 8. 4 6 8 10 VGS (V) Input and reverse transfer capacitances as a function of gate-source voltage; typical values PSMN3R5-30YL_1 Preliminary data sheet 2 © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 6 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac718 120 gfs (S) 003aab272 3 VGS(th) (V) 100 max 2 typ 1.5 80 min 1 60 0.5 40 0 10 20 30 40 ID (A) 50 0 -60 0 60 120 180 Tj (°C) 15 Fig 9. Forward transconductance as a function of drain current; typical values 003aab271 10−3 Fig 10. Gate-source threshold voltage as a function of junction temperature 003aac707 6 RDSon (mΩ) ID (A) VGS (V) = 3.2 5 10−4 max typ min 4 4.5 10−5 3 10 10−6 2 0 0.5 1 1.5 2 2.5 VGS (V) Fig 11. Sub-threshold drain current as a function of gate-source voltage 0 40 60 80 I (A) 100 D Fig 12. Drain-source on-state resistance as a function of drain current; typical values PSMN3R5-30YL_1 Preliminary data sheet 20 © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 7 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 003aab273 2 VDS a ID 1.6 VGS(pl) 1.2 VGS(th) VGS 0.8 QGS1 QGS2 QGS 0.4 QGD QG(tot) 003aaa508 0 -60 0 60 120 Tj (°C) 180 Fig 14. Gate charge waveform definitions Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature 003aac715 10 VGS (V) 8 VDS = 12 (V) 3000 C (pF) 2500 2000 VDS = 19 (V) 6 003aac719 Ciss Coss 1500 4 1000 Crss 2 500 0 0 10 20 30 40 50 QG (nC) Fig 15. Gate-source voltage as a function of gate charge; typical values 0 10-1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN3R5-30YL_1 Preliminary data sheet 1 © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 8 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac708 100 IS (A) 80 60 40 Tj = 150 °C 20 0 0.0 25 °C 0.2 0.4 0.6 0.8 1.0 VSD (V) Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN3R5-30YL_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 9 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads A2 A E SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b 1/2 X c e A (A 3) A1 C θ L detail X y C 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 mm b3 b4 2.2 2.0 0.9 0.7 c D (1) c2 D1(1) E(1) E1(1) max 0.25 0.30 4.10 4.20 0.19 0.24 3.80 5.0 4.8 3.3 3.1 e H L L1 L2 w y θ 1.27 6.2 5.8 0.85 0.40 1.3 0.8 1.3 0.8 0.25 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 MO-235 Fig 18. Package outline SOT669 (LFPAK) PSMN3R5-30YL_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 10 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN3R5-30YL_1 20081014 Preliminary data sheet - - PSMN3R5-30YL_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 11 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status [1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PSMN3R5-30YL_1 Preliminary data sheet © NXP B.V. 2008. All rights reserved. Rev. 01 — 14 October 2008 12 of 13 PSMN3R5-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: Rev. 01 — 14 October 2008 Document identifier: PSMN3R5-30YL_1