BF1208D Dual N-channel dual gate MOSFET Rev. 01 — 16 May 2007 Product data sheet 1. Product profile 1.1 General description The BF1208D is a combination of two dual gate MOSFET amplifiers with shared source and gate2 leads and an integrated switch. The integrated switch is operated by the gate1 bias of amplifier B. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross modulation performance during Automatic Gain Control (AGC). Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT666 micro-miniature plastic package. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features n Two low noise gain controlled amplifiers in a single package. One with a fully integrated bias and one with a partly integrated bias n Internal switch to save external components n Superior cross modulation performance during AGC n High forward transfer admittance n High forward transfer admittance to input capacitance ratio 1.3 Applications n Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage u digital and analog television tuners u professional communication equipment BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 1.4 Quick reference data Table 1. Quick reference data Per MOSFET unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit - - 6 VDS drain-source voltage DC ID drain current DC Ptot total power dissipation Tsp ≤ 109 °C |yfs| forward transfer admittance f = 100 MHz; Tj = 25 °C Ciss(G1) input capacitance at gate1 - - 30 mA - - 180 mW amplifier A; ID = 19 mA 26 31 41 mS amplifier B; ID = 15 mA 25 30 40 mS [1] f = 100 MHz amplifier A [2] - 2.1 2.6 pF amplifier B [2] - 2.1 2.6 pF [2] - 30 - fF amplifier A; f = 400 MHz - 0.9 1.5 dB amplifier B; f = 800 MHz - 1.4 2.0 dB Crss reverse transfer capacitance f = 100 MHz NF noise figure Xmod YS = YS(opt) cross modulation input level for k = 1 %; fw = 50 MHz; funw = 60 MHz at 40 dB AGC amplifier A [3] 102 105 - dBµV amplifier B [4] 102 105 - dBµV - - 150 °C junction temperature Tj V [1] Tsp is the temperature at the soldering point of the source lead. [2] Calculated from S-parameters. [3] Measured in Figure 33 test circuit. [4] Measured in Figure 34 test circuit. 2. Pinning information Table 2. Discrete pinning Pin Description 1 gate1 (AMP A) 2 gate2 3 gate1 (AMP B) 4 drain (AMP B) 5 source 6 Simplified outline 6 5 Symbol 4 AMP A G1A DA G2 drain (AMP A) 1 2 S 3 G1B DB AMP B sym089 BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 2 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 3. Ordering information Table 3. Ordering information Type number BF1208D Package Name Description Version - plastic surface-mounted package; 6 leads SOT666 4. Marking Table 4. Marking codes Type number Marking code BF1208D 4A 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per MOSFET VDS drain-source voltage DC - 6 V ID drain current DC - 30 mA IG1 gate1 current - ±10 mA IG2 gate2 current Ptot total power dissipation Tstg Tj [1] - ±10 mA - 180 mW storage temperature −65 +150 °C junction temperature - 150 °C Tsp ≤ 109 °C [1] Tsp is the temperature at the soldering point of the source lead. 001aac193 250 Ptot (mW) 200 150 100 50 0 0 50 100 150 200 Tsp (˚C) Fig 1. Power derating curve BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 3 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point Typ Unit 225 K/W 7. Static characteristics Table 7. Static characteristics Tj = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit amplifier A 6 - - V amplifier B 6 - - V Per MOSFET; unless otherwise specified V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0 V; ID = 10 µA V(BR)G1-SS gate1-source breakdown voltage VG2-S = VDS = 0 V; IG1-S = 10 mA 6 - 10 V V(BR)G2-SS gate2-source breakdown voltage VG1-S = VDS = 0 V; IG2-S = 10 mA 6 - 10 V VF(S-G1) forward source-gate1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 - 1.5 V VF(S-G2) forward source-gate2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 - 1.5 V VG1-S(th) gate1-source threshold voltage VDS = 5 V; VG2-S = 4 V; ID = 100 µA 0.3 - 1.0 V VG2-S(th) gate2-source threshold voltage VDS = 5 V; VG1-S = 5 V; ID = 100 µA 0.4 - 1.0 V IDS drain-source current VG2-S = 4 V; VDS(B) = 5 V; RG1 = 86 kΩ IG1-S IG2-S gate1 cut-off current gate2 cut-off current amplifier A; VDS(A) = 5 V [1] 14 - 24 mA amplifier B [2] 10 - 20 mA amplifier A; VG1-S(A) = 5 V; ID(B) = 0 A - - 50 nA amplifier B; VG1-S(B) = 5 V; VDS(B) = 0 V - - 50 nA - - 20 nA VG2-S = VDS(A) = 0 V VG2-S = 4 V; VG1-S(B) = 0 V; VG1-S(A) = VDS(A) = VDS(B) = 0 V [1] RG1 connects gate1 (B) to VGG = 0 V (see Figure 3). [2] RG1 connects gate1 (B) to VGG = 5 V (see Figure 3). BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 4 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aag356 20 ID (mA) 16 (1) G1A DA (2) 12 G2 S (3) G1B 8 RG1 (4) (5) (6) 4 DB VGG 001aac205 0 0 1 2 3 4 5 VGG (V) (1) ID(B); RG1 = 68 kΩ. VGG = 5 V: amplifier A is off; amplifier B is on. (2) ID(B); RG1 = 86 kΩ. VGG = 0 V: amplifier A is on; amplifier B is off. (3) ID(B); RG1 = 100 kΩ. (4) ID(A); RG1 = 100 kΩ. (5) ID(A); RG1 = 86 kΩ. (6) ID(A); RG1 = 68 kΩ. Fig 2. Drain currents of MOSFET A and B as a function of VGG Fig 3. Functional diagram 8. Dynamic characteristics 8.1 Dynamic characteristics for amplifier A Table 8. Dynamic characteristics for amplifier A[1] Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA; unless otherwise specified. Symbol Parameter Conditions |yfs| forward transfer admittance f = 100 MHz; Tj = 25 °C Min Typ Max Unit 26 31 41 mS Ciss(G1) input capacitance at gate1 f = 100 MHz [2] - 2.1 2.6 pF Ciss(G2) input capacitance at gate2 f = 100 MHz [2] - 3.4 - pF f = 100 MHz [2] - 0.8 - pF [2] - 30 - fF f = 200 MHz; GS = 2 mS; GL = 0.5 mS 32 36 40 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 28 32 36 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 24 28 33 dB Coss output capacitance Crss reverse transfer capacitance f = 100 MHz Gtr transducer power gain BS = BS(opt); BL = BL(opt) NF noise figure f = 11 MHz; GS = 20 mS; BS = 0 S - 3.0 - dB f = 400 MHz; YS = YS(opt) - 0.9 1.5 dB f = 800 MHz; YS = YS(opt) - 1.1 1.7 dB BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 5 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET Table 8. Dynamic characteristics for amplifier A[1] …continued Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 19 mA; unless otherwise specified. Symbol Parameter Xmod Conditions cross modulation Min Typ Max Unit at 0 dB AGC 90 - - dBµV at 10 dB AGC - 90 - dBµV at 20 dB AGC - 99 - dBµV at 40 dB AGC 102 105 - dBµV [3] input level for k = 1 %; fw = 50 MHz; funw = 60 MHz [1] For the MOSFET not in use: VG1-S(B) = 0 V; VDS(B) = 0 V. [2] Calculated from S-parameters. [3] Measured in Figure 33 test circuit. 8.1.1 Graphics for amplifier A 001aaa554 30 001aaa555 32 (1) ID (mA) (2) ID (mA) (3) (1) (2) (4) 24 (3) 20 (4) (5) 16 (5) (6) 10 (7) (6) 8 (8) (9) (7) 0 0 0 0.4 0.8 1.2 1.6 2 VG1-S (V) 0 4 6 VDS (V) (1) VG2-S = 4 V. (1) VG1-S(A) = 1.8 V. (2) VG2-S = 3.5 V. (2) VG1-S(A) = 1.7 V. (3) VG2-S = 3 V. (3) VG1-S(A) = 1.6 V. (4) VG2-S = 2.5 V. (4) VG1-S(A) = 1.5 V. (5) VG2-S = 2 V. (5) VG1-S(A) = 1.4 V. (6) VG2-S = 1.5 V. (6) VG1-S(A) = 1.3 V. (7) VG2-S = 1 V. (7) VG1-S(A) = 1.2 V. VDS(A) = 5 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 °C. 2 (8) VG1-S(A) = 1.1 V. (9) VG1-S(A) = 1 V. VG2-S = 4 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 °C. Fig 4. Amplifier A: transfer characteristics; typical values Fig 5. Amplifier A: output characteristics; typical values BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 6 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aaa556 40 yfs (mS) ID(A) (mA) 16 (1) (2) 30 001aac206 20 12 20 (3) 8 (4) 10 4 (5) (6) 0 0 0 8 16 24 32 0 (1) VG2-S = 4 V. 20 40 60 ID(B) (µA) ID (mA) VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 5 V; VG1-S(B) = 0 V; Tj = 25 °C. (2) VG2-S = 3.5 V. ID(B) = internal gate1 current = current in pin drain (AMP B) if MOSFET (B) is switched off. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. VDS(A) = 5 V; VG1-S(B) = VDS(B) = 0 V; Tj = 25 °C. Fig 6. Amplifier A: forward transfer admittance as a function of drain current; typical values Fig 7. Amplifier A: drain current as a function of internal gate1 current; typical values BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 7 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aaa558 20 001aaa559 32 ID (mA) 16 ID (mA) 24 (1) 12 (2) (3) 16 (4) (5) 8 (6) 8 4 0 0 0 1 2 3 4 5 0 2 4 Vsup (V) 6 VG2-S (V) VDS(A) = VDS(B) = Vsup; VG2-S = 4 V; Tj = 25 °C; RG1 = 86 kΩ (connected to ground); see Figure 3. (1) VDS(B) = 5 V. (2) VDS(B) = 4.5 V. (3) VDS(B) = 4 V. (4) VDS(B) = 3.5 V. (5) VDS(B) = 3 V. (6) VDS(B) = 2.5 V. VDS(A) = 5 V; VG1-S(B) = 0 V; gate1 (AMP A) is open; Tj = 25 °C. Fig 8. Amplifier A: drain current of amplifier A as a function of supply voltage of A and B amplifier; typical values 001aac195 120 Fig 9. Amplifier A: drain current as a function of gate2 voltage; typical values 001aac196 0 gain reduction (dB) 10 Vunw (dBµV) 110 20 100 30 90 40 80 50 0 10 20 30 40 50 gain reduction (dB) VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C; see Figure 33. Fig 10. Amplifier A: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values 0 2 3 4 VAGC (V) VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; f = 50 MHz; see Figure 33. Fig 11. Amplifier A: gain reduction as a function of AGC voltage; typical values BF1208D_1 Product data sheet 1 © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 8 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aac197 28 001aag357 102 bis, gis (mS) ID (mA) 10 20 bis 1 12 gis 10−1 10−2 4 0 10 20 30 40 50 gain reduction (dB) 10 001aag358 102 ϕfs (deg) Yfs Yfs (mS) −102 −10 10 103 f (MHz) VDS(A) = VDS(B) = 5 V; VG1-S(B) = 0 V; f = 50 MHz; Tamb = 25 °C; see Figure 33. Fig 12. Amplifier A: drain current as a function of gain reduction; typical values 102 VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA Fig 13. Amplifier A: input admittance as a function of frequency; typical values 001aag359 103 −103 ϕrs (deg) Yrs (µS) ϕrs 102 −102 ϕfs Yrs 1 10−1 10 102 f (MHz) −1 10 −10−1 103 1 −10 10 102 f (MHz) −1 103 VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA Fig 14. Amplifier A: forward transfer admittance and phase as a function of frequency; typical values Fig 15. Amplifier A: reverse transfer admittance and phase as a function of frequency; typical values BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 9 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aag360 10 bos, gos (mS) 1 bos 10−1 gos 10−2 102 10 f (MHz) 103 VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = VG1-S(B) = 0 V; ID(A) = 19 mA Fig 16. Amplifier A: output admittance as a function of frequency; typical values 8.1.2 Scattering parameters for amplifier A Table 9. Scattering parameters for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 19 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 °C; typical values. f (MHz) s11 Magnitude (ratio) Angle (deg) s21 40 0.992 −3.037 3.21 100 0.99152 −7.62 200 0.98685 300 0.97979 400 s12 Magnitude (ratio) Angle (deg) s22 Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) 177.04 0.00763 87.34 0.992 −1.139 3.13270 172.06 0.00182 85.21 0.99168 −2.93 −15.12 3.11006 164.12 0.00350 78.32 0.99047 −5.83 −22.49 3.06743 156.24 0.00511 73.45 0.98876 −8.72 0.97176 −29.74 3.01634 148.56 0.00664 69.12 0.98662 −11.57 500 0.96209 −36.76 2.95125 141.00 0.00805 64.73 0.98424 −14.39 600 0.95108 −43.63 2.87828 133.56 0.00931 60.38 0.98168 −17.21 700 0.93915 −50.35 2.79946 126.28 0.01042 56.16 0.97884 −19.97 800 0.92742 −56.82 2.71508 119.20 0.01141 52.16 0.97630 −22.68 900 0.91573 −62.95 2.62937 112.29 0.01224 48.31 0.97350 −25.42 1000 0.90429 −68.83 2.54239 105.56 0.01297 44.63 0.97115 −28.14 8.1.3 Noise data for amplifier A Table 10. Noise data for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 19 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 °C; typical values; unless otherwise specified. f (MHz) NFmin (dB) Γopt (ratio) (deg) 400 0.9 0.77 22.7 0.65 800 1.1 0.73 45.75 0.62 BF1208D_1 Product data sheet rn (ratio) © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 10 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 8.2 Dynamic characteristics for amplifier B Table 11. Dynamic characteristics for amplifier B[1] Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. Symbol Parameter Conditions |yfs| f = 100 MHz; Tj = 25 °C forward transfer admittance Min Typ Max Unit 25 30 40 mS Ciss(G1) input capacitance at gate1 f = 100 MHz [2] - 2.1 2.6 pF Ciss(G2) input capacitance at gate2 f = 100 MHz [2] - 3.4 - pF f = 100 MHz [2] - 0.85 - pF [2] - 30 - fF f = 200 MHz; GS = 2 mS; GL = 0.5 mS 31 35 39 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 28 32 36 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 26 30 34 dB f = 11 MHz; GS = 20 mS; BS = 0 S - 3 - dB f = 400 MHz; YS = YS(opt) - 1.1 1.7 dB - 1.4 2.0 dB at 0 dB AGC 90 - - dBµV at 10 dB AGC - 90 - dBµV at 20 dB AGC - 98 - dBµV at 40 dB AGC 102 105 - dBµV Coss output capacitance Crss reverse transfer capacitance f = 100 MHz Gtr transducer power gain BS = BS(opt); BL = BL(opt) NF noise figure f = 800 MHz; YS = YS(opt) Xmod cross modulation input level for k = 1 %; fw = 50 MHz; funw = 60 MHz [1] For the MOSFET not in use: VG1-S(A) = 0 V; VDS(A) = 0 V. [2] Calculated from S-parameters. [3] Measured in Figure 34 test circuit. BF1208D_1 Product data sheet [3] © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 11 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 8.2.1 Graphics for amplifier B 001aag361 30 (1) (2) (3) ID (mA) 001aag362 24 (1) ID (mA) (4) 20 (2) 16 (3) (5) (4) (5) 10 8 (6) (6) (7) (7) 0 0 0 0.4 0.8 1.2 1.6 2.0 VG1-S (V) 0 (1) VG1-S(B) = 1.6 V. (2) VG2-S = 3.5 V. (2) VG1-S(B) = 1.5 V. (3) VG2-S = 3 V. (3) VG1-S(B) = 1.4 V. (4) VG2-S = 2.5 V. (4) VG1-S(B) = 1.3 V. (5) VG2-S = 2 V. (5) VG1-S(B) = 1.2 V. (6) VG2-S = 1.5 V. (6) VG1-S(B) = 1.1 V. (7) VG2-S = 1 V. (7) VG1-S(B) = 1 V. Fig 17. Amplifier B: transfer characteristics; typical values 6 VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. Fig 18. Amplifier B: output characteristics; typical values BF1208D_1 Product data sheet 4 VDS (V) (1) VG2-S = 4 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. 2 © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 12 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aag363 100 IG1 (µA) 001aag364 40 Yfs (mS) (1) 80 (1) 32 (2) (2) (3) 60 (3) 24 40 (4) 16 (4) (5) (5) 20 8 (6) (6) (7) (7) 0 0 0 0.4 0.8 1.2 1.6 2.0 VG1-S (V) 0 8 (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (7) VG2-S = 1 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. 001aag365 20 24 32 ID (mA) (1) VG2-S = 4 V. Fig 19. Amplifier B: gate1 current as a function of gate1 voltage; typical values 16 VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. Fig 20. Amplifier B: forward transfer admittance as a function of drain current; typical values 001aag366 20 ID (mA) ID (mA) 16 16 12 12 8 8 4 4 0 0 0 10 20 30 40 50 IG1 (µA) 0 1 2 3 4 5 VGG (V) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C. VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C; RG1 = 86 kΩ (connected to VGG); see Figure 3. Fig 21. Amplifier B: drain current as a function of gate1 current; typical values Fig 22. Amplifier B: drain current as a function of gate1 supply voltage; typical values BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 13 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aag367 25 ID (mA) ID (mA) (1) 20 (2) 10 (1) 16 (3) (4) (5) (6) (7) (8) (9) 15 001aag368 24 (2) (3) (4) (5) 8 5 0 0 0 1 2 3 4 5 VGG = VDS (V) 0 2 4 6 VG2-S (V) (1) RG1 = 47 kΩ. (1) VGG = 5.0 V. (2) RG1 = 56 kΩ. (2) VGG = 4.5 V. (3) RG1 = 68 kΩ. (3) VGG = 4.0 V. (4) RG1 = 82 kΩ. (4) VGG = 3.5 V. (5) RG1 = 86 kΩ. (5) VGG = 3.0 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C; RG1 = 86 kΩ (connected to VGG); see Figure 3. (6) RG1 = 100 kΩ. (7) RG1 = 120 kΩ. (8) RG1 = 150 kΩ. (9) RG1 = 180 kΩ. VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C; RG1 is connected to VGG; see Figure 3. Fig 23. Amplifier B: drain current as a function of gate1 supply voltage and drain supply voltage; typical values Fig 24. Amplifier B: drain current as a function of gate2 voltage; typical values BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 14 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aag369 50 IG1 (µA) 001aag370 120 (1) Vunw (dBµV) (2) 110 40 (3) 30 (4) 100 (5) 20 90 10 0 80 0 2 4 6 0 20 VG2-S (V) (1) VGG = 5.0 V. 40 60 gain reduction (dB) VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 86 kΩ (connected to VGG); fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C; see Figure 34. (2) VGG = 4.5 V. (3) VGG = 4.0 V. (4) VGG = 3.5 V. (5) VGG = 3.0 V. VDS(B) = 5 V; VDS(A) = VG1-S(A) = 0 V; Tj = 25 °C; RG1 = 86 kΩ (connected to VGG); see Figure 3. Fig 25. Amplifier B: gate1 current as a function of gate2 voltage; typical values 001aag371 0 gain reduction (dB) 10 Fig 26. Amplifier B: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values 001aag372 24 ID (mA) 18 20 12 30 6 40 0 50 0 1 2 3 4 0 VAGC (V) VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 86 kΩ (connected to VGG); f = 50 MHz; Tamb = 25 °C; see Figure 34. Fig 27. Amplifier B: gain reduction as a function of AGC voltage; typical values 40 60 gain reduction (dB) VDS(B) = 5 V; VGG = 5 V; VDS(A) = VG1-S(A) = 0 V; RG1 = 86 kΩ (connected to VGG); f = 50 MHz; Tamb = 25 °C; see Figure 34. Fig 28. Amplifier B: drain current as a function of gain reduction; typical values BF1208D_1 Product data sheet 20 © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 15 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 001aag373 102 001aag374 102 bis, gis (mS) Yfs (mS) −102 ϕfs (deg) Yfs 10 −10 10 bis ϕfs 1 gis 10−1 10 102 f (MHz) 103 Fig 29. Amplifier B: input admittance as a function of frequency; typical values 001aag375 −103 ϕrs (deg) Yrs (µS) ϕrs 102 10 102 f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 15 mA 103 −1 103 1 −102 VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 15 mA Fig 30. Amplifier B: forward transfer admittance and phase as a function of frequency; typical values 001aag376 10 bos, gos (mS) 1 bos 10−1 gos Yrs −10 10 1 10 102 f (MHz) −1 103 10−2 10 102 f (MHz) 103 VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 15 mA VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = VG1-S(A) = 0 V; ID(B) = 15 mA Fig 31. Amplifier B: reverse transfer admittance and phase as a function of frequency; typical values Fig 32. Amplifier B: output admittance as a function of frequency; typical values BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 16 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 8.2.2 Scattering parameters for amplifier B Table 12. Scattering parameters for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 15 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 °C; typical values. f (MHz) s11 s21 s12 Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) 40 0.9830 −3.09 2.96410 100 0.98257 −7.62 200 300 s22 Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) 176.88 0.00070 87.02 0.9920 −1.22 2.92951 171.69 0.00176 86.41 0.99190 −3.22 0.97956 −15.00 2.90869 163.43 0.00339 83.66 0.99064 −6.42 0.97446 −22.33 2.86877 155.20 0.00501 81.33 0.98894 −9.59 400 0.96849 −29.56 2.82073 147.13 0.00663 79.12 0.98688 −12.74 500 0.96112 −36.62 2.75891 139.15 0.00820 76.85 0.98454 −15.88 600 0.95238 −43.55 2.68790 131.26 0.00967 74.48 0.98181 −19.02 700 0.94282 −50.37 2.61038 123.50 0.01110 72.29 0.97880 −22.13 800 0.93319 −56.94 2.52719 115.92 0.01250 70.11 0.97585 −25.20 900 0.92326 −63.22 2.44054 108.46 0.01379 67.93 0.97175 −28.30 1000 0.91325 −69.31 2.35036 101.13 0.01506 65.65 0.96801 −31.40 8.2.3 Noise data for amplifier B Table 13. Noise data for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 15 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 °C; typical values; unless otherwise specified. f (MHz) NFmin (dB) Γopt (ratio) (deg) 400 1.1 0.72 22.83 0.66 800 1.4 0.68 46.42 0.64 BF1208D_1 Product data sheet rn (Ω) © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 17 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 9. Test information VDS(A) VAGC 5V 4.7 nF 10 kΩ 4.7 nF RGEN 50 Ω G2 4.7 nF Vi BF1208D G1B 50 Ω 4.7 nF DA G1A 4.7 nF 50 Ω L1 2.2 µH RL 50 Ω S DB L2 2.2 µH RG1 4.7 nF VGG VDS(B) 0V 5V 001aag398 Fig 33. Cross modulation test set-up for amplifier A VDS(A) VAGC 5V 4.7 nF 10 kΩ 4.7 nF 50 Ω DA G1A 4.7 nF G2 4.7 nF RGEN 50 Ω L1 2.2 µH BF1208D G1B 50 Ω S 4.7 nF DB L2 2.2 µH RG1 RL 50 Ω 4.7 nF Vi VGG 5V VDS(B) 5V 001aag399 Fig 34. Cross modulation test set-up for amplifier B BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 18 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 10. Package outline Plastic surface-mounted package; 6 leads SOT666 D E A X Y S S HE 6 5 4 pin 1 index A 1 2 e1 c 3 bp w M A Lp e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A bp c D E e e1 HE Lp w y mm 0.6 0.5 0.27 0.17 0.18 0.08 1.7 1.5 1.3 1.1 1.0 0.5 1.7 1.5 0.3 0.1 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 SOT666 Fig 35. Package outline SOT666 BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 19 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 11. Abbreviations Table 14. Abbreviations Acronym Description AGC Automatic Gain Control DC Direct Current MOSFET Metal-Oxide Semiconductor Field-Effect Transistor UHF Ultra High Frequency VHF Very High Frequency 12. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes BF1208D_1 20070516 Product data sheet - - BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 20 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] BF1208D_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 16 May 2007 21 of 22 BF1208D NXP Semiconductors Dual N-channel dual gate MOSFET 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.1.3 8.2 8.2.1 8.2.2 8.2.3 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics for amplifier A. . . . . . . 5 Graphics for amplifier A . . . . . . . . . . . . . . . . . . 6 Scattering parameters for amplifier A . . . . . . . 10 Noise data for amplifier A . . . . . . . . . . . . . . . . 10 Dynamic characteristics for amplifier B. . . . . . 11 Graphics for amplifier B . . . . . . . . . . . . . . . . . 12 Scattering parameters for amplifier B . . . . . . . 17 Noise data for amplifier B . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 May 2007 Document identifier: BF1208D_1