DISCRETE SEMICONDUCTORS DATA SHEET andbook, halfpage MBD128 BF1206 Dual N-channel dual-gate MOS-FET Product specification 2003 Nov 17 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET FEATURES BF1206 PINNING - SOT363 • Two low noise gain controlled amplifiers in a single package PIN • Superior cross-modulation performance during AGC • High forward transfer admittance • High forward transfer admittance to input capacitance ratio. APPLICATIONS • Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage, such as digital and analog television tuners. DESCRIPTION 1 drain (b) 2 source 3 gate 1 (b) 4 gate 1 (a) 5 gate 2 6 drain (a) d (a) handbook, halfpage 6 5 g2 g1 (a) 4 DESCRIPTION AMP a The BF1206 is a combination of two different dual gate MOS-FET amplifiers with shared source and gate 2 leads. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor is encapsulated in SOT363 micro-miniature plastic package. AMP b 1 2 3 Top view d (b) s g1 (b) MAM480 Marking code: L6-. Fig.1 Simplified outline and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Per MOS-FET; unless otherwise specified VDS drain-source voltage − − 6 V ID drain current (DC) − − 30 mA yfs forward transfer admittance 33 38 48 mS Cig1-s input capacitance at gate 1 amp. a: ID = 18 mA amp. b: ID = 12 mA 29 34 44 mS amp. a: ID = 18 mA; f = 1 MHz − 2.4 2.9 pF amp. b: ID = 12 mA; f = 1 MHz − 1.7 2.2 pF Crss reverse transfer capacitance f = 1 MHz − 15 − fF Xmod cross-modulation amp. a: input level for k = 1% at 40 dB AGC 102 105 − dBµV amp. b: input level for k = 1% at 40 dB AGC 100 103 − dBµV NF 2003 Nov 17 noise figure amp. a: f = 400 MHz; ID = 18 mA − 1.3 1.9 dB amp. b: f = 800 MHz; ID = 12 mA − 1.4 2.0 dB amp. a: f = 11 MHz; ID = 18 mA − 3 − dB amp. b: f = 11 MHz; ID = 12 mA − 3.5 − dB 2 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME − BF1206 DESCRIPTION VERSION plastic surface mounted package; 6 leads SOT363 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per MOS-FET; unless otherwise specified VDS drain-source voltage − 6 V ID drain current (DC) − 30 mA IG1 gate 1 current − ±10 mA IG2 gate 2 current − ±10 mA Ptot total power dissipation − 180 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Ts ≤ 107 °C; note 1 Note 1. Ts is the temperature at the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s 2003 Nov 17 PARAMETER thermal resistance from junction to soldering point 3 VALUE UNIT 240 K/W Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE257 200 handbook, halfpage Ptot (mW) 150 100 50 0 0 50 100 150 Ts (°C) 200 Fig.2 Power derating curve. STATIC CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per MOS-FET unless otherwise specified V(BR)DSS drain-source breakdown voltage VG1-S = VG2-S = 0; ID = 10 µA 6 − V V(BR)G1-SS gate-source breakdown voltage VGS = VDS = 0; IG1-S = 10 mA 6 10 V V(BR)G2-SS gate-source breakdown voltage VGS = VDS = 0; IG2-S = 10 mA 6 10 V V(F)S-G1 forward source-gate voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate-source threshold voltage VDS = 5 V; VG2-S = 4 V; ID = 100 µA 0.3 1 V VG2-S(th) gate-source threshold voltage VDS = 5 V; VG1-S = 5 V; ID = 100 µA 0.35 1 V IDSX drain-source current amp. a: VG2-S = 4 V; VDS = 5 V; RG = 91 kΩ; note 1 14 23 mA amp. b: 9 VG2-S = 4 V; VDS = 5 V; RG = 150 kΩ; note 1 17 mA IG1-S gate cut-off current VG1-S = 5 V; VG2-S = VDS = 0 − 50 nA IG2-S gate cut-off current VG2-S = 5 V; VG1-S = VDS = 0 − 20 nA Note 1. RG1 connects gate 1 to VGG = 5 V. 2003 Nov 17 4 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 DYNAMIC CHARACTERISTICS AMPLIFIER a Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 18 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj = 25 °C 33 38 48 mS Cig1-ss input capacitance at gate 1 f = 1 MHz − 2.4 2.9 pF Cig2-ss input capacitance at gate 2 f = 1 MHz − 3.2 − pF Coss output capacitance f = 1 MHz − 1.1 − pF Crss reverse transfer capacitance f = 1 MHz − 15 30 fF NF noise figure f = 11 MHz; GS = 20 mS; BS = 0 − 3 − dB f = 400 MHz; YS = YS opt − 1.3 1.9 dB f = 800 MHz; YS = YS opt − 1.6 2.2 dB f = 200 MHz; GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt; note 1 − 35 − dB f = 400 MHz; GS = 2 mS; BS = BS opt; GL = 1 mS; BL = BL opt; note 1 − 30 − dB f = 800 MHz; GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt; note 1 − 23 − dB Gtr Xmod power gain cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 2 at 0 dB AGC 90 − − dBµV at 10 dB AGC − 92 − dBµV at 40 dB AGC 102 105 − dBµV Notes 1. Calculated from measured s-parameters. 2. Measured in Fig.35 test circuit. 2003 Nov 17 5 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 GRAPHS FOR AMPLIFIER a MLE258 30 handbook, halfpage ID (2) (mA) (3) MLE259 32 handbook, halfpage (1) (4) (5) ID (mA) (1) 24 (2) 20 (3) (4) 16 (6) (5) 10 (6) 8 (7) 0 (7) 0 0 0.5 1 1.5 2 0 2 VG1-S (V) VDS = 5 V; Tj = 25 °C. (1) (2) (3) (4) VG2-S = 4 V. VG2-S = 3.5 V. VG2-S = 3 V. VG2-S = 2.5 V. Fig.3 VDS (V) 6 VG2-S = 4 V; Tj = 25 °C. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (1) VG1-S = 1.5 V. (2) VG1-S = 1.4 V. (3) VG1-S = 1.3 V. (4) VG1-S = 1.2 V. Transfer characteristics; typical values; amplifier a. 2003 Nov 17 4 Fig.4 6 (5) VG1-S = 1.1 V. (6) VG1-S = 1 V. (7) VG1-S = 0.9 V. Output characteristics; typical values; amplifier a. Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE260 100 IG1 handbook, halfpage (1) yfs (mS) (µA) 80 MLE261 50 handbook, halfpage (2) (3) (2) 40 (3) (1) (4) (4) 30 60 (5) (5) 20 40 (6) (6) (7) 1 20 (7) 0 0 0 0.5 1 0 1.5 2 VG1-S (V) 20 ID(mA) 30 VDS = 5 V; Tj = 25 °C. VDS = 5 V; Tj = 25 °C. (1) VG2-S = 4 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. Fig.5 10 Gate 1 current as a function of gate 1 voltage; typical values; amplifier a. (5) VG2-S = 2 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. Fig.6 MLE262 24 (1) VG2-S = 4 V. Forward transfer admittance as a function of drain current; typical values; amplifier a. MLE263 20 handbook, halfpage handbook, halfpage ID (mA) ID 16 (mA) 16 12 8 8 4 0 0 0 10 20 30 40 50 IG1 (µA) 0 1 2 3 5 VGG (V) VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. RG1 = 91 kΩ (connected to VGG); see Fig.35. Fig.7 Fig.8 Drain current as a function of gate 1 current; typical values; amplifier a. 2003 Nov 17 4 7 Drain current as a function of gate 1 supply voltage (VGG); typical values; amplifier a. Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE288 40 ID MLE292 20 (1) handbook, halfpage handbook, halfpage (mA) ID (mA) (1) (2) 16 32 (3) (2) (4) (3) (4) (5) 24 (5) 12 (6) (7) 16 8 4 8 0 0 0 2 3 6 0 8 VGG = VDS (V) 2 4 VG2-S(V) 6 VG2-S = 4 V; Tj = 25 °C; RG1 = 150 kΩ (connected to VGG); see Fig.35. (1) (2) (3) (4) RG1 = 56 kΩ. RG1 = 68 kΩ. RG1 = 82 kΩ. RG1 = 91 kΩ. Fig.9 VDS = 5 V; Tj = 25 °C; RG1 = 91 kΩ (connected to VGG); see Fig.35. (5) RG1 = 100 kΩ. (6) RG1 = 120 kΩ. (7) RG1 = 150 kΩ. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. Drain current as a function of gate 1 (VGG) and drain supply voltage; typical values; amplifier a. 2003 Nov 17 (4) VGG = 3.5 V. (5) VGG = 3 V. Fig.10 Drain current as a function of gate 2 voltage; typical values; amplifier a. 8 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE264 50 MLE266 120 handbook, halfpage handbook, halfpage IG1 (µA) 40 (1) Vunw (dBµV) (2) 110 (3) 30 (4) 100 (5) 20 90 1 0 80 0 4 2 VG2-S(V) 6 0 10 20 30 40 50 gain reduction (dB) VDS 5 V; Tj = 25 °C. RG1 = 91 kΩ (connected to VGG); see Fig.35. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. (4) VGG = 3.5 V. VDS = 5 V; VGG = 5 V; RG1 = 91 kΩ; f = 50 MHz; f unw = 60 MHz; Tamb = 25 °C; see Fig.35. (5) VGG = 3 V. Fig.12 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier a. Fig.11 Gate 1 current as a function of gate 2 voltage; typical values; amplifier a. MLE265 0 MLE267 24 handbook, gain halfpage handbook, halfpage reduction (dB) −10 ID (mA) 16 −20 −30 8 −40 −50 0 0 1 2 4 3 0 VAGC (V) 10 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 91 kΩ; f = 50 MHz; Tamb = 25 °C; see Fig.35. VDS = 5 V; VGG = 5 V; RG1 = 91 kΩ; f = 50 MHz; Tamb = 25 °C; see Fig.35. Fig.13 Typical gain reduction as a function of AGC voltage; typical values; amplifier a. Fig.14 Drain current as a function of gain reduction; typical values; amplifier a. 2003 Nov 17 9 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE268 102 handbook, halfpage MLE269 103 handbook, halfpage ϕrs (deg) yrs (µS) Yis (mS) ϕrs 102 10 −103 −102 bis yrs 1 −10 10 gis 10−1 10 102 1 10 103 −1 103 102 f (MHz) f (MHz) VDS = 5 V; VG2 = 4 V; ID = 18 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V; ID = 18 mA; Tamb = 25 °C. Fig.16 Reverse transfer admittance and phase as a function of frequency; typical values; amplifier a. Fig.15 Input admittance as a function of frequency; typical values; amplifier a. MLE270 102 handbook, halfpage MLE271 10 handbook, halfpage ϕfs (deg) yfs yfs (mS) −102 Yos (mS) bos 1 10 −10 −ϕfs gos 10−1 1 10 102 f (MHz) 10−2 10 −1 103 102 f (MHz) 103 VDS = 5 V; VG2 = 4 V; ID = 18 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V; ID = 18 mA; Tamb = 25 °C. Fig.17 Forward transfer admittance and phase as a function of frequency; typical values; amplifier a. 2003 Nov 17 Fig.18 Output admittance as a function of frequency; typical values; amplifier a. 10 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 Amplifier a scattering parameters VDS = 5 V; VG2-S = 4 V; ID = 18 mA; Tamb = 25 °C f (MHz) s21 s11 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.988 −4.62 3.72 174.72 0.0008 86.73 0.991 −2.07 100 0.984 −9.23 3.71 169.42 0.0015 84.39 0.989 −4.16 200 0.971 −18.33 3.66 159.05 0.0029 79.96 0.986 −8.24 300 0.951 −27.32 3.58 148.77 0.0038 76.62 0.980 −12.32 400 0.926 −36.04 3.47 138.74 0.0044 74.42 0.973 −16.33 500 0.896 −44.50 3.36 129.05 0.0046 74.84 0.965 −20.25 600 0.865 −52.63 3.23 119.67 0.0043 79.73 0.958 −24.20 700 0.832 −60.47 3.09 110.43 0.0038 92.63 0.951 −28.14 800 0.797 −67.66 2.91 101.40 0.0028 118.47 0.937 −32.14 900 0.769 −75.01 2.83 93.09 0.0051 146.61 0.940 −35.76 1000 0.732 −81.73 2.67 84.05 0.0071 159.78 0.937 −39.86 Noise data VDS = 5 V; VG2-S = 4 V; ID = 18 mA; Tamb = 25 °C Γopt f (MHz) Fmin (dB) (ratio) (deg) Rn (Ω) 400 1.3 0.618 22.7 26.7 800 1.6 0.593 44.1 29.7 2003 Nov 17 11 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 DYNAMIC CHARACTERISTICS AMPLIFIER b Common source; Tamb = 25 °C; VG2-S = 4 V; VDS = 5 V; ID = 12 mA; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT yfs forward transfer admittance pulsed; Tj = 25 °C 29 34 44 mS Cig1-ss input capacitance at gate 1 f = 1 MHz − 1.7 2.2 pF Cig2-ss input capacitance at gate 2 f = 1 MHz − 4.2 − pF Coss output capacitance f = 1 MHz − 0.85 − pF Crss reverse transfer capacitance f = 1 MHz − 15 30 fF F noise figure f = 11 MHz; GS = 20 mS; BS = 0 − 3.5 − dB f = 400 MHz; YS = YS opt − 1.3 1.9 dB f = 800 MHz; YS = YS opt − 1.4 2 dB f = 200 MHz; GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt; note 1 − 35 − dB f = 400 MHz; GS = 2 mS; BS = BS opt; GL = 1 mS; BL = BL opt; note 1 − 31 − dB f = 800 MHz; GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt; note 1 − 27 − dB Gtr Xmod power gain cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 2 at 0 dB AGC 90 − − dBµV at 10 dB AGC − 90 − dBµV at 40 dB AGC 100 103 − dBµV Notes 1. Calculated from measured s-parameters. 2. Measured in Fig.35 test circuit. 2003 Nov 17 12 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 GRAPHS FOR AMPLIFIER b MLE272 30 handbook, halfpage ID (2) (mA) (3) MLE273 32 handbook, halfpage (1) ID (mA) (4) (5) (1) 24 20 (2) (3) 16 (6) (4) (5) 10 8 (7) (6) (7) 0 0 0 0.5 1 1.5 2 0 VG1-S (V) VDS = 5 V; Tj = 25 °C. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. 4 VDS (V) 6 VG2-S = 4 V; Tj = 25 °C. (1) VG1-S = 1.5 V. (2) VG1-S = 1.4 V. (3) VG1-S = 1.3 V. (4) VG1-S = 1.2 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. Fig.19 Transfer characteristics; typical values; amplifier b. 2003 Nov 17 2 (5) VG1-S = 1.1 V. (6) VG1-S = 1 V. (7) VG1-S = 0.9 V. Fig.20 Output characteristics; typical values; amplifier b. 13 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE274 100 IG1 handbook, halfpage (1) MLE275 50 handbook, halfpage (2) (µA) yfs (mS) 80 40 (2) (3) (3) (4) (4) 60 (1) 30 (5) (5) 20 40 (6) (6) 10 20 (7) (7) 0 0 0 0.5 1 0 1.5 2 VG1-S (V) VDS = 5 V; Tj = 25 °C. 10 20 ID(mA) 30 VDS = 5 V; Tj = 25 °C. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (7) VG2-S = 1 V. Fig.21 Gate 1 current as a function of gate 1 voltage; typical values; amplifier b. (5) VG2-S = 2 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. Fig.22 Forward transfer admittance as a function of drain current; typical values; amplifier b. MLE276 24 (1) VG2-S = 4 V. MLE277 12 handbook, halfpage handbook, halfpage ID (mA) ID (mA) 16 8 8 4 0 0 0 10 20 30 40 50 IG1 (µA) 0 1 2 3 4 5 VGG (V) VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. VDS = 5 V; VG2-S = 4 V; Tj = 25 °C. RG1 = 150 kΩ (connected to VGG); see Fig.35. Fig.23 Drain current as a function of gate 1 current; typical values; amplifier b. Fig.24 Drain current as a function of gate 1 supply voltage (VGG); typical values; amplifier b. 2003 Nov 17 14 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE278 24 MLE279 16 handbook, halfpage handbook, halfpage ID ID (mA) (1) (mA) (2) (1) (2) 12 (3) (3) 16 (4) (4) (5) (5) 8 (6) (7) 8 4 0 0 0 2 4 6 8 0 2 4 VGG = VDS (V) VG2-S (V) VG2-S = 4 V; Tj = 25 °C. RG1 = 150 kΩ (connected to VGG); see Fig.35. (1) RG1 = 270 kΩ. (2) RG1 = 220 kΩ. (3) RG1 = 180 kΩ. (4) RG1 = 150 kΩ. VDS = 5 V; Tj = 25 °C. RG1 = 150 kΩ (connected to VGG); see Fig.35. (5) RG1 = 120 kΩ. (6) RG1 = 100 kΩ. (7) RG1 = 82 kΩ. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. Fig.25 Drain current as a function of gate 1 (VGG) and drain supply voltage; typical values; amplifier b. 2003 Nov 17 (4) VGG = 3.5 V. (5) VGG = 3 V. Fig.26 Drain current as a function of gate 2 voltage; typical values; amplifier b. 15 6 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE280 30 MLE282 120 handbook, halfpage handbook, halfpage IG1 (µA) 20 (1) Vunw (dBµV) (2) 110 (3) (4) 100 (5) 10 90 0 80 0 2 4 VG2-S (V) 0 6 10 20 30 40 50 gain reduction (dB) VDS 5 V; Tj = 25 °C. RG1 = 150 kΩ (connected to VGG); see Fig.35. (1) VGG = 5 V. (2) VGG = 4.5 V. (3) VGG = 4 V. (4) VGG = 3.5 V. (5) VGG = 3 V. VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ; f = 50 MHz; f unw = 60 MHz; Tamb = 25 °C; see Fig.35. Fig.28 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier b. Fig.27 Gate 1 current as a function of gate 2 voltage; typical values; amplifier b. MLE281 0 MLE283 16 handbook, halfpage handbook, gain halfpage ID (mA) reduction (dB) −10 12 −20 8 −30 4 −40 −50 0 0 1 2 4 3 0 VAGC (V) 10 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ; f = 50 MHz; Tamb = 25 °C; see Fig.35. VDS = 5 V; VGG = 5 V; RG1 = 150 kΩ; f = 50 MHz; Tamb = 25 °C; see Fig.35. Fig.29 Typical gain reduction as a function of AGC voltage; typical values; amplifier b. Fig.30 Drain current as a function of gain reduction; typical values; amplifier b. 2003 Nov 17 16 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 MLE284 102 handbook, halfpage MLE285 103 handbook, halfpage Yis (mS) −103 ϕrs (deg) yrs (µS) 10 ϕrs 102 −102 bis 1 yrs gis −10 10 10−1 10−2 10 102 f (MHz) 1 10 103 −1 103 102 f (MHz) VDS = 5 V; VG2 = 4 V; ID = 12 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V; ID = 12 mA; Tamb = 25 °C. Fig.32 Reverse transfer admittance and phase as a function of frequency; typical values; amplifier b. Fig.31 Input admittance as a function of frequency; typical values; amplifier b. MLE286 102 handbook, halfpage yfs yfs (mS) −102 102 handbook, halfpage ϕfs (deg) Yos (mS) MLE287 bos 10 −10 10 gos −ϕfs 1 10 102 1 f (MHz) 10−1 10 −1 103 102 f (MHz) 103 VDS = 5 V; VG2 = 4 V; ID = 12 mA; Tamb = 25 °C. VDS = 5 V; VG2 = 4 V; ID = 12 mA; Tamb = 25 °C. Fig.33 Forward transfer admittance and phase as a function of frequency; typical values; amplifier b. 2003 Nov 17 Fig.34 Output admittance as a function of frequency; typical values; amplifier b. 17 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 VAGC handbook, full pagewidth R1 10 kΩ C1 4.7 nF C3 4.7 nF L1 C2 RGEN 50 Ω R2 50 Ω DUT ≈ 2.2 µH RL 50 Ω C4 4.7 nF RG1 4.7 nF VGG VI VDS MGS315 Fig.35 Cross-modulation test set-up (for one MOS-FET). Amplifier b scattering parameters VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C f (MHz) s21 s11 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.991 −3.43 3.44 176.33 0.0008 86.54 0.988 −1.69 100 0.989 −6.84 3.43 172.66 0.0015 84.92 0.987 −3.38 200 0.982 −13.61 3.41 165.44 0.0029 80.95 0.985 −6.72 300 0.973 −20.37 3.38 158.20 0.0041 77.63 0.982 −10.08 400 0.961 −27.05 3.34 151.04 0.0051 74.43 0.978 −13.46 500 0.947 −33.68 3.29 144.02 0.0058 71.86 0.973 −16.83 600 0.933 −40.17 3.23 137.12 0.0062 70.28 0.969 −20.25 700 0.919 −46.54 3.16 130.22 0.0063 70.72 0.965 −23.68 800 0.905 −52.86 3.09 123.22 0.0065 72.37 0.960 −27.22 900 0.890 −58.60 3.02 116.84 0.0055 75.91 0.958 −30.57 1000 0.881 −64.34 2.94 110.20 0.0058 89.82 0.958 −34.14 Noise data VDS = 5 V; VG2-S = 4 V; ID = 12 mA; Tamb = 25 °C Γopt f (MHz) Fmin (dB) (ratio) (deg) Rn (Ω) 400 1.3 0.648 14.4 28.8 800 1.4 0.604 31.1 27.9 2003 Nov 17 18 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 PACKAGE OUTLINE Plastic surface mounted package; 6 leads SOT363 D E B y X A HE 6 v M A 4 5 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT363 2003 Nov 17 REFERENCES IEC JEDEC EIAJ SC-88 19 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors Product specification Dual N-channel dual-gate MOS-FET BF1206 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Nov 17 20 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R77 20p/01/pp21 Date of release: 2003 Nov 17 Document order number: 9397 750 12005