74AUP1T45 Low-power dual supply translating transceiver; 3-state Rev. 02 — 3 August 2009 Product data sheet 1. General description The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)) which enable bidirectional level translation. Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A. Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC(A) and VCC(B) ranges. The device ensures low static and dynamic power consumption and is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND, both A and B are in the high-impedance OFF-state. 2. Features n Wide supply voltage range: u VCC(A): 1.1 V to 3.6 V u VCC(B): 1.1 V to 3.6 V n High noise immunity n Complies with JEDEC standards: u JESD8-7 (1.2 V to 1.95 V) u JESD8-5 (1.8 V to 2.7 V) u JESD8-B (2.7 V to 3.6 V) n ESD protection: u HBM JESD22-A114E Class 3A exceeds 5000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Low static power consumption; ICC = 0.9 µA (maximum) n Suspend mode n Latch-up performance exceeds 100 mA per JESD 78 Class II n Inputs accept voltages up to 3.6 V n Low noise overshoot and undershoot < 10 % of VCC n IOFF circuitry provides partial Power-down mode operation n Multiple package options n Specified from −40 °C to +85 °C and −40 °C to +125 °C 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1T45GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP1T45GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74AUP1T45GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Type number Marking code[1] 74AUP1T45GW p5 74AUP1T45GM p5 74AUP1T45GF p5 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram DIR 5 DIR A 3 A 4 VCC(A) B B VCC(B) VCC(A) 001aae962 Fig 1. Logic symbol 001aae963 Fig 2. Logic diagram 74AUP1T45_2 Product data sheet VCC(B) © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 2 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 6. Pinning information 6.1 Pinning 74AUP1T45 74AUP1T45 VCC(A) 1 6 GND 2 5 DIR A 3 4 B VCC(A) 1 6 VCC(B) GND 2 5 DIR VCC(B) A VCC(A) 1 6 VCC(B) GND 2 5 DIR A 3 4 B B 001aae965 001aae966 Transparent top view Transparent top view 001aae964 Fig 3. 4 3 74AUP1T45 Pin configuration SOT363 (SC-88) Fig 4. Pin configuration SOT886 (XSON6) Fig 5. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage port A GND 2 ground (0 V) A 3 data input or output A B 4 data input or output B DIR 5 direction control DIR VCC(B) 6 supply voltage port B 7. Functional description Table 4. Function table[1] Supply voltage Input[2] Input/output[3] VCC(A), VCC(B) DIR A B 1.1 V to 3.6 V L A=B input 1.1 V to 3.6 V H input B=A GND X suspend mode suspend mode [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [2] The DIR input circuit is referenced to VCC(A). [3] The input circuit of the data I/Os are always active. 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 3 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC(A) supply voltage port A VCC(B) supply voltage port B IIK input clamping current Conditions VI < 0 V [1] VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode Min Max Unit −0.5 +4.6 V −0.5 +4.6 V −50 - mA −0.5 +4.6 V −50 - mA A port [1][2] −0.5 VCC(A) + 0.5 V B port [1][2] −0.5 VCC(B) + 0.5 V [1][2] −0.5 +4.6 suspend or 3-state mode V IO output current - ±20 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C - 250 mW total power dissipation Ptot VO = 0 V to VCC Tamb = −40 °C to +125 °C [3] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The values of VCC(A) and VCC(B) are provided in the recommended operating conditions; see Table 6. [3] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Min Max Unit VCC(A) supply voltage port A 1.1 3.6 V VCC(B) supply voltage port B 1.1 3.6 V VI input voltage 0 3.6 V VO output voltage Tamb ambient temperature ∆t/∆V input transition rise and fall rate [1] Conditions [1] VCCI =1.1 V to 3.6 V 0 VCCO V −40 +125 °C 0 200 ns/V VCCO is the supply voltage associated with the output port. 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 4 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCCI = 1.1 V to 1.95 V 0.65 × VCCI - - V VCCI = 2.3 V to 2.7 V 1.6 - - V 2.0 - - V VCCI = 1.1 V to 1.95 V 0.65 × VCC(A) - - V VCCI = 2.3 V to 2.7 V 1.6 - - V 2.0 - - V VCCI = 1.1 V to 1.95 V - - 0.35 × VCCI V VCCI = 2.3 V to 2.7 V - - 0.7 V - - 0.9 V VCCI = 1.1 V to 1.95 V - - 0.35 × VCC(A) V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V Tamb = 25 °C VIH HIGH-level input voltage [1][3] data input VCCI = 3.0 V to 3.6 V [1][4] DIR input VCCI = 3.0 V to 3.6 V VIL LOW-level input voltage [1][3] data input VCCI = 3.0 V to 3.6 V [1][4] DIR input VOH VOL HIGH-level output voltage VI = VIH IO = −20 µA; VCC(A) = VCC(B) = 1.1 V to 3.6 V [2] VCCO − 0.1 - - V IO = −1.1 mA; VCC(A) = VCC(B) = 1.1 V [2] 0.75 × VCCO - - V IO = −1.7 mA; VCC(A) = VCC(B) = 1.4 V 1.11 - - V IO = −1.9 mA; VCC(A) = VCC(B) = 1.65 V 1.32 - - V IO = −2.3 mA; VCC(A) = VCC(B) = 2.3 V 2.05 - - V IO = −3.1 mA; VCC(A) = VCC(B) = 2.3 V 1.9 - - V IO = −2.7 mA; VCC(A) = VCC(B) = 3.0 V 2.72 - - V IO = −4.0 mA; VCC(A) = VCC(B) = 3.0 V 2.6 - - V - - 0.1 V LOW-level output VI = VIL voltage IO = 20 µA; VCC(A) = VCC(B) = 1.1 V to 3.6 V - - 0.3 × VCCO V IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V - - 0.31 V IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V - - 0.31 V IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V - - 0.31 V IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V - - 0.44 V IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V - - 0.31 V IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V - - 0.44 V - - ±0.1 µA IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V II input leakage current DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 1.1 V to 3.6 V 74AUP1T45_2 Product data sheet [2] © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 5 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max - - ±0.1 µA A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V - - ±0.2 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 1.1 V to 3.6 V - - ±0.2 µA DIR input; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V - - ±0.2 µA A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V - - ±0.2 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V to 0.2 V; VCC(A) = 1.1 V to 3.6 V - - ±0.2 µA DIR input; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V - - ±0.2 µA VCC(A) = VCC(B) = 1.1 V to 3.6 V - - 0.5 µA VCC(A) = 3.6 V; VCC(B) = 0 V - - 0.5 µA - 0 - µA VCC(A) = VCC(B) = 1.1 V to 3.6 V - - 0.5 µA VCC(A) = 3.6 V; VCC(B) = 0 V - 0 - µA - - 0.5 µA - - 0.5 µA additional supply A port; VCC(A) = VCC(B) = 3.3 V; current A port at VCC(A) − 0.6 V; DIR at VCC(A); B port = open - - 40 µA B port; VCC(A) = VCC(B) = 3.3 V; B port at VCC(B) − 0.6 V; DIR at GND; A port = open - - 40 µA DIR input; VCC(A) = VCC(B) = 3.3 V; A port at VCC(A) or GND; B port = open; DIR at VCC(A) − 0.6 V - - 40 µA - 0.9 - pF - 2.0 - pF IOZ OFF-state output A or B port; VI = VIH or VIL; VO = 0 V to VCCO; current VCC(A) = VCC(B) = 1.1 V to 3.6 V IOFF power-off leakage current ∆IOFF ICC additional power-off leakage current supply current A port; VI = GND or VCCI; IO = 0 A [2] [1] VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = GND or VCCI; IO = 0 A [1] VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = VCC(B) = 1.1 V to 3.6 V ∆ICC CI input capacitance DIR input; VI = GND or VCC(A); VCC(A) = VCC(B) = 1.1 V to 3.6 V CI/O input/output capacitance A and B port; suspend mode; VCCI = 0 V; VCCO = 1.1 V to 3.6 V; VO = VCCO or GND 74AUP1T45_2 Product data sheet Unit [1] [1][2] © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 6 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VCCI = 1.1 V to 1.95 V 0.65 × VCCI - - V VCCI = 2.3 V to 2.7 V 1.6 - - V 2.0 - - V VCCI = 1.1 V to 1.95 V 0.65 × VCC(A) - - V VCCI = 2.3 V to 2.7 V 1.6 - - V 2.0 - - V VCCI = 1.1 V to 1.95 V - - 0.35 × VCCI V VCCI = 2.3 V to 2.7 V - - 0.7 V - - 0.9 V VCCI = 1.1 V to 1.95 V - - 0.35 × VCC(A) V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V Tamb = −40 °C to +85 °C VIH HIGH-level input voltage [1][3] data input VCCI = 3.0 V to 3.6 V [1][4] DIR input VCCI = 3.0 V to 3.6 V VIL LOW-level input voltage [1][3] data input VCCI = 3.0 V to 3.6 V [1][4] DIR input VOH VOL HIGH-level output voltage VI = VIH IO = −20 µA; VCC(A) = VCC(B) = 1.1 V to 3.6 V [2] VCCO − 0.1 - - V IO = −1.1 mA; VCC(A) = VCC(B) = 1.1 V [2] 0.7 × VCCO - - V IO = −1.7 mA; VCC(A) = VCC(B) = 1.4 V 1.03 - - V IO = −1.9 mA; VCC(A) = VCC(B) = 1.65 V 1.30 - - V IO = −2.3 mA; VCC(A) = VCC(B) = 2.3 V 1.97 - - V IO = −3.1 mA; VCC(A) = VCC(B) = 2.3 V 1.85 - - V IO = −2.7 mA; VCC(A) = VCC(B) = 3.0 V 2.67 - - V IO = −4.0 mA; VCC(A) = VCC(B) = 3.0 V 2.55 - - V - - 0.1 V - - 0.3 × VCCO V LOW-level output VI = VIL voltage IO = 20 µA; VCC(A) = VCC(B) = 1.1 V to 3.6 V IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V - - 0.37 V IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V - - 0.35 V IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V - - 0.33 V IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V - - 0.45 V IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V - - 0.33 V IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V - - 0.45 V - - ±0.5 µA - - ±0.5 µA II input leakage current IOZ OFF-state output A or B port; VI = VIH or VIL; VO = 0 V to VCCO; current VCC(A) = VCC(B) = 1.1 V to 3.6 V DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 1.1 V to 3.6 V 74AUP1T45_2 Product data sheet [2] [2] © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 7 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max IOFF A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V - - ±0.5 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 1.1 V to 3.6 V - - ±0.5 µA DIR input; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V - - ±0.5 µA A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V - - ±0.6 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V to 0.2 V; VCC(A) = 1.1 V to 3.6 V - - ±0.6 µA DIR input; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V - - ±0.6 µA VCC(A) = VCC(B) = 1.1 V to 3.6 V - - 0.9 µA VCC(A) = 3.6 V; VCC(B) = 0 V - - 0.9 µA VCC(A) = 0 V; VCC(B) = 3.6 V - 0 - µA VCC(A) = VCC(B) = 1.1 V to 3.6 V - - 0.9 µA VCC(A) = 3.6 V; VCC(B) = 0 V - 0 - µA VCC(A) = 0 V; VCC(B) = 3.6 V - - 0.9 µA - - 0.9 µA additional supply A port; VCC(A) = VCC(B) = 3.3 V; current A port at VCC(A) − 0.6 V; DIR at VCC(A); B port = open - - 50 µA B port; VCC(A) = VCC(B) = 3.3 V; B port at VCC(B) − 0.6 V; DIR at GND; A port = open - - 50 µA DIR input; VCC(A) = VCC(B) = 3.3 V; A port at VCC(A) or GND; B port = open; DIR at VCC(A) − 0.6 V - - 50 µA VCCI = 1.1 V to 1.95 V 0.7 × VCCI - - V VCCI = 2.3 V to 2.7 V 1.6 - - V 2.0 - - V ∆IOFF ICC power-off leakage current additional power-off leakage current supply current A port; VI = GND or VCCI; IO = 0 A B port; VI = GND or VCCI; IO = 0 A A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = VCC(B) = 1.1 V to 3.6 V ∆ICC Unit [1] [1] [1] Tamb = −40 °C to +125 °C VIH HIGH-level input voltage [1][3] data input VCCI = 3.0 V to 3.6 V [1][4] DIR input VCCI = 1.1 V to 1.95 V 0.7 × VCC(A) - - V VCCI = 2.3 V to 2.7 V 1.6 - - V VCCI = 3.0 V to 3.6 V 2.0 - - V 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 8 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIL LOW-level input voltage Conditions Min Typ Max VCCI = 1.1 V to 1.95 V - - 0.3 × VCCI V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V VCCI = 1.1 V to 1.95 V - - 0.3 × VCC(A) V VCCI = 2.3 V to 2.7 V - - 0.7 V VCCI = 3.0 V to 3.6 V - - 0.9 V data input [1][4] DIR input VOH VOL HIGH-level output voltage VI = VIH IO = −20 µA; VCC(A) = VCC(B) = 1.1 V to 3.6 V [2] VCCO − 0.11 - - V IO = −1.1 mA; VCC(A) = VCC(B) = 1.1 V [2] 0.6 × VCCO - - V IO = −1.7 mA; VCC(A) = VCC(B) = 1.4 V 0.93 - - V IO = −1.9 mA; VCC(A) = VCC(B) = 1.65 V 1.17 - - V IO = −2.3 mA; VCC(A) = VCC(B) = 2.3 V 1.77 - - V IO = −3.1 mA; VCC(A) = VCC(B) = 2.3 V 1.67 - - V IO = −2.7 mA; VCC(A) = VCC(B) = 3.0 V 2.40 - - V IO = −4.0 mA; VCC(A) = VCC(B) = 3.0 V 2.30 - - V - - 0.11 V - - 0.33 × VCCO V - - 0.41 V LOW-level output VI = VIL voltage IO = 20 µA; VCC(A) = VCC(B) = 1.1 V to 3.6 V IO = 1.1 mA; VCC(A) = VCC(B) = 1.1 V [2] IO = 1.7 mA; VCC(A) = VCC(B) = 1.4 V IO = 1.9 mA; VCC(A) = VCC(B) = 1.65 V - - 0.39 V IO = 2.3 mA; VCC(A) = VCC(B) = 2.3 V - - 0.36 V IO = 3.1 mA; VCC(A) = VCC(B) = 2.3 V - - 0.50 V IO = 2.7 mA; VCC(A) = VCC(B) = 3.0 V - - 0.36 V IO = 4.0 mA; VCC(A) = VCC(B) = 3.0 V - - 0.50 V - - ±0.75 µA - - ±0.75 µA A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V - - ±0.75 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V; VCC(A) = 1.1 V to 3.6 V - - ±0.75 µA DIR input; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V; VCC(B) = 1.1 V to 3.6 V - - ±0.75 µA II input leakage current IOZ OFF-state output A or B port; VI = VIH or VIL; VO = 0 V to VCCO; current VCC(A) = VCC(B) = 1.1 V to 3.6 V IOFF power-off leakage current DIR input; VI = GND to VCC(A); VCC(A) = VCC(B) = 1.1 V to 3.6 V 74AUP1T45_2 Product data sheet Unit [1][3] [2] © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 9 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max ∆IOFF A port; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V - - ±0.75 µA B port; VI or VO = 0 V to 3.6 V; VCC(B) = 0 V to 0.2 V; VCC(A) = 1.1 V to 3.6 V - - ±0.75 µA DIR input; VI or VO = 0 V to 3.6 V; VCC(A) = 0 V to 0.2 V; VCC(B) = 1.1 V to 3.6 V - - ±0.75 µA VCC(A) = VCC(B) = 1.1 V to 3.6 V - - 1.4 µA VCC(A) = 3.6 V; VCC(B) = 0 V - - 1.4 µA - 0 - µA VCC(A) = VCC(B) = 1.1 V to 3.6 V - - 1.4 µA VCC(A) = 3.6 V; VCC(B) = 0 V - 0 - µA - - 1.4 µA - - 1.4 µA additional supply A port; VCC(A) = VCC(B) = 3.3 V; current A port at VCC(A) − 0.6 V; DIR at VCC(A); B port = open - - 75 µA B port; VCC(A) = VCC(B) = 3.3 V; B port at VCC(B) − 0.6 V; DIR at GND; A port = open - - 75 µA DIR input; VCC(A) = VCC(B) = 3.3 V; A port at VCC(A) or GND; B port = open; DIR at VCC(A) − 0.6 V - - 75 µA additional power-off leakage current supply current ICC A port; VI = GND or VCCI; IO = 0 A [1] VCC(A) = 0 V; VCC(B) = 3.6 V B port; VI = GND or VCCI; IO = 0 A [1] VCC(A) = 0 V; VCC(B) = 3.6 V A plus B port (ICC(A) + ICC(B)); IO = 0 A; VI = GND or VCCI; VCC(A) = VCC(B) = 1.1 V to 3.6 V ∆ICC [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. [1] [3] For VCCI values not specified in the data sheet: minimum VIH = 0.7 × VCCI and maximum VIL = 0.3 × VCCI. [4] For VCCI values not specified in the data sheet: minimum VIH = 0.7 × VCC(A) and maximum VIL = 0.3 × VCC(A). [5] All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. 74AUP1T45_2 Product data sheet Unit © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 10 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 2.8 15.4 28.0 2.4 28.3 31.2 ns VCC(B) = 1.4 V to 1.6 V 2.8 10.2 16.2 2.6 17.5 19.3 ns VCC(B) = 1.65 V to 1.95 V 2.4 8.1 13.0 2.2 14.4 15.9 ns VCC(B) = 2.3 V to 2.7 V 2.5 6.3 10.0 2.1 10.7 11.8 ns 2.3 5.6 9.0 1.9 9.7 10.7 ns VCC(B) = 1.1 V to 1.3 V 2.7 5.3 8.5 2.5 8.7 9.6 ns VCC(B) = 1.4 V to 1.6 V 2.9 5.3 8.4 2.7 8.7 9.7 ns VCC(B) = 1.65 V to 1.95 V 2.7 5.3 8.5 2.5 9.0 10.0 ns VCC(B) = 2.3 V to 2.7 V 2.7 5.3 8.7 2.5 8.9 9.9 ns VCC(B) = 3.0 V to 3.6 V 2.9 5.3 8.7 2.5 9.1 10.1 ns VCC(B) = 1.1 V to 1.3 V 6.1 13.2 22.1 5.4 23.4 25.8 ns VCC(B) = 1.4 V to 1.6 V 5.0 9.3 13.9 4.4 15.2 16.7 ns VCC(B) = 1.65 V to 1.95 V 4.2 8.1 12.3 3.6 13.5 14.9 ns VCC(B) = 2.3 V to 2.7 V 3.3 6.3 9.3 2.9 10.2 11.2 ns VCC(B) = 3.0 V to 3.6 V 3.6 6.3 9.2 3.2 9.7 10.7 ns VCC(B) = 1.1 V to 1.3 V 2.5 14.5 26.6 2.2 27.1 29.9 ns VCC(B) = 1.4 V to 1.6 V 2.5 9.4 14.5 2.3 15.9 17.5 ns VCC(B) = 1.65 V to 1.95 V 2.1 7.4 11.2 1.9 12.7 14.0 ns VCC(B) = 2.3 V to 2.7 V 2.2 5.5 8.0 1.8 8.9 9.8 ns VCC(B) = 3.0 V to 3.6 V 2.0 4.7 6.8 1.6 7.6 8.4 ns CL = 5 pF; VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 5 pF; VCC(A) = 1.4 V to 1.6 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 11 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 2.0 3.8 5.3 1.9 5.7 6.3 ns VCC(B) = 1.4 V to 1.6 V 2.2 3.8 5.3 2.0 5.7 6.4 ns VCC(B) = 1.65 V to 1.95 V 2.1 3.8 5.5 1.8 5.9 6.6 ns VCC(B) = 2.3 V to 2.7 V 2.1 3.8 5.5 1.9 5.9 6.6 ns VCC(B) = 3.0 V to 3.6 V 2.2 3.8 5.5 1.9 6.0 6.6 ns VCC(B) = 1.1 V to 1.3 V 5.7 12.7 21.0 5.2 22.3 24.6 ns VCC(B) = 1.4 V to 1.6 V 4.7 8.7 12.7 4.1 14.1 15.5 ns VCC(B) = 1.65 V to 1.95 V 3.9 7.4 10.9 3.3 12.3 13.5 ns VCC(B) = 2.3 V to 2.7 V 3.0 5.6 7.8 2.6 8.8 9.7 ns VCC(B) = 3.0 V to 3.6 V 3.3 5.5 7.4 2.9 8.1 8.9 ns VCC(B) = 1.1 V to 1.3 V 2.4 14.2 26.1 2.0 26.5 29.2 ns VCC(B) = 1.4 V to 1.6 V 2.4 9.1 13.9 2.1 15.4 17.0 ns VCC(B) = 1.65 V to 1.95 V 2.0 7.0 10.7 1.7 12.1 13.4 ns VCC(B) = 2.3 V to 2.7 V 2.0 5.1 7.4 1.6 8.2 9.1 ns 1.9 4.3 6.1 1.5 6.9 7.7 ns VCC(B) = 1.1 V to 1.3 V 2.0 3.5 4.8 1.8 5.2 5.8 ns VCC(B) = 1.4 V to 1.6 V 2.1 3.5 4.8 1.9 5.2 5.7 ns VCC(B) = 1.65 V to 1.95 V 2.0 3.5 5.0 1.8 5.4 6.0 ns VCC(B) = 2.3 V to 2.7 V 2.0 3.5 4.9 1.8 5.4 6.0 ns 2.1 3.5 4.9 1.8 5.4 6.0 ns VCC(B) = 1.1 V to 1.3 V 5.8 12.4 20.6 5.1 21.9 24.2 ns VCC(B) = 1.4 V to 1.6 V 4.6 8.4 12.2 3.9 13.5 14.9 ns VCC(B) = 1.65 V to 1.95 V 3.8 7.1 10.4 3.2 11.8 13.0 ns VCC(B) = 2.3 V to 2.7 V 2.9 5.2 7.3 2.5 8.3 9.1 ns VCC(B) = 3.0 V to 3.6 V 3.1 5.1 6.9 2.7 7.5 8.3 ns VCC(B) = 1.1 V to 1.3 V 2.4 13.6 25.5 2.0 25.9 28.6 ns VCC(B) = 1.4 V to 1.6 V 2.3 8.5 13.3 2.1 14.7 16.2 ns VCC(B) = 1.65 V to 1.95 V 1.9 6.5 10.0 1.7 11.4 12.5 ns VCC(B) = 2.3 V to 2.7 V 1.9 4.6 6.7 1.6 7.5 8.3 ns VCC(B) = 3.0 V to 3.6 V 1.8 3.8 5.3 1.4 6.2 6.8 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 5 pF; VCC(A) = 1.65 V to 1.95 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 5 pF; VCC(A) = 2.3 V to 2.7 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 12 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 1.4 2.5 3.3 1.3 3.6 4.0 ns VCC(B) = 1.4 V to 1.6 V 1.6 2.5 3.3 1.4 3.6 4.0 ns VCC(B) = 1.65 V to 1.95 V 1.5 2.5 3.4 1.3 3.8 4.2 ns VCC(B) = 2.3 V to 2.7 V 1.4 2.5 3.4 1.3 3.8 4.2 ns VCC(B) = 3.0 V to 3.6 V 1.6 2.5 3.4 1.3 3.7 4.1 ns VCC(B) = 1.1 V to 1.3 V 5.8 12.3 20.4 5.1 21.8 24.0 ns VCC(B) = 1.4 V to 1.6 V 4.5 8.3 11.9 4.0 13.2 14.5 ns VCC(B) = 1.65 V to 1.95 V 3.7 7.0 10.0 3.2 11.3 12.5 ns VCC(B) = 2.3 V to 2.7 V 2.8 5.0 6.8 2.5 7.8 8.6 ns VCC(B) = 3.0 V to 3.6 V 3.1 4.9 6.4 2.7 7.0 7.8 ns VCC(B) = 1.1 V to 1.3 V 2.3 13.1 24.9 2.0 25.2 27.8 ns VCC(B) = 1.4 V to 1.6 V 2.3 8.1 12.8 2.0 14.1 15.5 ns VCC(B) = 1.65 V to 1.95 V 1.9 6.1 9.5 1.7 10.8 12.0 ns VCC(B) = 2.3 V to 2.7 V 1.9 4.3 6.2 1.6 7.0 7.7 ns 1.7 3.5 5.0 1.4 5.7 6.3 ns VCC(B) = 1.1 V to 1.3 V 1.7 2.8 3.5 1.5 3.8 4.2 ns VCC(B) = 1.4 V to 1.6 V 1.8 2.8 3.5 1.7 3.8 4.2 ns VCC(B) = 1.65 V to 1.95 V 1.7 2.8 3.6 1.5 4.0 4.4 ns VCC(B) = 2.3 V to 2.7 V 1.7 2.8 3.6 1.5 3.9 4.4 ns 1.8 2.8 3.6 1.5 3.9 4.3 ns VCC(B) = 1.1 V to 1.3 V 5.8 12.3 20.6 5.1 22.0 24.2 ns VCC(B) = 1.4 V to 1.6 V 4.6 8.3 11.8 4.0 13.1 14.5 ns VCC(B) = 1.65 V to 1.95 V 3.8 6.9 10.0 3.2 11.3 12.5 ns VCC(B) = 2.3 V to 2.7 V 2.8 5.0 6.7 2.5 7.6 8.4 ns VCC(B) = 3.0 V to 3.6 V 3.1 4.9 6.3 2.7 6.9 7.6 ns VCC(B) = 1.1 V to 1.3 V 3.0 16.2 29.8 2.7 30.2 33.3 ns VCC(B) = 1.4 V to 1.6 V 3.0 10.8 17.5 2.7 18.6 20.5 ns VCC(B) = 1.65 V to 1.95 V 3.1 8.7 13.5 2.8 14.6 16.1 ns VCC(B) = 2.3 V to 2.7 V 2.7 6.8 10.5 2.4 11.2 12.4 ns VCC(B) = 3.0 V to 3.6 V 2.7 6.1 9.6 2.4 10.1 11.1 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 5 pF; VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 10 pF; VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 13 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 3.2 6.5 9.9 3.1 10.2 11.3 ns VCC(B) = 1.4 V to 1.6 V 3.5 6.5 10.0 3.2 10.2 11.3 ns VCC(B) = 1.65 V to 1.95 V 3.7 6.5 9.8 3.5 10.1 11.1 ns VCC(B) = 2.3 V to 2.7 V 3.2 6.5 10.1 3.1 10.2 11.3 ns VCC(B) = 3.0 V to 3.6 V 3.6 6.5 10.1 3.2 10.3 11.4 ns VCC(B) = 1.1 V to 1.3 V 6.4 14.3 23.5 5.8 24.8 27.4 ns VCC(B) = 1.4 V to 1.6 V 5.3 10.2 15.4 4.6 16.6 18.4 ns VCC(B) = 1.65 V to 1.95 V 5.2 9.2 13.6 4.7 14.7 16.2 ns VCC(B) = 2.3 V to 2.7 V 3.6 7.1 10.1 3.2 11.0 12.1 ns VCC(B) = 3.0 V to 3.6 V 4.4 7.6 10.8 3.8 11.4 12.5 ns VCC(B) = 1.1 V to 1.3 V 2.7 15.3 28.3 2.4 29.0 31.9 ns VCC(B) = 1.4 V to 1.6 V 2.7 10.0 15.8 2.5 17.0 18.7 ns VCC(B) = 1.65 V to 1.95 V 2.8 7.9 11.8 2.5 13.0 14.4 ns VCC(B) = 2.3 V to 2.7 V 2.4 6.0 8.6 2.2 9.4 10.4 ns 2.4 5.2 7.4 2.1 8.0 8.9 ns VCC(B) = 1.1 V to 1.3 V 2.5 4.7 6.4 2.3 6.8 7.6 ns VCC(B) = 1.4 V to 1.6 V 2.7 4.7 6.5 2.4 6.9 7.6 ns VCC(B) = 1.65 V to 1.95 V 2.9 4.7 6.5 2.6 6.9 7.6 ns VCC(B) = 2.3 V to 2.7 V 2.5 4.7 6.5 2.3 6.9 7.6 ns 2.8 4.7 6.6 2.4 6.9 7.7 ns VCC(B) = 1.1 V to 1.3 V 6.1 13.7 22.4 5.6 23.8 26.3 ns VCC(B) = 1.4 V to 1.6 V 5.0 9.6 14.2 4.3 15.5 17.1 ns VCC(B) = 1.65 V to 1.95 V 4.9 8.5 12.3 4.4 13.4 14.8 ns VCC(B) = 2.3 V to 2.7 V 3.3 6.4 8.7 3.0 9.6 10.6 ns VCC(B) = 3.0 V to 3.6 V 4.1 6.7 9.1 3.5 9.7 10.8 ns VCC(B) = 1.1 V to 1.3 V 2.6 15.0 27.8 2.3 28.3 31.2 ns VCC(B) = 1.4 V to 1.6 V 2.6 9.7 15.2 2.3 16.5 18.2 ns VCC(B) = 1.65 V to 1.95 V 2.7 7.5 11.2 2.3 12.4 13.7 ns VCC(B) = 2.3 V to 2.7 V 2.3 5.6 7.9 2.0 8.8 9.7 ns VCC(B) = 3.0 V to 3.6 V 2.3 4.8 6.7 1.9 7.4 8.2 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 10 pF; VCC(A) = 1.4 V to 1.6 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 10 pF; VCC(A) = 1.65 V to 1.95 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 14 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 2.5 4.6 6.2 2.4 6.6 7.3 ns VCC(B) = 1.4 V to 1.6 V 2.7 4.6 6.3 2.5 6.7 7.4 ns VCC(B) = 1.65 V to 1.95 V 2.9 4.6 6.3 2.7 6.7 7.4 ns VCC(B) = 2.3 V to 2.7 V 2.5 4.6 6.2 2.4 6.7 7.4 ns VCC(B) = 3.0 V to 3.6 V 2.8 4.6 6.3 2.5 6.7 7.4 ns VCC(B) = 1.1 V to 1.3 V 6.1 13.5 22.1 5.4 23.4 25.8 ns VCC(B) = 1.4 V to 1.6 V 5.0 9.3 13.6 4.2 14.9 16.5 ns VCC(B) = 1.65 V to 1.95 V 4.8 8.3 11.8 4.2 13.0 14.3 ns VCC(B) = 2.3 V to 2.7 V 3.2 6.0 8.1 2.8 9.1 10.0 ns VCC(B) = 3.0 V to 3.6 V 3.9 6.4 8.5 3.3 9.2 10.2 ns VCC(B) = 1.1 V to 1.3 V 2.5 14.4 27.2 2.3 27.8 30.6 ns VCC(B) = 1.4 V to 1.6 V 2.5 9.1 14.6 2.3 15.8 17.4 ns VCC(B) = 1.65 V to 1.95 V 2.6 7.0 10.5 2.2 11.7 12.9 ns VCC(B) = 2.3 V to 2.7 V 2.2 5.1 7.2 1.9 8.0 8.9 ns 2.2 4.3 5.9 1.9 6.6 7.3 ns VCC(B) = 1.1 V to 1.3 V 1.8 3.3 4.2 1.7 4.6 5.1 ns VCC(B) = 1.4 V to 1.6 V 2.0 3.3 4.4 1.8 4.7 5.2 ns VCC(B) = 1.65 V to 1.95 V 2.1 3.3 4.4 2.0 4.7 5.2 ns VCC(B) = 2.3 V to 2.7 V 1.8 3.3 4.3 1.7 4.7 5.2 ns 2.1 3.3 4.4 1.8 4.7 5.2 ns VCC(B) = 1.1 V to 1.3 V 6.1 13.4 21.8 5.4 23.2 25.6 ns VCC(B) = 1.4 V to 1.6 V 4.9 9.2 13.3 4.2 14.6 16.1 ns VCC(B) = 1.65 V to 1.95 V 4.8 8.1 11.4 4.2 12.5 13.8 ns VCC(B) = 2.3 V to 2.7 V 3.1 5.8 7.7 2.8 8.6 9.5 ns VCC(B) = 3.0 V to 3.6 V 3.9 6.2 8.0 3.3 8.7 9.6 ns VCC(B) = 1.1 V to 1.3 V 2.5 14.0 26.6 2.2 27.0 29.8 ns VCC(B) = 1.4 V to 1.6 V 2.5 8.7 14.0 2.3 15.1 16.7 ns VCC(B) = 1.65 V to 1.95 V 2.5 6.6 10.1 2.2 11.2 12.4 ns VCC(B) = 2.3 V to 2.7 V 2.2 4.8 6.8 1.9 7.5 8.3 ns VCC(B) = 3.0 V to 3.6 V 2.1 4.0 5.5 1.9 6.1 6.8 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 10 pF; VCC(A) = 2.3 V to 2.7 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 10 pF; VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 15 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 2.3 4.0 5.0 2.2 5.3 5.9 ns VCC(B) = 1.4 V to 1.6 V 2.5 4.0 5.2 2.3 5.4 6.0 ns VCC(B) = 1.65 V to 1.95 V 2.6 4.0 5.2 2.5 5.4 6.0 ns VCC(B) = 2.3 V to 2.7 V 2.3 4.0 5.1 2.2 5.4 6.0 ns VCC(B) = 3.0 V to 3.6 V 2.6 4.0 5.2 2.3 5.4 6.0 ns VCC(B) = 1.1 V to 1.3 V 6.2 13.5 22.0 5.5 23.4 25.8 ns VCC(B) = 1.4 V to 1.6 V 4.9 9.2 13.2 4.2 14.6 16.1 ns VCC(B) = 1.65 V to 1.95 V 4.8 8.1 11.3 4.3 12.4 13.7 ns VCC(B) = 2.3 V to 2.7 V 3.1 5.8 7.6 2.8 8.5 9.4 ns VCC(B) = 3.0 V to 3.6 V 3.9 6.2 7.9 3.3 8.5 9.5 ns VCC(B) = 1.1 V to 1.3 V 3.4 16.9 31.6 3.0 32.0 35.2 ns VCC(B) = 1.4 V to 1.6 V 3.7 11.3 18.2 3.1 19.5 21.5 ns VCC(B) = 1.65 V to 1.95 V 3.2 9.1 14.3 3.0 15.6 17.2 ns VCC(B) = 2.3 V to 2.7 V 3.2 7.3 11.2 2.8 12.0 13.2 ns 3.1 6.5 10.2 2.6 10.7 11.8 ns VCC(B) = 1.1 V to 1.3 V 3.9 7.6 11.4 3.8 11.7 12.9 ns VCC(B) = 1.4 V to 1.6 V 4.5 7.6 11.3 4.1 11.7 12.9 ns VCC(B) = 1.65 V to 1.95 V 4.2 7.6 11.3 4.1 11.7 12.9 ns VCC(B) = 2.3 V to 2.7 V 3.9 7.6 11.7 3.8 11.9 13.1 ns 4.5 7.6 11.7 4.1 11.9 13.1 ns VCC(B) = 1.1 V to 1.3 V 7.2 15.4 24.9 6.5 26.3 29.0 ns VCC(B) = 1.4 V to 1.6 V 6.3 11.1 16.3 5.4 17.7 19.5 ns VCC(B) = 1.65 V to 1.95 V 5.7 10.4 15.0 5.2 16.2 17.9 ns VCC(B) = 2.3 V to 2.7 V 4.1 7.9 11.4 3.8 12.1 13.4 ns VCC(B) = 3.0 V to 3.6 V 5.3 8.8 12.2 4.9 12.7 14.1 ns VCC(B) = 1.1 V to 1.3 V 3.1 16.1 30.1 2.8 30.7 33.8 ns VCC(B) = 1.4 V to 1.6 V 3.4 10.5 16.5 2.8 17.9 19.7 ns VCC(B) = 1.65 V to 1.95 V 3.0 8.4 12.6 2.7 13.9 15.4 ns VCC(B) = 2.3 V to 2.7 V 2.9 6.4 9.3 2.5 10.1 11.2 ns VCC(B) = 3.0 V to 3.6 V 2.8 5.6 8.0 2.3 8.7 9.6 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 15 pF; VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 15 pF; VCC(A) = 1.4 V to 1.6 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 16 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 3.1 5.6 7.6 2.9 8.0 8.9 ns VCC(B) = 1.4 V to 1.6 V 3.5 5.6 7.5 3.1 8.0 8.8 ns VCC(B) = 1.65 V to 1.95 V 3.3 5.6 7.6 3.1 8.0 8.9 ns VCC(B) = 2.3 V to 2.7 V 3.1 5.6 7.7 2.9 8.1 9.0 ns VCC(B) = 3.0 V to 3.6 V 3.5 5.6 7.8 3.1 8.1 9.0 ns VCC(B) = 1.1 V to 1.3 V 6.9 14.9 23.8 6.4 25.3 27.9 ns VCC(B) = 1.4 V to 1.6 V 6.0 10.5 15.1 5.2 16.6 18.3 ns VCC(B) = 1.65 V to 1.95 V 5.4 9.7 13.7 5.0 15.0 16.5 ns VCC(B) = 2.3 V to 2.7 V 3.8 7.2 9.9 3.5 10.7 11.9 ns VCC(B) = 3.0 V to 3.6 V 5.0 8.0 10.5 4.6 11.1 12.3 ns VCC(B) = 1.1 V to 1.3 V 3.0 15.8 29.6 2.6 30.1 33.2 ns VCC(B) = 1.4 V to 1.6 V 3.2 10.2 15.9 2.6 17.4 19.2 ns VCC(B) = 1.65 V to 1.95 V 2.8 8.0 12.0 2.5 13.4 14.8 ns VCC(B) = 2.3 V to 2.7 V 2.8 6.0 8.6 2.3 9.5 10.5 ns 2.6 5.2 7.3 2.2 8.0 8.9 ns VCC(B) = 1.1 V to 1.3 V 3.2 5.8 7.6 3.1 8.0 8.9 ns VCC(B) = 1.4 V to 1.6 V 3.7 5.8 7.6 3.3 8.1 8.9 ns VCC(B) = 1.65 V to 1.95 V 3.5 5.8 7.7 3.3 8.1 9.0 ns VCC(B) = 2.3 V to 2.7 V 3.2 5.8 7.8 3.1 8.2 9.0 ns 3.7 5.8 7.8 3.4 8.1 9.0 ns VCC(B) = 1.1 V to 1.3 V 6.9 14.7 23.4 6.2 24.9 27.4 ns VCC(B) = 1.4 V to 1.6 V 5.9 10.2 14.6 5.0 16.0 17.7 ns VCC(B) = 1.65 V to 1.95 V 5.3 9.4 13.2 4.8 14.5 16.0 ns VCC(B) = 2.3 V to 2.7 V 3.7 6.8 9.4 3.4 10.2 11.3 ns VCC(B) = 3.0 V to 3.6 V 4.9 7.6 9.9 4.4 10.6 11.7 ns VCC(B) = 1.1 V to 1.3 V 3.0 15.2 29.0 2.6 29.5 32.5 ns VCC(B) = 1.4 V to 1.6 V 3.1 9.6 15.3 2.6 16.7 18.4 ns VCC(B) = 1.65 V to 1.95 V 2.7 7.5 11.3 2.5 12.6 13.9 ns VCC(B) = 2.3 V to 2.7 V 2.7 5.5 7.9 2.3 8.7 9.6 ns VCC(B) = 3.0 V to 3.6 V 2.5 4.7 6.5 2.1 7.2 8.0 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 15 pF; VCC(A) = 1.65 V to 1.95 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 15 pF; VCC(A) = 2.3 V to 2.7 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 17 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 2.4 4.1 5.2 2.2 5.6 6.2 ns VCC(B) = 1.4 V to 1.6 V 2.7 4.1 5.3 2.4 5.7 6.3 ns VCC(B) = 1.65 V to 1.95 V 2.5 4.1 5.4 2.4 5.7 6.3 ns VCC(B) = 2.3 V to 2.7 V 2.4 4.1 5.4 2.2 5.7 6.3 ns VCC(B) = 3.0 V to 3.6 V 2.7 4.1 5.3 2.4 5.6 6.2 ns VCC(B) = 1.1 V to 1.3 V 6.9 14.6 23.2 6.2 24.7 27.2 ns VCC(B) = 1.4 V to 1.6 V 5.9 10.1 14.2 5.0 15.6 17.3 ns VCC(B) = 1.65 V to 1.95 V 5.3 9.2 12.8 4.8 14.0 15.5 ns VCC(B) = 2.3 V to 2.7 V 3.7 6.7 8.9 3.4 9.8 10.8 ns VCC(B) = 3.0 V to 3.6 V 4.8 7.4 9.4 4.4 10.1 11.2 ns VCC(B) = 1.1 V to 1.3 V 2.9 14.7 28.3 2.6 28.8 31.7 ns VCC(B) = 1.4 V to 1.6 V 3.1 9.2 14.7 2.6 16.0 17.7 ns VCC(B) = 1.65 V to 1.95 V 2.7 7.1 10.9 2.4 12.1 13.4 ns VCC(B) = 2.3 V to 2.7 V 2.7 5.2 7.4 2.2 8.2 9.1 ns 2.5 4.5 6.1 2.1 6.8 7.5 ns VCC(B) = 1.1 V to 1.3 V 3.1 5.3 6.5 3.0 6.9 7.6 ns VCC(B) = 1.4 V to 1.6 V 3.5 5.3 6.6 3.2 7.0 7.7 ns VCC(B) = 1.65 V to 1.95 V 3.3 5.3 6.7 3.2 7.0 7.8 ns VCC(B) = 2.3 V to 2.7 V 3.1 5.3 6.8 3.0 7.1 7.8 ns 3.5 5.3 6.6 3.2 6.9 7.6 ns VCC(B) = 1.1 V to 1.3 V 6.9 14.6 23.4 6.3 24.9 27.4 ns VCC(B) = 1.4 V to 1.6 V 5.9 10.1 14.2 5.0 15.6 17.2 ns VCC(B) = 1.65 V to 1.95 V 5.3 9.2 12.7 4.8 13.9 15.4 ns VCC(B) = 2.3 V to 2.7 V 3.7 6.6 8.8 3.4 9.6 10.6 ns VCC(B) = 3.0 V to 3.6 V 4.8 7.4 9.3 4.4 10.0 11.0 ns VCC(B) = 1.1 V to 1.3 V 4.2 19.1 36.0 3.8 36.8 40.5 ns VCC(B) = 1.4 V to 1.6 V 4.5 12.8 20.6 4.0 22.0 24.2 ns VCC(B) = 1.65 V to 1.95 V 4.2 10.4 16.2 3.8 17.4 19.2 ns VCC(B) = 2.3 V to 2.7 V 4.0 8.3 12.4 3.5 13.2 14.5 ns VCC(B) = 3.0 V to 3.6 V 4.0 7.5 11.5 3.7 12.5 13.8 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 15 pF; VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 30 pF; VCC(A) = 1.1 V to 1.3 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 18 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 5.6 11.0 15.7 5.5 16.2 17.9 ns VCC(B) = 1.4 V to 1.6 V 6.1 11.0 15.6 6.0 15.9 17.5 ns VCC(B) = 1.65 V to 1.95 V 6.6 11.0 15.5 6.5 15.8 17.4 ns VCC(B) = 2.3 V to 2.7 V 5.6 11.0 15.6 5.5 15.8 17.5 ns VCC(B) = 3.0 V to 3.6 V 7.0 11.0 15.9 6.6 16.7 18.4 ns VCC(B) = 1.1 V to 1.3 V 8.7 18.9 29.0 8.1 30.5 33.6 ns VCC(B) = 1.4 V to 1.6 V 7.3 13.8 19.3 6.8 20.7 22.8 ns VCC(B) = 1.65 V to 1.95 V 8.1 13.7 19.2 7.7 20.3 22.4 ns VCC(B) = 2.3 V to 2.7 V 5.2 10.3 14.0 4.9 14.7 16.2 ns VCC(B) = 3.0 V to 3.6 V 8.1 12.5 16.5 7.5 18.0 19.9 ns VCC(B) = 1.1 V to 1.3 V 4.0 18.2 34.5 3.5 35.5 39.1 ns VCC(B) = 1.4 V to 1.6 V 4.2 12.0 18.9 3.7 20.3 22.4 ns VCC(B) = 1.65 V to 1.95 V 3.9 9.6 14.4 3.5 15.8 17.4 ns VCC(B) = 2.3 V to 2.7 V 3.8 7.5 10.4 3.2 11.4 12.6 ns 3.7 6.7 9.3 3.4 10.4 11.4 ns VCC(B) = 1.1 V to 1.3 V 4.4 8.3 10.8 4.3 11.4 12.6 ns VCC(B) = 1.4 V to 1.6 V 4.8 8.3 10.7 4.6 11.2 12.3 ns VCC(B) = 1.65 V to 1.95 V 5.2 8.3 10.8 5.0 11.2 12.4 ns VCC(B) = 2.3 V to 2.7 V 4.4 8.3 10.8 4.3 11.1 12.3 ns 5.5 8.3 11.0 5.1 11.8 13.0 ns VCC(B) = 1.1 V to 1.3 V 8.4 18.3 27.9 7.9 29.5 32.5 ns VCC(B) = 1.4 V to 1.6 V 7.1 13.2 18.2 6.6 19.6 21.6 ns VCC(B) = 1.65 V to 1.95 V 7.8 13.1 17.9 7.4 19.1 21.0 ns VCC(B) = 2.3 V to 2.7 V 4.9 9.6 12.6 4.6 13.4 14.8 ns VCC(B) = 3.0 V to 3.6 V 7.7 11.7 14.8 7.2 16.3 18.0 ns VCC(B) = 1.1 V to 1.3 V 3.9 18.0 34.0 3.4 34.9 38.4 ns VCC(B) = 1.4 V to 1.6 V 4.1 11.7 18.3 3.5 19.8 21.9 ns VCC(B) = 1.65 V to 1.95 V 3.8 9.2 13.9 3.4 15.2 16.8 ns VCC(B) = 2.3 V to 2.7 V 3.6 7.1 9.8 3.1 10.8 11.9 ns VCC(B) = 3.0 V to 3.6 V 3.5 6.3 8.6 3.2 9.7 10.7 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 30 pF; VCC(A) = 1.4 V to 1.6 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 30 pF; VCC(A) = 1.65 V to 1.95 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 19 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 5.0 9.2 11.7 4.8 12.3 13.6 ns VCC(B) = 1.4 V to 1.6 V 5.4 9.2 11.7 5.3 12.1 13.4 ns VCC(B) = 1.65 V to 1.95 V 5.8 9.1 11.9 5.7 12.3 13.6 ns VCC(B) = 2.3 V to 2.7 V 5.0 9.1 11.7 4.8 12.1 13.4 ns VCC(B) = 3.0 V to 3.6 V 6.2 9.2 11.9 5.8 12.7 14.1 ns VCC(B) = 1.1 V to 1.3 V 8.4 18.1 27.6 7.8 29.1 32.0 ns VCC(B) = 1.4 V to 1.6 V 7.0 12.9 17.7 6.4 19.1 21.0 ns VCC(B) = 1.65 V to 1.95 V 7.7 12.8 17.4 7.2 18.6 20.6 ns VCC(B) = 2.3 V to 2.7 V 4.8 9.3 12.0 4.5 12.9 14.2 ns VCC(B) = 3.0 V to 3.6 V 7.6 11.3 14.2 7.0 15.8 17.4 ns VCC(B) = 1.1 V to 1.3 V 3.8 17.4 33.4 3.4 34.3 37.8 ns VCC(B) = 1.4 V to 1.6 V 4.0 11.1 17.7 3.5 19.1 21.1 ns VCC(B) = 1.65 V to 1.95 V 3.7 8.7 13.2 3.3 14.4 15.9 ns VCC(B) = 2.3 V to 2.7 V 3.4 6.5 9.1 3.0 10.0 11.1 ns 3.5 5.7 7.8 3.1 8.9 9.8 ns VCC(B) = 1.1 V to 1.3 V 3.6 6.5 8.1 3.5 8.5 9.4 ns VCC(B) = 1.4 V to 1.6 V 3.9 6.5 8.1 3.8 8.5 9.4 ns VCC(B) = 1.65 V to 1.95 V 4.2 6.5 8.3 4.1 8.6 9.5 ns VCC(B) = 2.3 V to 2.7 V 3.6 6.5 8.2 3.5 8.5 9.4 ns 4.5 6.5 8.2 4.2 8.9 9.8 ns VCC(B) = 1.1 V to 1.3 V 8.4 18.0 27.4 7.8 28.8 31.8 ns VCC(B) = 1.4 V to 1.6 V 7.0 12.8 17.3 6.4 18.7 20.6 ns VCC(B) = 1.65 V to 1.95 V 7.7 12.6 17.0 7.2 18.2 20.0 ns VCC(B) = 2.3 V to 2.7 V 4.8 9.1 11.6 4.5 12.4 13.7 ns VCC(B) = 3.0 V to 3.6 V 7.6 11.1 13.7 7.0 15.3 16.9 ns VCC(B) = 1.1 V to 1.3 V 3.8 16.9 32.8 3.3 33.5 36.9 ns VCC(B) = 1.4 V to 1.6 V 3.9 10.7 17.1 3.5 18.5 20.4 ns VCC(B) = 1.65 V to 1.95 V 3.7 8.3 12.7 3.3 13.9 15.4 ns VCC(B) = 2.3 V to 2.7 V 3.2 6.3 8.6 2.9 9.5 10.5 ns VCC(B) = 3.0 V to 3.6 V 3.4 5.5 7.4 3.1 8.4 9.3 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] CL = 30 pF; VCC(A) = 2.3 V to 2.7 V tpd propagation delay A to B or B to A; see Figure 6 [2] VCC(B) = 3.0 V to 3.6 V tdis disable time DIR to A; see Figure 7 [3] VCC(B) = 3.0 V to 3.6 V DIR to B; see Figure 7 [3] CL = 30 pF; VCC(A) = 3.0 V to 3.6 V tpd propagation delay A to B or B to A; see Figure 6 [2] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 20 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tdis disable time 25 °C Conditions Unit Min Max Min Max (85 °C) Max (125 °C) VCC(B) = 1.1 V to 1.3 V 5.0 9.0 11.0 4.9 11.5 12.7 ns VCC(B) = 1.4 V to 1.6 V 5.4 9.0 11.1 5.3 11.4 12.6 ns VCC(B) = 1.65 V to 1.95 V 5.9 9.0 11.3 5.7 11.6 12.8 ns VCC(B) = 2.3 V to 2.7 V 5.0 9.0 11.2 4.9 11.4 12.6 ns VCC(B) = 3.0 V to 3.6 V 6.2 9.0 11.2 5.9 11.9 13.2 ns VCC(B) = 1.1 V to 1.3 V 8.4 18.1 27.6 7.8 29.1 32.0 ns VCC(B) = 1.4 V to 1.6 V 7.0 12.8 17.3 6.4 18.6 20.6 ns VCC(B) = 1.65 V to 1.95 V 7.7 12.6 17.0 7.2 18.1 19.9 ns VCC(B) = 2.3 V to 2.7 V 4.8 9.0 11.5 4.5 12.3 13.6 ns VCC(B) = 3.0 V to 3.6 V 7.6 11.1 13.6 7.0 15.1 16.7 ns DIR to A; see Figure 7 DIR to B; see Figure 7 [3] [3] 74AUP1T45_2 Product data sheet −40 °C to +125 °C Typ[1] © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 21 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC(A) = VCC(B) = 1.2 V - 0.6 - - - - pF VCC(A) = VCC(B) = 1.5 V - 0.7 - - - - pF VCC(A) = VCC(B) = 1.8 V - 0.7 - - - - pF VCC(A) = VCC(B) = 2.5 V - 0.9 - - - - pF - 1.1 - - - - pF CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD A port; (direction A to B) [4][5] VCC(A) = VCC(B) = 3.3 V A port; (direction B to A) [4][5] VCC(A) = VCC(B) = 1.2 V - 3.7 - - - - pF VCC(A) = VCC(B) = 1.5 V - 3.8 - - - - pF VCC(A) = VCC(B) = 1.8 V - 4.0 - - - - pF VCC(A) = VCC(B) = 2.5 V - 4.6 - - - - pF - 5.2 - - - - pF VCC(A) = VCC(B) = 1.2 V - 3.7 - - - - pF VCC(A) = VCC(B) = 1.5 V - 3.8 - - - - pF VCC(A) = VCC(B) = 1.8 V - 4.0 - - - - pF VCC(A) = VCC(B) = 2.5 V - 4.6 - - - - pF - 5.2 - - - - pF VCC(A) = VCC(B) = 3.3 V B port; (direction A to B) [4][5] VCC(A) = VCC(B) = 3.3 V B port; (direction B to A) [4][5] VCC(A) = VCC(B) = 1.2 V - 0.6 - - - - pF VCC(A) = VCC(B) = 1.5 V - 0.7 - - - - pF VCC(A) = VCC(B) = 1.8 V - 0.7 - - - - pF VCC(A) = VCC(B) = 2.5 V - 0.9 - - - - pF VCC(A) = VCC(B) = 3.3 V - 1.1 - - - - pF [1] All typical values are measured at nominal VCC(A) and VCC(B). [2] tpd is the same as tPLH and tPHL. [3] tdis is the same as tPLZ and tPHZ. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [5] fi = 1 MHz; VI = GND to VCC 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 22 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 12. Waveforms VI VM A, B input GND tPLH tPHL VOH B, A output VM 001aae967 VOL Measurement points are given in Table 9. VOL and VOH are typical output voltage drops that occur with the output load. Fig 6. The data input (A, B) to output (B, A) propagation delay times VI DIR input VM GND t PLZ output LOW-to-OFF OFF-to-LOW t PZL VCCO VM VX VOL t PHZ VOH t PZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aae968 Measurement points are given in Table 9. VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. Table 9. Enable and disable times Measurement points Supply voltage Input[1] Output[2] VCC(A), VCC(B) VM VM VX VY 1.1 V to 1.6 V 0.5 × VCCI 0.5 × VCCO VOL + 0.1 V VOH − 0.1 V 1.65 V to 2.7 V 0.5 × VCCI 0.5 × VCCO VOL + 0.15 V VOH − 0.15 V 3.0 V to 3.6 V 0.5 × VCCI 0.5 × VCCO VOL + 0.3 V VOH − 0.3 V [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 23 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state VCC VEXT 5 kΩ VI G VO DUT RT CL RL 001aac521 Test data is given in Table 10. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance. VEXT = External voltage for measuring switching times. Fig 8. Table 10. Test circuit for measuring switching times Test data Supply voltage Input VCC(A), VCC(B) VI[1] Load tr = tf 1.1 V to 3.6 V VCCI ≤ 3.0 ns VEXT CL RL[2] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ[3] 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ open GND 2 × VCCO [1] VCCI is the supply voltage associated with the data input port. [2] For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. [3] VCCO is the supply voltage associated with the output port. 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 24 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 13. Application information 13.1 Unidirectional logic level-shifting application The circuit given in Figure 9 is an example of the 74AUP1T45 being used in an unidirectional logic level-shifting application. VCC1 74AUP1T45 VCC1 VCC(A) GND A VCC2 1 6 2 5 3 4 System-1 VCC2 VCC(B) DIR B System-2 001aae969 Fig 9. Unidirectional logic level-shifting application Table 11. Description unidirectional logic level-shifting application Pin Name Function Description 1 VCC(A) VCC1 supply voltage of system-1 (1.1 V to 3.6 V) 2 GND GND device ground (0 V) 3 A OUT output level depends on VCC1 voltage 4 B IN input threshold value depends on VCC2 voltage 5 DIR DIR the GND (LOW level) determines B port to A port direction 6 VCC(B) VCC2 supply voltage of system-2 (1.1 V to 3.6 V) 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 25 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 13.2 Bidirectional logic level-shifting application Figure 10 shows the 74AUP1T45 being used in a bidirectional logic level-shifting application. Since the device does not have an output enable (OE) pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. VCC1 74AUP1T45 VCC1 VCC(A) I/O-1 PULL-UP/DOWN OR BUSHOLD GND A VCC2 1 6 2 5 3 4 VCC2 VCC(B) DIR PULL-UP/DOWN OR BUSHOLD I/O-2 B DIR CTRL System-1 System-2 001aae970 System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. Fig 10. Bidirectional logic level-shifting application Table 12 gives a sequence that will illustrate data transmission from system-1 to system-2 and then from system-2 to system-1. Table 12. Description bidirectional logic level-shifting application[1][2] State DIR CTRL I/O-1 I/O-2 Description 1 H output input system-1 data to system-2 2 H Z Z system-2 is getting ready to send data to system-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on the pull-up or pull-down. 3 L Z Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on the pull-up or pull-down. 4 L input output system-2 data to system-1 [1] System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down. [2] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 26 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 13.3 Power-up considerations A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies. Take the following precautions to guard against such power-up problems: • Connect ground before any supply voltage is applied. • Power-up VCC(A). • VCC(B) can be ramped up along with or after VCC(A). 13.4 Enable times Calculate the enable times for the 74AUP1T45 using the following formulas: • • • • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the 74AUP1T45 initially is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 27 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 14. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT363 JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 11. Package outline SOT363 (SC-88) 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 28 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 12. Package outline SOT886 (XSON6) 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 29 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 4 e1 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 13. Package outline SOT891 (XSON6) 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 30 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 15. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 16. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1T45_2 20090803 Product data sheet - 74AUP1T45_1 Modifications: • Table 2 “Marking”: Changed: marking code for all packages changed from a5 to p5. 74AUP1T45_1 20061018 Product data sheet 74AUP1T45_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 31 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AUP1T45_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 3 August 2009 32 of 33 74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver; 3-state 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Application information. . . . . . . . . . . . . . . . . . 25 Unidirectional logic level-shifting application. . 25 Bidirectional logic level-shifting application. . . 26 Power-up considerations . . . . . . . . . . . . . . . . 27 Enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 28 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 31 Legal information. . . . . . . . . . . . . . . . . . . . . . . 32 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Contact information. . . . . . . . . . . . . . . . . . . . . 32 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 August 2009 Document identifier: 74AUP1T45_2