INTEGRATED CIRCUITS 74ALS109A Dual J-K positive edge-triggered flip-flop with set and reset Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset DESCRIPTION PIN CONFIGURATION The 74ALS109A is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active-Low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the Low-to-High transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation. TYPE 74ALS109A 74ALS109A TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 150MHz 3.0mA RD0 1 16 VCC J0 2 15 RD1 K0 3 14 J1 CP0 4 13 K1 SD0 5 12 CP1 Q0 6 11 SD1 Q0 7 10 Q1 GND 8 9 Q1 SF00135 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 16-pin plastic DIP 74ALS109AN SOT38-4 16-pin plastic SO 74ALS109AD SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW J0, J1 J inputs 1.0/2.0 20µA/0.2mA K0, K1 K inputs 1.0/2.0 20µA/0.2mA CP0, CP1 Clock inputs (active rising edge) 1.0/2.0 20µA/0.2mA SD0, SD1 Set inputs (active-Low) 1.0/4.0 20µA/0.4mA RD0, RD1 Reset inputs (active-Low) 1.0/4.0 20µA/0.4mA Data outputs 20/80 0.4mA/8mA Q0, Q1, Q0, Q1 NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. LOGIC SYMBOL IEC/IEEE SYMBOL 2 14 3 13 2 1J 4 J1 J0 3 K0 K1 4 CP0 5 SD0 1 5 1 RD0 12 CP1 11 SD1 15 RD1 14 13 15 6 VCC = Pin 16 GND = Pin 8 1991 Feb 08 7 10 1K 11 9 SF00136 7 R S 2J 12 Q0 Q0 Q1 Q1 6 C1 10 C2 2K 9 R S SF00137 2 853–1275 01670 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset LOGIC DIAGRAM 74ALS109A FUNCTION TABLE INPUTS SD RD CP 5, 11 1, 15 6, 10 K Q RD CP J K Q L H X X X H L Asynchronous set H L X X X L H Asynchronous reset L L X X X H* H* Undetermined* H H ↑ h l q q Toggle H H ↑ l l L H Load “0” H H ↑ h h H L Load “1” H H ↑ l h q q Hold “no change” H H L l h q q Hold “no change” 2, 14 3, 13 VCC = Pin 16 GND = Pin 8 Q OPERATING MODE SD 4, 12 7, 9 J Q OUTPUTS H = High voltage level h = High state must be present one setup time prior to Low-to-High clock transition L = Low voltage level l = Low state must be present one setup time prior to Low-to-High clock transition q = Lower case indicate the state of the referenced output prior to the Low-to-High clock transition X = Don’t care ↑ = Low-to-High clock transition * = The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the set and reset are near VIN maximum. Furthermore, this configuration is nonstable; that is, it will not remain when either set or reset returns to its inactive (High) level. SC00042 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in Low output state 16 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER UNIT MIN NOM MAX 5.0 5.5 VCC Supply voltage 4.5 VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIk Input clamp current –18 mA IOH High-level output current –0.4 mA IOL Low-level output current 8 mA +70 °C Tamb 1991 Feb 08 Operating free-air temperature range 0 3 V V Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH High-level output voltage VCC = ±10%, VIL = MAX, VIH = MIN VOL O Low level output voltage Low-level VCC = MIN,, VIL = MAX,, VIH = MIN VIK Input clamp voltage II Input current at maximum input voltage IIH High level input current High–level IIL Low level input current Low–level IO current3 LIMITS TEST CONDITIONS1 PARAMETER IOH = –0.4mA MIN TYP2 MAX VCC – 2 V IOL = 4mA 0.25 0.40 V IOL = 8mA 0.35 0.50 V –0.73 –1.5 V 0.1 mA 0.2 mA 20 µA 40 µA –0.2 mA –0.4 mA –112 mA 4.0 mA VCC = MIN, II = IIK Jn, Kn, CPn SDn, RDn VCC = MAX, MAX VI = 7 7.0V 0V Jn, Kn, CPn SDn, RDn MAX VI = 2 7V VCC = MAX, 2.7V Jn, Kn, CPn ICC Output Supply current SDn, RDn (total)4 UNIT VCC = MAX, MAX VI = 0 0.4V 4V VCC = MAX, VO = 2.25V –30 VCC = MAX 3.0 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, IOS. 4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs High in turn. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX fMAX Maximum clock frequency Waveform 1 80 MHz tPLH tPHL Propagation delay CPn to Qn or Qn Waveform 1 3.0 3.0 14.0 14.0 ns tPLH tPHL Propagation delay SDn or RD to Qn or Qn Waveform 2, 3 1.0 3.0 8.0 10.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX tsu (H) tsu (L) Setup time, High or Low Jn, Kn to CPn Waveform 1 6.0 6.0 ns th (H) th (L) Hold time, High or Low Jn, Kn to CPn Waveform 1 0.0 0.0 ns tw (H) tw (L) CPn Pulse width High or Low Waveform 1 6.0 6.0 ns tw (L) SDn or RDn Pulse width Low Waveform 2, 3 6.0 ns Recovery time, SDn or RDn to CPn Waveform 2, 3 6.0 ns trec 1991 Feb 08 4 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A AC WAVEFORMS For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. Jn, Kn VM tsu(L) VM VM tsu(H) th(L) VM th(H) 1/fmax CPn VM tw(L) VM VM tw(H) tPHL tPLH Qn VM VM tPLH tPHL VM VM Qn SC00043 Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, Clock Width, and Maximum Clock Frequency Jn, Kn SDn Jn, Kn VM tw(L) RDn VM VM tw(L) VM tREC CPn tREC CPn VM tPLH Qn tPLH Qn VM tPHL Qn VM tPHL VM Qn SC00044 VM SC00045 Waveform 2. Propagation Delay for Set to Output, Set Pulse Width and Recovery Time for Set to Clock 1991 Feb 08 VM Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width and Recovery Time for Reset to Clock 5 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop with set and reset 74ALS109A TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN CL RL AMP (V) VM 10% D.U.T. RT 90% VM VOUT PULSE GENERATOR tw 90% 10% tTHL (tff) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0.3V AMP (V) 90% Test Circuit for Totem-pole Outputs POSITIVE PULSE 90% VM VM 10% 10% tw 0.3V Input Pulse Definition DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. INPUT PULSE REQUIREMENTS Family Amplitude VM 74ALS 3.5V 1.3V Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns SC00005 1991 Feb 08 6 Philips Semiconductors Product specification Dual J-K positive edge-triggered flip-flop with set and reset DIP16: plastic dual in-line package; 16 leads (300 mil) 1991 Feb 08 7 74ALS109A SOT38-4 Philips Semiconductors Product specification Dual J-K positive edge-triggered flip-flop with set and reset SO16: plastic small outline package; 16 leads; body width 3.9 mm 1991 Feb 08 8 74ALS109A SOT109-1 Philips Semiconductors Product specification Dual J-K positive edge-triggered flip-flop with set and reset 74ALS109A DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1991 Feb 08 9