INTEGRATED CIRCUITS DATA SHEET 74AHC30; 74AHCT30 8-input NAND gate Product specification File under Integrated Circuits, IC06 1999 Nov 30 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 FEATURES DESCRIPTION • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V The 74AHC/AHCT30 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • Balanced propagation delays The 74AHC/AHCT30 provide the 8-input NAND function. • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Output capability: standard • ICC category: SSI • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS CL = 15 pF; VCC = 5 V UNIT AHC AHCT 3.6 3.3 ns tPHL/tPLH propagation delay A, B, C, D, E, F, G, H to Y CI input capacitance 3.0 3.0 pF CO output capacitance 4.0 4.0 pF CPD power dissipation capacitance 10 12 pF CL = 50 pF; f = 1 MHz; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 1999 Nov 30 2 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 FUNCTION TABLE See note 1. INPUTS OUTPUTS A B C D E F G H Y L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H Η H L Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care. ORDERING INFORMATION PACKAGES TYPE NUMBER 74AHC30D TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +125 °C 14 SO plastic SOT108-1 74AHCT30D 14 SO plastic SOT108-1 74AHC30PW 14 TSSOP plastic SOT402-1 74AHCT30PW 14 TSSOP plastic SOT402-1 PINNING PIN SYMBOL 1 A data input 2 B data input 3 C data input 4 D data input 5 E data input 6 F data input 7 GND ground (0 V) 8 Y data output 9, 10 and 13 n.c. 11 G data input 12 H data input 14 VCC 1999 Nov 30 DESCRIPTION not connected DC supply voltage 3 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 handbook, halfpage A 1 14 VCC B 2 13 n.c. C 3 D 4 E 5 F 6 9 GND 7 8 Y handbook, halfpage 12 H 11 G 30 10 n.c. n.c. 1 A 2 B 3 C 4 D 5 E 6 F 11 G 12 H Y 8 MNA488 MNA487 Fig.1 Pin configuration. Fig.2 Functional diagram. handbook, halfpage A B handbook, halfpage 1 & 2 C 3 4 D 8 5 Y 6 E 11 MNA490 12 F MNA489 G H Fig.3 IEC logic symbol. 1999 Nov 30 Fig.4 Logic diagram. 4 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC DC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature +25 +85 −40 +25 +85 °C +25 +125 −40 +25 +125 °C ns/V tr,tf (∆t/∆f) input rise and fall rates see DC and AC −40 characteristics per device −40 VCC = 3.3 ±0.3 V − − 100 − − − VCC = 5 ±0.5 V − − 20 − − 20 V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK DC input diode current VI < −0.5 V; note 1 − −20 mA IOK DC output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA IO DC output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC DC VCC or GND current − ±75 mA Tstg storage temperature −65 +150 °C PD power dissipation per package − 500 mW for temperature range from −40 to +125 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO-packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP-packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. 1999 Nov 30 5 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 DC CHARACTERISTICS Family 74AHC Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage −40 to +85 25 PARAMETER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 1.5 − − 1.5 − 1.5 − V 3.0 2.1 − − 2.1 − 2.1 − V 5.5 3.85 − − 3.85 − 3.85 − V 2.0 − − 0.5 − 0.5 − 0.5 V 3.0 − − 0.9 − 0.9 − 0.9 V 5.5 − − 1.65 − 1.65 − 1.65 V VI = VIH or VIL IO = −50 µA 2.0 1.9 2.0 − 1.9 − 1.9 − V IO = −50 µA 3.0 2.9 3.0 − 2.9 − 2.9 − V IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V IO = −4.0 mA 3.0 2.58 − − 2.48 − 2.40 − V IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V VI = VIH or VIL IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 V IO = 50 µA 3.0 − 0 0.1 − 0.1 − 0.1 V IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V IO = 4.0 mA 3.0 − − 0.36 − 0.44 − 0.55 V IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 2.0 − 20 − 40 µA CI input capacitance − − 3 10 − 10 − 10 pF 1999 Nov 30 6 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 Family 74AHCT Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output voltage IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V IO = 8.0 mA 4.5 − − 0.36 − 0.44 − 0.55 V − 1.0 − 2.0 µA ±2.5 − ±10.0 µA VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VIH or VIL 5.5 − − 0.1 IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 − ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 2.0 − 20 − 40 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V; other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF 1999 Nov 30 − 7 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 AC CHARACTERISTICS Type 74AHC30 GND = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. see Figs 5 and 6 15 pF − 5.0 9.5 1.0 11.0 1.0 12.0 ns 50 pF − 6.7 12.0 1.0 14.5 1.0 15.5 ns see Figs 5 and 6 15 pF − 3.6 6.5 1.0 7.5 1.0 8.0 ns 50 pF − 4.9 8.0 1.0 9.5 1.0 10.5 ns VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay A, B, C, D, E, F, G, H to Y VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay A, B, C, D, E, F, G, H to Y Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. Type 74AHCT30 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 WAVEFORMS CL MIN. −40 to +125 UNIT TYP. MAX. MIN. MAX. MIN. MAX. see Figs 5 and 6 15 pF − 3.3 6.5 1.0 7.5 1.0 8.0 ns 50 pF − 4.7 8.5 1.0 9.5 1.0 10.5 ns VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay A, B, C, D, E, F, G, H to Y Note 1. Typical values at VCC = 5.0 V. 1999 Nov 30 8 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 AC WAVEFORMS handbook, halfpage A, B, C, D, E, F, G, H input VM t PHL t PLH VM Y output MNA491 VI INPUT REQUIREMENTS FAMILY VM INPUT VM OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.5 The input (A, B, C, D, E, F, G and H) to output (Y) propagation delays. S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO VCC open GND D.U.T. CL RT MNA183 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit: CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”); RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Test circuitry for switching times. 1999 Nov 30 9 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.050 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06S MS-012AB 1999 Nov 30 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 10 o 8 0o Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 1999 Nov 30 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 MO-153 11 o Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Nov 30 12 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Nov 30 13 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 NOTES 1999 Nov 30 14 Philips Semiconductors Product specification 8-input NAND gate 74AHC30; 74AHCT30 NOTES 1999 Nov 30 15 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245002/01/pp16 Date of release: 1999 Nov 30 Document order number: 9397 750 06465