SC4525C 28V 3A Step-Down Switching Regulator POWER MANAGEMENT Features Description Wide input range: 3V to 28V 3A Output Current 200kHz to 2MHz Programmable Frequency Precision 1V Feedback Voltage Peak Current-Mode Control Cycle-by-Cycle Current Limiting Hiccup Overload Protection with Frequency Foldback Soft-Start and Enable Thermal Shutdown Thermally Enhanced 8-pin SOIC Package Fully RoHS and WEEE compliant Applications XDSL and Cable Modems Set Top Boxes Point of Load Applications CPE Equipment DSP Power Supplies LCD and Plasma TVs The SC4525C is a constant frequency peak current-mode step-down switching regulator capable of producing 3A output current from an input ranging from 3V to 28V. The switching frequency of the SC4525C is programmable up to 2MHz, allowing the use of small inductors and ceramic capacitors for miniaturization, and high input/ output conversion ratio. The SC4525C is suitable for next generation XDSL modems, high-definition TVs and various point of load applications. Peak current-mode PWM control employed in the SC4525C achieves fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. Soft-start function reduces input startup current and prevents the output from overshooting during power-up. The SC4525C is available in SOIC-8 EDP package. SC4525A Typical Application Circuit Efficiency 90 D1 C4 4.7mF 1N4148 C1 0.33mF L1 BST IN SW 5.2mH SC4525C SS/EN 80 OUT R4 33.2k 5V/3A FB COMP C7 22nF C8 22pF ROSC R7 12.7k GND R5 15.8k D2 20BQ030 R6 8.25k C5 2.2nF C2 10mFX3 Efficiency (%) 10V– 28V V IN 70 60 50 40 0.0 L1: Coiltronics CD1- 5R2 VIN = 24V VIN = 12V 0.5 C2: Murata GRM31CR60J106K C4: Murata GRM32ER71H475K 1.0 1.5 2.0 2.5 3.0 Load Current (A) Figure 1. 1MHz 10V -28V to 5V/3A Step-down Converter Jan. 13, 2011 Efficiency of the 1MHz 10V-28V to 5V/3A Step-Down Conve SC4525C Pin Configuration Ordering Information SW 1 8 BST IN 2 7 FB ROSC 3 6 COMP GND 4 5 SS/EN 9 Device Package SC4525CSETRT(1)(2) SOIC-8 EDP SC4525CEVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. (8 - Pin SOIC - EDP) Marking Information yyww=Date code (Example: 0752) xxxxx=Semtech Lot No. (Example: E9010) SC4525C Absolute Maximum Ratings Thermal Information VIN Supply Voltage ……………………………… -0.3 to 32V Junction to Ambient (1) ……………………………… 36°C/W BST Voltage ……………………………………………… 42V Junction to Case (1) ………………………………… BST Voltage above SW …………………………………… 34V Maximum Junction Temperature……………………… 150°C 5.5°C/W Storage Temperature ………………………… -65 to +150°C SS Voltage ……………………………………………-0.3 to 3V FB Voltage …………………………………………… -0.3 to VIN SW Voltage ………………………………………… -0.6 to VIN Lead Temperature (Soldering) 10 sec ………………… 300°C Recommended Operating Conditions SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V Input Voltage Range ……………………………… 3V to 28V Peak IR Reflow Temperature …………………………. Maximum Output Current ……………………………… 3A 260°C ESD Protection Level ………………………………… 2000V (2) Operating Ambient Temperature …………… -40 to +105°C Operating Junction Temperature …………… -40 to +125°C Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, ROSC = 12.1kΩ. Parameter Conditions Min Typ Max Units 28 V 2.95 V Input Supply Input Voltage Range VIN Start Voltage 3 VIN Rising 2.70 VIN Start Hysteresis VIN Quiescent Current VIN Quiescent Current in Shutdown 2.82 225 mV VCOMP = 0 (Not Switching) 2 2.6 mA VSS/EN = 0, VIN = 12V 40 52 µA 1.000 1.020 V Error Amplifier Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current 0.980 VIN = 8V to 28V 0.005 VFB = 1V, VCOMP = 0.8V -170 %/V -340 nA Error Amplifier Transconductance 300 µΩ-1 Error Amplifier Open-loop Gain 60 dB 15.2 A/V VFB = 0.9V 2.35 V COMP Source Current VFB = 0.8V, VCOMP = 0.8V 17 COMP Sink Current VFB = 1.2V, VCOMP = 0.8V 25 COMP Pin to Switch Current Gain COMP Maximum Voltage µA Internal Power Switch Switch Current Limit Switch Saturation Voltage (Note 1) ISW = -3.9A 3.9 5.1 6.6 A 380 600 mV SC4525C Electrical Characteristics (Cont.) Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, ROSC = 12.1kΩ. Parameter Conditions Min Typ Minimum Switch On-time 150 Minimum Switch Off-time 100 Switch Leakage Current Max Units ns 150 ns 10 µA Minimum Bootstrap Voltage ISW = -3.9A 1.8 2.3 V BST Pin Current ISW = -3.9A 100 150 mA Oscillator Switching Frequency Foldback Frequency ROSC = 12.1kΩ 1.04 1.3 1.56 MHz ROSC = 73.2kΩ 230 300 370 kHz ROSC = 12.1kΩ, VFB = 0 100 ROSC = 73.2kΩ, VFB = 0 35 60 90 0.2 0.3 0.4 V 0.95 1.2 1.4 V 250 kHz Soft Start and Overload Protection SS/EN Shutdown Threshold SS/EN Switching Threshold Soft-start Charging Current VFB = 0 V VSS/EN = 0 V VSS/EN = 1.5 V 1.9 1.6 Soft-start Discharging Current 2.4 3.2 µA 1.5 µA Hiccup Arming SS/EN Voltage VSS/EN Rising 2.15 V Hiccup SS/EN Overload Threshold VSS/EN Falling 1.9 V Hiccup Retry SS/EN Voltage VSS/EN Falling 0.6 1.0 1.2 V Over Temperature Protection Thermal Shutdown Temperature 165 °C Thermal Shutdown Hysteresis 10 °C Note 1: Switch current limit does not vary with duty cycle. SC4525C Pin Descriptions SO-8 Pin Name Pin Function 1 SW Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. 2 IN Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane. 3 ROSC An external resistor from this pin to ground sets the oscillator frequency. 4 GND Ground pin 5 SS/EN Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off the regulator to low current state. 6 COMP The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator. 7 FB The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to improve short-circuit robustness (see Applications Information for details). 8 BST Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than VIN in order to fully enhance the internal NPN power transistor. 9 Exposed Pad The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the PC board. SC4525C Block Diagram IN SLOPE COMP COMP 6 FB 7 + 2 S + + ISEN 3.53m W + EA + + ILIM - OC 18mV BST V1 8 + PWM - S R FREQUENCY FOLDBACK ROSC Q POWER TRANSISTOR CLK OSCILLATOR 3 1.2V 1 R SW OVERLOAD - PWM A1 + R SS/EN 5 1V SOFT- START AND OVERLOAD HICCUP CONTROL 1.9V REFERENCE & THERMAL SHUTDOWN FAULT GND 4 Figure 2. SC4525C Block Diagram 1.9V SS/EN IC 2.4mA B4 + Q B1 OVERLOAD R 1V/2.15V FAULT S ID 3.9mA B2 _ Q S OC R PWM B3 Figure 3. Soft-start and Overload Hiccup Control Circuit (2) 24Vin Eff Curve 3 Typical Characteristics SC4525A SS270 REV 6-7 85 V O=3.3V 80 65 V O=1.5V 60 55 Curve 5 45 50 VIN =12V 1.01 V O=3.3V 75 Efficiency (%) 70 1.02 V O=5V 80 V O=2.5V 75 Feedback Voltage vs Temperature Efficiency 90 VO=5V 85 Efficiency (%) SC4525A Efficiency 90 SC4525C V O=2.5V 70 VFB (V) ff 65 60 55 1MHz, VIN=12V D2 =B320A Curve 6 45 50 40 1MHz, VIN=24V 0.5 1 1.5 2 2.5 0.97 0 3 0.5 Load Current (A) SS270 REV 6-7 1 1.5 2 2.5 3 -50 Frequency Setting Resistor vs Frequency (8) OCP current 1 0.25 0.5 0.75 1 1.25 1.5 1.75 2 100 125 Foldback Frequency vs VFB 1.1 ROSC =73.2k 1.0 ROSC =12.1k (9) BST Pin current 0.9 0.8 -50 -25 0 25 50 75 1 0.75 ROSC =73.2k 0.5 TA=25oC 0.25 ROSC =12.1k 0 0.00 100 125 0.20 0.40 Temperature (OC) 0.60 0.80 1.00 VFB (V) SS270 REV 6-7 500 Switch Saturation Voltage vs Switch Current Switch Current Limit vs Temperature BST Pin Current vs Switch Current 100.0 5.2 VIN =12V 450 25oC o -40 C 200 150 BST Pin Current (mA) 300 Current Limit (A) 350 250 V BST-SW =5V 4.8 125oC 400 VCESAT (mV) 75 1.25 1.2 Frequency (MHz) SS270 REV 6-7 50 Temperature ( C) Normalized Frequency 10 25 SS270 REV 6-7 Frequency vs Temperature Normalized Frequency ROSC (k) 100 0 o VIN =12V 0 -25 Load Current (A) SS270 REV 6-7 1000 0.99 0.98 D 2 =B330A 40 0 1.00 4.4 4.0 3.6 75.0 -40oC 50.0 125oC 25.0 100 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Switch Current (A) 0.0 3.2 -50 -25 0 25 50 75 Temperature (oC) 100 125 0 0.5 1 1.5 2 2.5 3 3.5 4 Switch Current (A) SC4525C Curve 12 Curve 11 Typical Characteristics (Cont.) SS270 REV 6-7 SS270 REV 6-7 SS270 REV 6-7 VIN Supply Current vs Soft-Start Voltage VIN Thresholds vs Temperature 2.5 2.8 2.7 2.6 80 -40oC 1.5 1.0 Curve 14 2.5 0.5 2.4 0.0 60 -40oC -25 0 20 Curve 15 25 50 75 0 100 125 0.5 o 0 1 1.5 SS270 REV 6-7 5 10 20 25 30 Soft-Start Charging Current vs Soft-Start Voltage SS Shutdown Threshold vs Temperature 0.40 125oC 15 VIN (V) SS270 REV 6-7 VIN Quiescent Current vs VIN 2.5 0 2 VSS (V) Temperature ( C) SS270 REV 6-7 125oC 40 UVLO -50 0.0 -0.5 o SS Threshold (V) -40 C 1.5 1.0 0.5 0.35 Current (uA) 2.0 Current (mA) VSS = 0 125oC 2.0 Current (mA) VIN Threshold (V) 2.9 Start Current (uA) 3.0 VIN Shutdown Current vs VIN 100 0.30 15 VIN (V) 20 25 -2.0 -3.0 0.20 10 -40oC -1.5 -2.5 0.0 5 125oC 0.25 VCOMP = 0 0 -1.0 30 -50 -25 0 25 50 75 o Temperature ( C) 100 125 0 0.5 1 1.5 2 VSS (V) SC4525C Applications Information Operation The SC4525C is a constant-frequency, peak current-mode, step-down switching regulator with an integrated 28V, 3.9A power NPN transistor. Programmable switching frequency makes the regulator design more flexible. With the peak current-mode control, the double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop. This simplifies loop compensation and achieves fast transient response with a simple Type-2 compensation network. As shown in Figure 2, the switch collector current is sensed with an integrated 3.53mW sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifier (EA) output. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed signal exceeds the 18mV current-limit threshold. Driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C1 and the diode D1 in Figure 1) generates such a voltage at the BST pin for driving the power transistor. When the SS/EN pin is released, the soft-start capacitor is charged with an internal 1.9µA current source (not shown in Figure 3). As the SS/EN voltage exceeds 0.4V, the internal bias circuit of the SC4525C turns on and the SC4525C draws 2mA from VIN. The 1.9µA charging current turns off and the 2.4µA current source IC in Figure 3 slowly charges the soft-start capacitor. The error amplifier EA in Figure 2 has two non-inverting inputs. The non-inverting input with the lower voltage predominates. One of the non-inverting inputs is biased to a precision 1V reference and the other non-inverting input is tied to the output of the amplifier A1. Amplifier A1 produces an output V1 = 2(VSS/EN -1.2V). V1 is zero and COMP is forced low when VSS/EN is below 1.2V. During start up, the effective non-inverting input of EA stays at zero until the soft-start capacitor is charged above 1.2V. Once VSS/ exceeds 1.2V, COMP is released. The regulator starts to EN switch when VCOMP rises above 0.4V. If the soft-start interval is made sufficiently long, then the FB voltage (hence the output voltage) will track V1 during start up. VSS/EN must be at least 1.83V for the output to achieve regulation. Proper soft-start prevents output overshoot. Current drawn from the input supply is also well controlled. Overload / Short-Circuit Protection Table 2 lists various fault conditions and their corresponding protection schemes in the SC4525C. Shutdown and Soft-Start Table 2: Fault conditions and protections The SS/EN pin is a multiple-function pin. An external capacitor (4.7nF to 22nF) connected from the SS pin to ground sets the soft-start and overload shutoff times of the regulator (Figure 3). The effect of VSS/EN on the SC4525C is summarized in Table 1. Table 1: SS/EN operation modes SS/EN Mode Supply Current <0.2V Shutdown 18uA @ 5Vin 0.4V to 1.2V Not switching 2mA 1.2V to 2.15V Switching & hiccup disabled >2.15V Switching & hiccup armed Load dependent Pulling the SS/EN pin below 0.2V shuts off the regulator and reduces the input supply current to 18µA (VIN = 5V). Condition Cause of Fault Protective Action Cycle-by-cycle limit at IL>ILimit, V FB>0.8V Over current IL>ILimit, V FB<0.8V Over current VSS/EN Falling Persistent over current frequency foldback Shutdown, then retry SS/EN<1.9V or short circuit (Hiccup) Tj>160C Over temperature Shutdown programmed frequency Cycle-by-cycle limit with As summarized in Table 1, overload shutdown is disabled during soft-start (VSS/EN<2.15V). In Figure 3, the reset input of the overload latch B2 will remain high if the SS/EN voltage is below 2.15V. Once the soft-start capacitor is charged above 2.15V, the output of the Schmitt trigger B1 goes high, the reset input of B2 goes low and hiccup SC4525C Applications Information (Cont.) Table 3: Resistor for Typical Switching Frequency If the FB voltage falls below 0.8V because of output overload, then the switching frequency will be reduced. Frequency foldback helps to limit the inductor current when the output is hard shorted to ground. Fig.4 During normal operation, the soft-start capacitor is charged to 2.4V. Setting the Output Voltage The regulator output voltage, VO, is set with an external resistive divider (Figure 1) with its center tap tied to the FB pin. For a given R6 value, R4 can be found by V R 4 = R 6 O − 1 1 .0 V (1) VO + VD Frequency SettingDthe = Switching VIN + VD − VCESAT The switching frequency of the SC4525C is set with an external resistor from the ROSC pin to ground. Table 3 lists the standard(resistor V + VD )values ⋅ (1 − Dfor ) typical frequency setting. DIL = O FSW ⋅ L 1 L1 = ( VO + VD ) ⋅ (1 − D) 20 % ⋅ IO ⋅ FSW Freq. (k) ROSC (k) Freq. (k) ROSC (k) Freq. (k) ROSC (k) 200 110 700 25.5 1400 9.76 250 84.5 800 21.5 1500 8.87 300 69.8 900 18.2 1600 8.06 350 57.6 1000 15.8 1700 7.15 400 49.9 1100 14.0 1800 6.34 500 38.3 1200 12.4 1900 5.62 600 30.9 1300 11.0 2000 5.23 Minimum On Time Consideration AC = V The operating duty cycle of a non-synchronous stepR 4 = R 6 O − 1 down switching in continuous-conduction 1 . 0 Vregulator mode (CCM) is given by VO + VD D= VIN + VD − VCESAT AC = (2) where VIN is the input voltage, VCESAT is the switch saturation voltage, and VD is voltage drop across the rectifying diode. DI = ( VO + VD ) ⋅ (1 − D) L FSW ⋅ L 1 In peak current-mode control, the PWM modulating ramp is the( Vsensed + V ) ⋅ current (1 − D) ramp of the power switch. L1 = O D This current ramp is unless the switch is turned 20 % ⋅ IO ⋅absent FSW on. The intersection of this ramp with the output of the voltage feedback error amplifier determines the switch pulse Iwidth. The propagation delay time required to RMS _ CIN = I O ⋅ D ⋅ (1 − D) immediately turn off the switch after it is turned on is the SS270 REV 6-7 minimum controllable switch on time (TON(MIN)). R7 = C5 = C8 = Vo = Vc GPWM Minumum On Time 1vs Temperature DVO200 = DIL ⋅ ESR + 8 ⋅ FSW ⋅ C O V =1.5V, I =1A, 1MHz 180 O O1 V 1 R7 = AC = − 20 ⋅ log ⋅ ⋅ FB G R 2 π F C V C O O 160 CA S IO C IN > C5 = 4 ⋅ DVIN ⋅ F1SW 1 1 .0 140 AC = − 20 ⋅ log ⋅ ⋅ = 15 28 ⋅ 6 . 1 ⋅ 10 − 3 2 π ⋅ 80 ⋅ 10 3 ⋅ 22 ⋅ 10 −6 3 . 3 C8 = 120 TON_MIN (ns) becomes armed. As the load draws more current from the regulator, the current-limit comparator ILIM (Figure 2) will eventually limit the switch current on a cycle-bycycle basis. The over-current signal OC goes high, setting the latch B3. The soft-start capacitor is discharged with (ID - IC) (Figure 3). If the inductor current falls below the current limit and the PWM comparator instead turns off the switch, then latch B3 will be reset and IC will recharge the soft-start capacitor. If over-current condition persists or OC becomes asserted more often than PWM over a period of time, then the soft-start capacitor will be discharged below 1.9V. At this juncture, comparator B4 sets the overload latch B2. The soft-start capacitor will be continuously discharged with (ID - IC). The COMP pin is immediately pulled to ground. The switching regulator is shut off until the soft-start capacitor is discharged below 1.0V. At this moment, the overload latch is reset. The soft-start capacitor is recharged and the converter again undergoes soft-start. The regulator will go through softstart, overload shutdown and restart until it is no longer overloaded. 15 . 9 20 10100 R7 = = 22 . 3 k 0 . 28 ⋅ 10-50−3 -25 0 25 50 O 75 100 125 Temperature ( C) 1 C5 = = 0 . 45 nF 2 π ⋅ 16 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 Figure 4. Variation of Minimum On Time 1with Ambient Temperature C8 = = 12pF 2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 10 1 .0 V V R4 = R6 O − 1 V + V 1 . 0 V O D D= VIN + VD − VCESAT VO + VD D= VIN + VD − VCESAT ( V + VD ) ⋅ (1 − D) DIL = O FSW ⋅ L 1 SC4525C is 3.9A minus one half of the inductor ripple ( V + VD ) ⋅ (1 − D) current. DIL = O ( V + FVD ) ⋅⋅(L11− D) L 1 = O SW 20 % ⋅ ICapacitor O ⋅ FSW Input Decoupling ( V + V ) ⋅ (1 − D) L1 = O D The input capacitor 20 % ⋅ IOshould ⋅ FSW be chosen to handle the RMS I = I ⋅ D ⋅ converter. (1 − D) RMS _ CIN O ripple current of a buck This value is given by SC4525C Applications Information (Cont.) Closed-loop measurement shows that the SC4525C minimum on time is about 120ns at room temperature (Figure 4). If the required switch on time is shorter than the minimum on time, the regulator will either skip cycles or it will jitter. To allow for transient headroom, the minimum operating switch on time should be at least 20% to 30% higher than the worst-case minimum on time. Minimum Off Time Limitation The PWM latch in Figure 2 is reset every cycle by the clock. The clock also turns off the power transistor to refresh the bootstrap capacitor. This minimum off time limits the attainable duty cycle of the regulator at a given switching frequency. The measured minimum off time is 100ns typically. If the required duty cycle is higher than the attainable maximum, then the output voltage will not VOits−set be able R 4 to = Rreach 1 value in continuous-conduction 6 1 .0 V mode. Inductor Selection VO + VD D= VIN + VD − VCESAT The inductor ripple current for a non-synchronous stepdown converter in continuous-conduction mode is (V V + V ) ⋅ (1 − D) RD4IL==R 6 O O D− 1 V ⋅ L 1 1 . 0FSW (3) where FSW is the switching frequency and L1 is the ( V V+ V+ )V⋅ (1 − D) inductance. LD1== O O D D ⋅ I ⋅ FSW VIN 20 + V% D −OVCESAT An inductor ripple current between 20% to 50% of the maximum load current, IO, gives a good compromise ⋅ )D⋅ (and ⋅1(1−−D D _ CIN amongIRMS efficiency, size. ( VO= I+O Vcost ) ) Re-arranging Equation (3) D D I = L and assuming 35% ripple current, the inductor is FSWinductor ⋅ L1 given by D ) ⋅ (1 − D) 1 (V + V LD1VO= = DOIL ⋅ ESR + 35 % ⋅ IO ⋅ FSW8 ⋅ FSW ⋅ C O (4) If the input voltage varies over a wide range, then choose L1 based on the nominal input voltage. Always verify IRMS _ CIN = I O ⋅ D ⋅ (1 − D) converter operation at the input voltage extremes. IO C IN > 4 ⋅ DV ⋅ F The peak current INlimitSWof SC4525C power transistor is at least 3.9A. The maximum deliverable load current for the 1 DVO = DIL ⋅ ESR + 8 ⋅ FSW ⋅ C O IRMS _ CIN = I O ⋅ D ⋅ (1 − D) (5) 1 DVOcapacitance = DIL ⋅ ESR must + The input also be high enough to keep 8 ⋅ FSW ⋅ C O input ripple voltage within specification. This is important 1 from in reducing EMI ESR + the regulator. The DVO = the DIL ⋅conductive ⋅ FSW ⋅ C O from input capacitance can be8estimated AC = AC = R7 = RC75 == CC5 == 8 C8 = Vo = Vc Vo = Vc GPWM GPWM R7 = AC = VIO RC7 == (6) RC4IN=>R 6 O − 1 5 4⋅1D.V ⋅ F 0INV SW AC = IO 1 inputVripple FB is the 1allowable voltage. CDV >log Awhere ⋅ ⋅ C IN ⋅IN C = − 20 C58 == 4⋅ V DCA VINRV⋅SFSW2 πFC C O VO G O + D D= Multi-layerVceramic capacitors, which have very low ESR IN + VD − VCESAT 1 handle high RMS1 ripple current, 1 . 0 C 8 = (a few mW) and can easily AC = − 20 ⋅ log ⋅ ⋅ = R=7 15 −3 3 −6 are the ideal choice 3 .3 28 ⋅ 6 . 1for ⋅ 10input2 πfiltering. ⋅ 80 ⋅ 10 A ⋅ single 22 ⋅ 10 4.7µF X5R ceramic( Vcapacitor is adequate for 500kHz or higher O + VD ) ⋅ (1 − D) DIL =frequency switching applications, and 10µF is adequate C 5 = 15 . 9 FSW ⋅ L 1 for 200kHz 500kHz switching For high 10 20 to = V frequency. 122 . 3 k 1 R7 = Avoltage −. 28 20applications, ⋅⋅ 10 log−3 ⋅ FB (1µF or 2.2µF) can be a⋅ small ceramic C =0 C8 = R 2 πDF)C C O VO ( VO G +CA Vwith D )S⋅ (1a−low placedLin parallel ESR electrolytic capacitor to = 1 1 203ESR % ⋅ IOand ⋅ FSWbulk Csatisfy = 0 . 45 nF 5 = both the 3 capacitance requirements. 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 1 1 1 .0 AC = − 20 ⋅ log ⋅ ⋅ = 15 −3 3 −6 3 . 3 Vo 28 ⋅ 6 . 1 ⋅ 10 2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 1 Output Capacitor = C8 = I = I O3 ⋅⋅ 22D.⋅1(1⋅ 10 − D3 ) = 12pF Vc _ CIN⋅ 10 2 πRMS ⋅ 600 The output15 .9ripple voltage DVO of a buck converter can be 10 20as Rexpressed = 22 . 3 k 7 = − 3 (1 + s R GPWM Vo 0 . 28 ⋅ 10 ESR C O ) GPWM = 21 2 D V = D I ⋅ ESR + V ( 1 + s / ω ) ( 1 + s / ω Q + s / ω ) (7) O c p L1 n n 8 ⋅3FSW C5 = = 0⋅.C 45O nF 3 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 where CO is the output capacitance. R7 = R 1 1 1 G ≈ , 3 ωp ≈ 3 = 12 , pF ωZ = , CPWM 8 = ⋅ Rinductor R ESR C O ⋅CA 600 . 1 ⋅ 10 R C O S⋅ 10 ⋅ 22 Since2 πG the IO ripple current DIL increases as D C IN >(Equation (3)), the output ripple voltage is C 5 = decreases AC 4 ⋅ DVIN ⋅ FSW therefore when V is at its maximum. 10 20 the highest RV7o = GPWM (1 + s R ESR C O )IN = gm 2 VAc 22µF (1 +to s /47µF ωp )(1X5R + s ceramic / ωn Q + scapacitor / ωn2 ) is found adequate C 8 = 1 output filtering in most applications. Ripple current Cfor 5 = 2 πFoutput Z1 R 7 in the capacitor is not R 1 a concern because1 the Ginductor ≈ , ω ≈ , ωZ =feeds C ,, current of a buck converter directly PWM p 1 RCO R ESR C OO C 8 = GCA ⋅ R S 2 πFP1 R 7 AC R = 10 20 11 SC4525C Applications Information (Cont.) Freewheeling Diode Use of Schottky barrier diodes as freewheeling rectifiers reduces diode reverse recovery input current spikes, easing high-side current sensing in the SC4525C. These diodes should have an average forward current rating at least 3A and a reverse blocking voltage of at least a few volts higher than the input voltage. For switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher average current ratings (thus lower forward voltages). This is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. Fig 5 The freewheeling diode should be placed close to the SW pin of the SC4525C to minimize ringing due to trace inductance. 20BQ030 (International Rectifier), B320A, B330A (Diodes Inc.), SS33 (Vishay), CMSH3-20MA and CMSH3-40MA (Central-Semi.) are all suitable. For the bootstrap circuit, a fast switching PN diode (such as 1N4148 or 1N914) and a small (0.33µF – 0.47µF) ceramic capacitor is sufficient for most applications. When bootstrapping from 2.5V to 3.0V output voltages, use a low forward drop Schottky diode (BAT-54 or similar) for D1. When bootstrapping from high input voltages (>20V), reduce the maximum BST voltage by connecting a Zener diode (D3) in series with D1 as shown in Figure 6 (b). If VOUT > 8V, then a protection diode D4 between the SW and the BST pins will be required as shown in Figure 6 (c). D4 can be a small PN diode such as 1N4148 or 1N914 if the operating temperature does not exceed 85 ºC. Use a small Schottky diode (BAT54 or similar) if the converter is to SS270 REV 6-7 operate up to 125 ºC. Minimum Bootstrap Voltage vs Temperature 2.2 2.1 Voltage (V) resulting in very low ripple current. Avoid using Z5U and Y5V ceramic capacitors for output filtering because these types of capacitors have high temperature and high voltage coefficients. 2.0 1.9 1.8 ISW =-3.9A 1.7 1.6 The freewheeling diode should be placed close to the SW pin of the SC4525C on the PCB to minimize ringing due to trace inductance. Bootstrapping the Power Transistor The minimum BST-SW voltage required to fully saturate the power transistor is shown in Figure 5, which is about 2V at room temperature. -50 -25 0 50 75 100 125 o Temperature ( C) Figure 5. Typical Minimum Bootstrap Voltage required to Saturate the Transistor (ISW= -3.9A) D1 BST C1 VIN VOUT SW IN The BST-SW voltage is supplied by a bootstrap circuit powered from either the input or the output of the converter (Figure 6(a), 6(b) and 6(c)). To maximize efficiency, tie the bootstrap diode to the converter output if VO>2.5V as shown in Figure 6(a). Since the bootstrap supply current is proportional to the converter load current (Equation (10), page 14), using a lower voltage to power the bootstrap circuit reduces driving loss and improves efficiency. 25 SC4525C D2 GND (a) Figure 6(a). Bootstrapping the SC4525C from the Converter Output 12 SC4525C Applications Information (Cont.) VFB 11 V 11 FB AC = =diagram − 20 20 ⋅⋅ log log The block inFigure 7⋅⋅shows the⋅⋅ control loops of a A − C G CAR R S 22 π πFFC C CO V VO G S CThe O inner O loop (current CASC4525C. buck converter with the VO C1 V O −1 R4 = =R R 6BST loop) consists of a current sensing resistor (Rs=3.53mW) R − 1 4 6 1 . 0 V 1 .0 1 .0 V 11 with gain 11 The VIN VOUT and a A (CA) (GCA=18.5). Acurrent =− − 20 20amplifier log ⋅ ⋅ 1 .0 C = SW ⋅⋅ log IN −33 ⋅ 3 −66 ⋅ C − 3 − 28 ⋅⋅ 66consists 10 of22an π ⋅⋅ 80 80 10amplifier 22 ⋅⋅ 10 10 28 33 ..3 ..11 ⋅⋅ 10 π ⋅⋅ 10 ⋅⋅ 22 error 1 VFB outer loop (voltage loop) 1 SC4525C V + V D ⋅ ⋅ O C+ = VA VDD− 20 ⋅2log (EA), a PWM modulator, and a LC filter. O D= = GND D G CAR S 2 πFC C O VO V + V − V IN + VD D − VCESAT CESAT VIN 15 . 9 .9 10 152020loop 10 Since the current is= internally closed, the remaining R = 22 . 3 k 7 R7 = −33 = 22 . 3 k 1 1 1 . 0 − (b) 0 . 28 ⋅ 10 compensation . 28 AC = − 20 ⋅ logD1 ⋅ 1task 3for the = 15 . 9 dB is to design the voltage V ⋅⋅10 1 0loop −3 −6 D4 3,. 3and 2 π⋅ 80compensator ⋅ 10⋅ ⋅ 22 ⋅ 10(C A.C1=⋅ 10 − 20 ⋅ log ⋅ FB , R (( V VO + +V VD )) ⋅⋅ ((11 − −D D)) 28 ⋅ 6 7 11 C8). 5 G R 2 π F C V O D C = = 00 ..45 45nF nF D I = CA S C O O 5 33 C5 = = DILL = 2π π ⋅⋅ 16 16 ⋅⋅ 10 10 ⋅⋅ 22 22 ..11 ⋅⋅ 10 10 33 FSW ⋅⋅ LL 1 VO 2 BST FSW 1 C1 = R6 −1 For a converter with switching frequency FSW, output 15 . 9 1 .0 V VIN 20 1 1 . 0 loading R, the VOUT>8V 10 111 C3O⋅ = C 8 −= =3 L⋅ 1, output capacitance =and 12pF pF AC. 3=k − 20 ⋅ log inductance = 15 . 9 dB SW R = = 22 IN ( V + C 12 3 V ) ⋅ ( 1 − D ) 3 − 6 7 8 − 3 3 ⋅⋅ 22 3 3 .3 ( VOO + VDD ) ⋅0(1. 28 − D⋅)10 ππ ⋅output 600 10 ⋅ 10 10function ⋅ 6 . 1 ⋅ 10(V ) 22to2π ⋅ 80 ⋅⋅⋅10 10 22..11 ⋅ 10 28 control =SC4525C ⋅ 600 ⋅ 22 ⋅ (V ) transfer in Figure 7 is LL11 = C O 20 % % ⋅⋅ IIO ⋅⋅ FFSWD2 VO + VD 20 O SW given by: 1 GND C5 = = 0 . 45 nF 3 3 VIN + VD − VCESAT 15 . 9 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 20 GPWM ((11 + + ss R R ESR C C O )) Vo G V 10 PWM ESR O o = (8) = IIRMS _ CIN = = II O ⋅⋅ D D ⋅⋅ ((11 − −D D)) 1 R 7 = 0 . 28 ⋅ 10 −3 = 22 . 3 k V Vc ((11 + + ss // ω ωp ))((11 + + ss // ω ωn Q Q + s 22 / ωn22 )) RMS _ CINa pnC O = diode or a Schottky diode c p n + s / ωn = 12 pF D4 is either juntion 8 depending on the operating temperature. 2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10 3 1 This transfer function has a finite DC gain ( VO + VD ) ⋅ (1 − D) (C) C5 = = 0 . 45 nF = 3 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 FSW ⋅ L 1 R 1 1 GPWM ≈ ≈ R ,, ωp ≈ ≈ 1 ,, ωZ = = 1 ,, G ω ω 1 PWM p Z 1 (1 +s R ESR C O ) GCA ⋅⋅ R RS RC CO R ESR C CO 1 G R R DV VO = =D DIIL VMethods ⋅o ESR + ofGPWM = CA S O ESR O D Figure 6(b) and Bootstrapping the 2 3 = + O (c). L ⋅ ESR C = 12 pF 8 ⋅ F ⋅ C 8 2 3 ( V + V ) ⋅ ( 1 − D ) SW)(1 ⋅ C+OOs/ ωn2Qπ+⋅ 600 ) D Vc (1 + s8 /⋅ FωSW s /ω ⋅ 10 ⋅ 22 . 1 ⋅ 10 p n) = O SC4525C AC AC 20 20 % ⋅ IO ⋅ FSW 10 20 10 an ESRRzero F at = Z R 77 = gm Loop Compensation g R (1 + s R ESR C=O ) m1 , Vo ω ≈ 1GPWM G ≈ , , ω = p PWM Z 1 = I ⋅ D ⋅ (1 − D) 2 IIOO GCA ⋅ R S 11Cn2O) O Vc (1 + sR/CωOp )(1 + s / ωnC Q5 += /ω C > _ CIN C =sR ESR IN C > The goal of compensation is to shape the frequency IN 5 4 ⋅ D V ⋅ F ⋅ C πFFZ1 R R IN ⋅ FSW SW 4 ⋅ DVIN SW O 22 π Z1 77 response of the converter soAC as to achieve high DC a dominant low-frequency pole FP at 20 10 1 accuracy and fast transient R 7 = response while maintaining R 1 C8 = = 1 1 C 8p ≈ 2 πF , R G ≈ , ω ωZ = , g PWM m loop stability. 1 P11 R 77 2 π F P G ⋅ R R C R CO CA S O ESR = D I ⋅ ESR + O L 8 ⋅ FSW ⋅ C O 1 C5 = AC and double poles at half the switching frequency. 2 π F Z1 R 7 CONTROLLER AND SCHOTTKY DIODE 10 20 R7 = gm 1 Io Including the voltage divider (R4 and R6), the control to Rs C CA 8 = 2 π F R feedback transfer function is found and plotted in Figure IO P1 7 1 > C5 = 8 as the converter gain. REF 4 ⋅ DVIN ⋅ FSW + 2 πFZ1 R 7 D3 D1 12 EA FB - Vc PWM MODULATOR SW Vramp L1 C8 = COMP Co C5 R7 1 2 πFP1 R 7 C8 Resr Figure 7. Block diagram of control loops Vo R4 R6 Since the converter gain has only one dominant pole at low frequency, a simple Type-2 compensation network is sufficient for voltage loop compensation. As shown in Figure 8, the voltage compensator has a low frequency integrator pole, a zero at FZ1, and a high frequency pole at FP1. The integrator is used to boost the gain at low frequency. The zero is introduced to compensate the excessive phase lag at the loop gain crossover due to the integrator pole (-90deg) and the dominant pole (-90deg). 13 SC4525C Applications Information (Cont.) The high frequency pole nulls the ESR zero and attenuates high frequency noise. 60 GAIN (dB) 30 Fz1 Fp 0 CO NV -30 -60 1K Fp1 ER T ER Fc LO CO MP OP G EN SA TO RG Choose a loop gain crossover frequency of 80kHz, and place voltage compensator zero and pole at FZ1=16kHz (20% of FC), and FP1=600kHz. From Equation (9), the required compensator gain at FC is AIN AIN AC GA IN Fz Fsw/2 100K FREQUENCY (Hz) 1M Example: Determine the voltage compensator for an 800kHz, 12V to 3.3V/3A converter with 47uF ceramic output capacitor. 20 log 1 1 18.5 3. 53 10 3 2 80 103 47 10 6 1.0 3.3 14.1 dB Then the compensator parameters are 14.1 10K 1 V 1 AC = − 20 ⋅ log ⋅ ⋅ FB G CAR S 2 πFC C O VO Figure 8. Bode plots for voltage loop design 10M 10 20 R7 = = 16.9 k 0.3⋅ 10− 3 1 C5 = = 0. 589 nF 3 2π ⋅ 16 ⋅ 10 ⋅ 16.9 ⋅ 10 3 1 1 1 1 .0 C8 = =15.7 pF AC =the − 20 ⋅ log ⋅ Therefore, procedure of the voltage loop design for −6 ⋅ = 15 . 9 dB2 π⋅ 600 ⋅ 103 ⋅ 16.9 ⋅ 10 3 −3 3 3 .3 2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 28 ⋅ 6 . 1 ⋅ 10 the SC4525C can be summarized as: Select R7=16.9k, C5=0.68nF, and C8=22pF for the design. 15 . 9 gain, i.e. control to feedback transfer (1) Plot the converter 10 20 function. Compensator parameters for various typical applications R7 = = 22 . 3 k −3 28 ⋅ 10 (2) Select the0 .open loop crossover frequency, FC, between are listed in Table 5. A MathCAD program is also available 1 10% and frequency. upon request for detailed calculation of the compensator C 5 20% = of the switching = 0 . 45At nF FC, find the 3 3 2 π ⋅ 16 ⋅ 10gain, ⋅ 22A. 1C. In ⋅ 10 required compensator typical applications with parameters. ceramic output capacitors, 1 the ESR zero is neglected and C 8 = compensator = 12 the required gain at F can bepF estimated by 2 π⋅ 600 ⋅ 10 3 ⋅ 22 . 1 ⋅ 10C 3 Thermal Considerations 1 V 1 (9) AC = − 20 ⋅ log ⋅ ⋅ FB R 2 πF C VO G CA For the power transistor inside the SC4525C, the GPWM (1 +S s R ESR CC O )O Vo (3) Place =the compensator zero, FZ1,2 between 10% and conduction loss PC, the switching loss PSW, and bootstrap 2 Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn ) 1 1 1 . 0 Ploss P = Pcan 20% ofAthe crossover frequency, FC. ⋅ circuit + PBST + Pas SWestimated Q follows: ⋅ 15 .BST, 9 dBC + Pbe =TOTAL C = − 20 ⋅ log −3 3 −6 3 . 3 ⋅ 6 . 1 ⋅F10 2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 (4) Use the compensator , to cancel the ESR zero, 28 pole, P1 FZ. R 1 1 PQ = VIN ⋅ 2mA G ≈ , ωp ≈ , ωZ = , PC = D ⋅ VCESAT ⋅ IO (5) Then,PWM the parameters of the compensation network GCA15⋅.9R S RCO R ESR C O 10 20by can be calculated 1 R7 = = 22 . 3 k AC PSW = ⋅ t S ⋅ VIN ⋅ I O ⋅ FSW (10) 0 . 28 ⋅ 10 −3 20 2 10 R7 = 1 C 5 = gm = 0 . 45 nF I 3 2 π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 PBST = D ⋅ VBST ⋅ O 1 40 C5 = 1 C 8 = 2 πFZ1 R 7 3 = 12pF 2 π⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 3 where PVBST=is(1the voltage and tS is the equivalent − DBST ) ⋅ Vsupply D D ⋅ IO 1 switching time of the NPN transistor (see Table 4). C8 = 2 πFP1 R 7 Gis (1 EA + sR PWM ESR C where Vgom=0.3mA/V the gain ofO )the SC4525C. PIND = (1 .1 ~ 1 .3 ) ⋅ I2O ⋅ R DC = 2 2 Vc (1 + s / ωp )(1 + s / ωn Q + s / ωn ) 14 SC4525C Table 4. Typical switching time Input Voltage 12V 24V 28V 1A 12.5ns 22ns 25.3ns Load Current 2A 3A 15.3ns 18ns 25ns 28ns 28ns 31ns + PBST +InPaddition, the quiescent current loss is Q W O N PCB Layout Considerations Applications Information (Cont.) PQ = VIN ⋅ 2mA (11) The total power loss of the SC4525C is therefore ⋅ I O ⋅ FSW IO 40 ⋅ IO PTOTAL = PC + PSW + PBST + PQ (12) The temperature rise⋅ of = Vproduct IN ⋅ 2 mA of the PC = D ⋅ VCESAT IO the SC4525C PisQthe total power dissipation (Equation (12)) and qJA (36oC/W), which is the thermal impedance from junction to ambient 1 ⋅ t S ⋅package. VIN ⋅ I O ⋅ FSW SW = for thePSOIC-8 EDP 2 In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse current (Figure 9). For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switch is already integrated within the SC4525C, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using vias directly under the device. I ) ⋅ I2O ⋅ R DCIt is not recommended PBST = D ⋅ VBST ⋅ O to operate the SC4525C above 40 125oC junction temperature. V IN PD = (1 − D) ⋅ VD ⋅ IO PIND = (1 .1 ~ 1 .3 ) ⋅ I2O ⋅ R DC VOUT ZL Figure 9. Heavy lines indicate the critical pulse current loop. The stray inductance of this loop should be minimized. 15 SC4525C Recommended Component Parameters in Typical Applications Table 5 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator parameters are calculated by assuming a 47mF low ESR ceramic output capacitor and a loop gain crossover frequency of FSW/10. Table 5. Recommended inductance (L1) and compensator (R7, C5, C8) Vin(V) Typical Applications Vo(V) Io(A) Fsw(kHz) 1.5 2.5 12 3.3 5 3 7.5 10 1.5 2.5 3.3 24 5 7.5 10 3 500 500 1000 500 1000 500 1000 500 1000 500 300 500 500 1000 500 1000 500 1000 500 C2(uF) 47 47 L1(uH) 3.3 4.7 2.2 6.8 3.3 6.8 3.3 6.8 3.3 3.3 6.8 6.8 6.8 3.3 8.2 4.7 10 4.7 15 Recommended Parameters R7(k) C5(nF) C8(pF) 5.23 8.45 15.4 12.1 20.5 15.4 36.5 22.6 47.5 36.5 3.57 6.49 12.1 22.6 15.4 30.9 26.1 52.3 30.9 3.9 3.9 0.82 3.9 0.82 3.9 0.82 3.9 0.82 3.9 3.9 3.9 3.9 0.82 3.9 0.82 3.9 0.82 3.9 Snubber no 22 1ȍ+220pF no 16 SC4525C Typical Application Schematics V IN D1 1N 4148 D3 24V 18 V Zener C4 4.7mF C1 0. 33 mF L1 BST IN SW 6.8 mH SC 4525C SS/ EN OUT R4 33.2k 1.5V/3A FB COMP C7 22 pF GND D2 B 330A R5 69.8k R7 3. 57k C8 22 nF ROSC R6 66.5k C2 47mF C5 3.9 nF L1 : Coiltronics DR74- 6R8 C2 : Murata GRM 31 CR60J 476 M C4 : Murata GRM 32 ER71H 475 K Figure 10. 300kHz 24V to 1.5V/3A Step-down Converter V IN D1 10V – 26V C4 4.7m F C1 0.33 m F BST IN 1 N 4148 L1 OUT SW 3.3 mH Fig10 : 300 kHz24 V to1.5V/3 A Step -3.3V/3 A Down Conv R4 SC 4525C SS/ EN R0 1 33.2k FB COMP C7 22nF C8 22 pF L1 : ROSC R7 22.6 k GND R5 15.8 k C5 0.82 nF Coiltronics DR74 - 3R3 C0 D2 B330A R6 14.3 k C2 47mF 220pF C2 : Murata GRM 31 CR60J 476M C4 : Murata GRM 32 ER71H 475K Figure 11. 1MHz 10V-26V to 3.3V/3A Step-down Converter 17 SC4525C SS Typical Performance Characteristics (For A 12V to 5V/3A Step-down Converter with 1MHz Switching Frequency) SS270 REV 6-7 Load Characteristic 6 Output Voltage (V) 5 12V Input (5V/DIV) 4 3 5V Output (2V/DIV) 2 1 SS Voltage (1V/DIV) 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Load Current (A) Figure 12(a). Load Characteristic OCP 10ms/DIV Figure 12(b). VIN Start up Transient (IO=3A) 5V Output Short (5V/DIV) 5V Output Response (500mV/DIV, AC Coupling) Inductor Current (1A/DIV) Retry Inductor Current (2A/DIV) SS Voltage (2V/DIV) 40us/DIV Figure 12(c). Load Transient Response (IO= 0.3A to 3A) 20ms/DIV Figure 12(d). Output Short Circuit (Hiccup) 18 SC4525C Outline Drawing - SOIC-8 EDP A D e N 2X E/2 E1 E 1 2 ccc C 2X N/2 TIPS e/2 B D aaa C SEATING PLANE A2 A C bxN bbb A1 DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc .069 .005 .065 .020 .010 .193 .197 .154 .157 .236 BSC .050 BSC .116 .120 .130 .085 .095 .099 .010 .020 .016 .028 .041 (.041) 8 0° 8° .004 .010 .008 .053 .000 .049 .012 .007 .189 .150 C A-B D 1.75 0.13 1.65 0.51 0.25 4.90 5.00 3.90 4.00 6.00 BSC 1.27 BSC 2.95 3.05 3.30 2.15 2.41 2.51 0.25 0.50 0.40 0.72 1.04 (1.05) 8 0° 8° 0.10 0.25 0.20 1.35 0.00 1.25 0.31 0.17 4.80 3.80 h F EXPOSED PAD h H H c GAGE PLANE 0.25 L (L1) SEE DETAIL SIDE VIEW A DETAIL 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MS -012, VARIATION BA. 4. -H- 19 SC4525C Land Pattern - SOIC-8 EDP E SOLDER MASK D DIMENSIONS DIM (C) F G Z Y THERMAL VIA Ø 0.36mm P X C D E F G P X Y Z INCHES (.205) .134 .201 .101 .118 .050 .024 .087 .291 MILLIMETERS (5.20) 3.40 5.10 2.56 3.00 1.27 0.60 2.20 7.40 NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 300A. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 20 SC4525C © Semtech 2011 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. 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