INTEGRATED CIRCUITS DATA SHEET PCF8811 80 × 128 pixels matrix LCD driver Product specification Supersedes data of 2002 Dec 04 2004 May 17 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 CONTENTS 12 I2C-BUS INTERFACE Characteristics of the I2C-bus (Hs-mode) I2C-bus Hs-mode protocol Command decoder 1 FEATURES 2 APPLICATIONS 12.1 12.2 12.3 3 GENERAL DESCRIPTION 13 INSTRUCTIONS 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 PIN FUNCTIONS 7.1 7.2 7.3 7.4 7.5 7.6 Explanation of the symbols Initialization Reset function Power-save mode Display control Set Y address of RAM Set X address of RAM Set display start line Bias levels Set VOP value Temperature control 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 ROW 0 to ROW 79: row driver outputs COL 0 to COL 127: column driver outputs VSS1 and VSS2: negative power supply rails VDD1 to VDD3: positive power supply rails VOTPPROG: OTP programming power supply VLCDOUT, VLCDIN and VLCDSENSE: LCD power supply T1 to T5: test pads MF2 to MF0 DS0 VOS4 to VOS0 EXT: extended command set PS0, PS1 and PS2 D/C R/W E SCLH/SCE SDAH SDAHOUT DB7 to DB0 OSC: oscillator RES: reset 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 14 LIMITING VALUES 15 HANDLING 16 DC CHARACTERISTICS 17 AC CHARACTERISTICS 18 PARALLEL INTERFACE TIMING CHARACTERISTICS 19 SERIAL INTERFACE TIMING CHARACTERISTICS 20 I2C-BUS INTERFACE TIMING CHARACTERISTICS 21 APPLICATION INFORMATION 22 MODULE MAKER PROGRAMMING 8 BLOCK DIAGRAM FUNCTIONS 8.1 8.2 8.3 8.4 8.5 8.6 Oscillator Address Counter (AC) Display Data RAM (DDRAM) Timing generator Display address counter LCD row and column drivers 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 VLCD calibration Temperature coefficient selection Seal bit OTP architecture Interface commands Example of filling the shift register Programming flow Programming specification 9 ADDRESSING 23 CHIP INFORMATION 9.1 Display data RAM structure 24 BONDING PAD LOCATIONS 10 PARALLEL INTERFACE 25 DEVICE PROTECTION DIAGRAM 10.1 6800 series parallel interface 26 TRAY INFORMATION 11 SERIAL INTERFACING (SPI AND SERIAL INTERFACE) 27 DATA SHEET STATUS 28 DEFINITIONS 11.1 11.2 Serial peripheral interface Serial interface (3-line) 29 DISCLAIMERS 30 PURCHASE OF PHILIPS I2C COMPONENTS 2004 May 17 2 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 1 PCF8811 FEATURES • Single-chip LCD controller/driver • 80 row and 128 column outputs • Display data RAM 80 × 128 bits • 128 icons (row 80 can be used for icons in extended command set and when icon rows are enabled) • Programmable bottom row pads mirroring; for compatibility with both Tape Carrier Packages (TCP) and Chip On Glass (COG) applications (extended command set) • An 8-bit parallel interface, 3 or 4-line Serial Peripheral Interface (SPI) and high-speed I2C-bus • On-chip: • Status read which allows for chip recognition and content checking of some registers – Configurable voltage multiplier generating VLCD; external VLCD also possible • Start address line which allows, for instance, the scrolling of the displayed image – Linear temperature compensation of VLCD; 8 programmable temperature coefficients (extended command set); one fixed temperature coefficient which default can be set by OTP programming (basic command set) • Programmable display RAM pointers for variable display sizes • Slim chip layout, suited for COG applications – Generation of intermediate LCD bias voltage • Temperature range: Tamb = −40 °C to +85 °C. – Oscillator requires no external components; external clock input also possible. 2 APPLICATIONS • OTP calibration for VLCD and accurate frame frequency • Telecom equipment • External reset input pin • Portable instruments • CMOS compatible inputs • Point of sale terminals. • Mux rate: 1 : 16 to 1 : 80 in steps of 8 when no icon row is used, with the icon row steps of 16 can be used 3 • Logic supply voltage range VDD1 − VSS: The PCF8811 is a low power CMOS LCD controller driver, designed to drive a graphic display of 80 rows and 128 columns or a graphic display of 79 rows and 128 columns and a icon row of 128 symbols. All necessary functions for the display are provided in a single chip, including on-chip generation of the LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF8811 can interface to microcontrollers via a parallel bus, serial bus or I2C-bus interface. – 1.7 V to 3.3 V. • High voltage generator supply voltage range VDD2,VDD3 − VSS: – 1.8 V to 3.3 V. • Display supply voltage range VLCD − VSS: – 3 V to 9 V. • Low power consumption; suitable for battery operated systems 4 GENERAL DESCRIPTION ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCF8811U/2DA/1 − chip with bumps in tray, not covered under Philips/Motif license agreement − PCF8811MU/2DA/1 − chip with bumps in tray, sold under license from Motif − 2004 May 17 3 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 5 PCF8811 BLOCK DIAGRAM VDD1 VDD2 VDD3 ROW 0 to ROW 79 COL 0 to COL 127 128 80 ROW DRIVERS COLUMN DRIVERS BIAS VOLTAGE GENERATOR VLCDIN ORTHOGONAL FUNCTION GENERATOR DATA PROCESSING VSS1 VSS2 VOTPPROG VLCDSENSE HIGH VOLTAGE GENERATOR VLCDOUT RESET RES OSCILLATOR OSC DISPLAY DATA RAM 80 × 128 bits T1 TIMING GENERATOR T2 T3 ADDRESS COUNTER T4 DISPLAY ADDRESS COUNTER T5 MF [2:0] COMMAND DECODER 3 DS0 PCF8811 I/O BUFFER PARALLEL/SERIAL/I 2C-BUS INTERFACE 5 3 Fig.1 Block diagram. 2004 May 17 4 DB0 DB1 DB2/SA0 DB3/SA1 DB4 DB5/SDO DB6/SCLK DB7/SDATA SDAHOUT SDAH SCLH/SCE E R/W D/C PS [2:0] EXT VOS [4:0] mgw732 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 6 PCF8811 PINNING SYMBOL PAD DESCRIPTION MF2 9 manufacturer device ID input MF1 10 manufacturer device ID input MF0 11 manufacturer device ID input DS0 12 device recognition input OSC 13 oscillator input EXT 14 extended command set input PS0 15 parallel/serial/I2C-bus data selection input PS1 16 parallel/serial/I2C-bus data selection input PS2 17 parallel/serial/I2C-bus data selection input VSS(tie off) 18 SDAHOUT 19 I2C-bus data output SDAH 20 and 21 I2C-bus data input SCLH/SCE 22 and 23 I2C-bus clock input/chip enable (6800 interface) VOTPPROG 24 to 26 supply voltage for OTP programming (can be combined with SCLH/SCE) RES 27 external reset input D/C 28 data/command input R/W 29 read/write (6800 interface) input E 30 clock enable (6800 interface) input VDD(tie off) 31 DB0 32 parallel data input/output DB1 33 parallel data input/output DB2/SA0 34 parallel data input/output or I2C-bus slave address input DB3/SA1 35 parallel data input/output or I2C-bus slave address input DB4 36 parallel data input/output DB5/SDO 37 parallel data input/output or serial data output DB6/SCLK 38 parallel data input/output or serial clock input DB7/SDATA 39 parallel data input/output or serial data input VDD1 40 to 45 general supply voltage VDD2 46 to 55 supply voltage for the internal voltage generator VDD3 56 to 60 supply voltage for the internal voltage generator VSS1 61 to 70 ground VSS2 71 to 80 ground T5 81 test input 5 T2 82 test input 2 T1 83 test input 1 T4 84 test output 4 T3 85 test output 3 VOS4 86 VLCD offset input pad 4 VOS3 87 VLCD offset input pad 3 VOS2 88 VLCD offset input pad 2 2004 May 17 5 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver SYMBOL PAD VOS1 VOS0 VLCDOUT PCF8811 89 VLCD offset pad 1 90 VLCD offset pad 0 91 to 99 VLCDSENSE DESCRIPTION 100 voltage multiplier output voltage multiplier regulation input VLCDIN 101 to 107 LCD supply voltage ROW 79 to ROW 40 115 to 154 LCD row driver outputs; ROW 79 is the icon row when the icon row is enabled ROW 80 155 COL 0 to COL 127 156 to 283 LCD column driver outputs ROW 0 to ROW 39 284 to 323 LCD row driver outputs 1, 3 to 8, 109 to 114, 324 to 333 dummy pads 2 and 108 alignment marks 7 7.1 duplicate of ROW 79 PIN FUNCTIONS 7.6 ROW 0 to ROW 79: row driver outputs Positive power supply for the liquid crystal display. If the internal VLCD generator is used, then all three inputs must be connected together. If not (VLCD generator is disabled and an external voltage is supplied to VLCDIN), then VLCDOUT must be left open-circuit, VLCDSENSE must be connected to VLCDIN, VDD2 and VDD3 should be applied according to the specified voltage range. An external LCD supply voltage can be supplied using the VLCDIN pad. In this case, VLCDOUT should not be connected to VLCDIN, and the internal voltage generator must be switched off. If the PCF8811 is in power-save mode, the external LCD supply voltage can be switched off. These pads output the display row signals. 7.2 COL 0 to COL 127: column driver outputs These pads output the display column signals. 7.3 VSS1 and VSS2: negative power supply rails The 2 supply rails must be connected together. 7.4 VDD1 to VDD3: positive power supply rails VDD2 and VDD3 are the supply voltage for the internal voltage generator. Both have the same voltage and may be connected together outside of the chip. VDD1 is used as supply for the rest of the chip. VDD1 can be connected together with VDD2, VDD3 but in this case care must be taken to respect the supply voltage range; see Chapter 16. 7.7 7.8 MF2 to MF0 Manufacturer device ID pads. (manufacturer ID 100 = Philips). VOTPPROG: OTP programming power supply 7.9 Supply voltage for the OTP programming; see Chapter 22. VOTPROG can be combined with the SCLH/SCE pin in order to reduce the external connections. 2004 May 17 T1 to T5: test pads T1, T2 and T5 must be connected to VSS, T3 and T4 must be left open-circuit. Not accessible to user. If the internal voltage generator is not used then pins VDD2 and VDD3 must be connected to VDD1. 7.5 VLCDOUT, VLCDIN and VLCDSENSE: LCD power supply DS0 Device recognition pad; see Table 10. 6 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 7.10 PCF8811 7.16 VOS4 to VOS0 SCLH/SCE These 5 input pins enable the calibration of the programmed VLCD (can be connected on the module to VDD1 or VSS1). Input to select the chip and so allowing data/commands to be clocked in or serial clock input when the I2C-bus interface is selected. 7.11 7.17 EXT: extended command set serial data input. When not used it must be connected to VDD1 and VSS1. Input to select the basic command set or the extended command set. Must be connected on the module to have only one command set enabled. 7.18 Table 1 Command set PIN LEVEL EXT basis command set HIGH extended command set Note: Philips strongly recommends that the extended command set be used. 7.12 PS0, PS1 and PS2 Parallel/serial/I2C-bus interface selection. Table 2 Interface selection PS[2:0] INTERFACE 000 3-line SPI 001 4-line SPI 010 no operation 011 6800 parallel interface 100 or 110 high-speed I2C-bus interface 101 or 111 3-line serial interface 7.13 SDAHOUT SDAHOUT is the serial data acknowledge output for the I2C-bus interface. By connecting SDAHOUT to SDAH externally, the SDAH line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in COG applications. In COG applications where the track resistance from the SDAHOUT pad to the system SDAH line can be significant, a potential divider is generated by the bus pull-up resistor and the ITO track resistance. It is possible that during the acknowledge cycle the PCF8811 will not be able to create a valid logic 0 level. By splitting the SDAH input from the SDAHOUT output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid low level. When not used it must be connected to VDD1 or VSS1. DESCRIPTION LOW SDAH I2C-bus 7.19 DB7 to DB0 These input/output lines are used by the several interfaces as described below. When not used in the serial interface or the I2C-bus interface it must be connected to VDD1 or VSS1. D/C 7.19.1 DB7 TO DB0 (PARALLEL INTERFACE) Input to select either command/data or data input. Not used in the 3-line serial interface, 3-line SPI and I2C-bus interface and must be connected to VDD1 or VSS1. 8-bit bidirectional bus. DB7 is the MSB. 7.14 DB7 is used for serial input data (SDATA) when the serial interface is selected. DB6 (SCLK) is used for the serial input clock when the serial interface is selected. DB5 is used as the serial output of the serial interface (SDO). 7.19.2 R/W Input to select read or write mode when the 6800 parallel interface is selected. Not used in the serial and I2C-bus mode and must be connected to VDD1 or VSS1. 7.15 7.19.3 E DB3 AND DB2 (I2C-BUS INTERFACE) DB3 and DB2 are respectively the SA1 and SA0 inputs when the I2C-bus interface is selected and can be used so that up to four PCF8811s can be distinguished on one I2C-bus interface. E is the clock enable input for the 6800 parallel bus. Not used in the serial or I2C-bus interface and must be connected to VDD1 or VSS1. 2004 May 17 DB7, DB6 AND DB5 (SERIAL INTERFACE) 7 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 7.20 PCF8811 8.4 OSC: oscillator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus. When the on-chip oscillator is used this input must be connected to VDD1. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to VSS1, the display is not clocked and may be left in a DC state. To avoid this the chip should always be put into Power-down mode before stopping the clock. 7.21 8.5 8.1 RES: reset BLOCK DIAGRAM FUNCTIONS The display status (all dots on/off and normal/inverse video) is set by the bits DON, DAL and E in the command display control; see Table 6. Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD1. An external clock signal, if used, is connected to this input. 8.2 8.6 Address Counter (AC) Display Data RAM (DDRAM) The PCF8811 contains an 80 × 128-bit static RAM which stores the display data. The RAM is divided into 10 banks of 128 bytes (10 × 8 × 128 bits). The icon row when enabled is always ROW 79 and therefore located in bank 9. During RAM access, data is transferred to the RAM via the parallel, serial interface or I2C-bus interface. There is a direct correspondence between the X address and the column output number. 2004 May 17 LCD row and column drivers The PCF8811 contains 80 row and 128 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. The address counter assigns addresses to the display data RAM for writing. The X address X[6:0] and the Y address Y[3:0] are set separately. 8.3 Display address counter The display is generated by simultaneously reading out the RAM content for 2, 4 or 8 rows depending on the selected current display size. This content will be processed with the corresponding set of 2, 4 or 8 orthogonal functions and so generating the signals for switching the pixels in the display on or off according to the RAM content. The possibility exists to set the p value for the display sizes 64 and 80 manually to p = 4. This signal will reset the device and must be applied to properly initialize the chip. The signal is active LOW. 8 Timing generator 8 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 DPRAM bank 0 top of LCD R0 bank 1 R8 bank 2 R16 LCD bank 3 R24 bank 9 R72 R79 MGW734 Fig.2 DDRAM to display mapping. 2004 May 17 9 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 9 PCF8811 ADDRESSING 9.1.1 BASIC COMMAND SET Data is downloaded in bytes into the RAM matrix of the PCF8811 as indicated in Fig.2. The display RAM has a matrix of 80 by 128 bits. The columns are addressed by the address pointer. The address ranges are: X = 0 to 127 (1111111), Y = 0 to 9 (1001). The Y address represents the bank number. The X and Y address which are effectively used can be programmed thus in order to use the PCF8811 with different display sizes without additional loading of the microprocessor. Addresses outside these ranges are not allowed. The icon row when enabled is always ROW 79 and therefore located in bank 9. After a write operation the column address counter (X address) auto-increments by one, and wraps to zero after the last column is written. The number of columns (X address) after which the wrap around must occur can be programmed. The Y address counter does not auto-increment in the basic command set, the counter stops when a complete bank has been written to. In this case the Y address counter must be set (Y address see Table 5) to write the next bank (see Fig.3). When only a part of the RAM is used both X (X max) and Y (Y max) addresses can be set. 9.1 The data order in the basic command set is as defined in Fig.3. Display data RAM structure The mode for storing data into the data RAM is dependent on the selected command set. handbook, full pagewidth LSB 0 MSB LSB Y max MSB 0 X address X max Y address MGW735 Fig.3 Sequence of writing data bytes into the RAM (basic command set). 2004 May 17 10 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 9.1.2 PCF8811 EXTENDED COMMAND SET 9.1.2.1 In the vertical addressing mode (V = 1) the Y address increments after each byte. After the last Y address (Y = 9), Y wraps around to 0 and X increments to address the next column (see Fig.5). The last Y address after which Y wraps to 0 can be programmed. In Fig.5 it can be seen that the X address is programmed to be 127, and the Y address is programmed to be 9. With X max and Y max the X and Y addresses can be programmed while the whole RAM is not being used. Horizontal/vertical addressing Two different addressing modes are possible with the extended command set: horizontal addressing mode and vertical addressing mode. In the horizontal addressing mode (V = 0) the X address increments after each byte. After the last X address, X wraps around to 0 and Y increments to address the next row (see Fig.4). The number of columns (last X address) after which the wrap around must occur can be programmed. In Fig.4 it can be seen that the X address is programmed to be 127, and the Y address is programmed to be 9. With X max and Y max the X and Y addresses can be programmed while the whole RAM is not being used. After the very last address the address pointers wrap around to address X = 0 and Y = 0 in both horizontal and vertical addressing modes. handbook, full pagewidth 0 1 2 128 129 130 256 257 258 384 385 386 512 513 514 640 641 642 768 769 770 896 897 898 0 Y address 1024 1025 1026 1152 1153 1154 0 1279 X address 127 9 MGW736 Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0) (extended command set). 2004 May 17 11 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth 0 10 1 11 0 2 3 4 Y address 5 6 7 8 9 0 1279 X address 127 9 MGW737 Fig.5 Sequence of writing data bytes into the RAM with vertical addressing (V = 1) (extended command set). 9.1.2.2 Data order The data order bit (DOR) defines the bit order (LSB or MSB on top) for writing into the RAM (see Figs 6 and 7). This feature is only available in the extended command set. LSB handbook, full pagewidth MSB LSB MGW738 MSB Fig.6 RAM byte organisation, if DOR = 0 (extended command set). 2004 May 17 12 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 MSB handbook, full pagewidth LSB MSB MGW739 LSB Fig.7 RAM byte organisation, if DOR = 1 (extended command set). 9.1.3 9.1.3.1 FEATURES AVAILABLE IN BOTH COMMAND SETS Mirror X (MX) The MX bit allows horizontal mirroring: when MX = 1 the X address space is mirrored; the address X = 0 is then located at the right side (X max) of the display (see Fig.8). When MX = 0 the mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display (see Fig.9). handbook, full pagewidth 0 Y max X max X address 0 Y address MGW740 Fig.8 RAM format addressing (MX = 1) (both command sets). 2004 May 17 13 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth 0 Y max 0 X address X max Y address MGW741 Fig.9 RAM format addressing (MX = 0) (both command sets). 9.1.3.2 Mirror Y (MY) The MY bit allows vertical mirroring: when MY = 1 the Y address space is mirrored; the address Y = 0 is then located at the bottom of the display (see Fig.10). When MY = 0 the mirroring is disabled and the address Y = 0 is located at top of the display (see Fig.11). The icon row, when enabled, will always be located in bank 9 and ROW 79. handbook, full pagewidth Y max 0 0 X address X max Y address MGW742 Fig.10 RAM format addressing (MY = 1) (both command sets). 2004 May 17 14 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth 0 Y max 0 X address X max Y address MGW743 Fig.11 RAM format addressing (MY = 0) (both command sets). 10 PARALLEL INTERFACE Table 3 The parallel interfaces which can be selected is the 6800 series 8-bit bidirectional interface for communication between the microcontroller and the LCD driver chip. The selection of these interfaces is achieved with pins PS[2:0]; see Section 7.12. 10.1 6800 series parallel interface function D/C R/WR OPERATION 0 0 command data write 0 1 read status register 1 0 display data write 1 1 none 6800 series parallel interface The interface functions of the 6800 series parallel interface are given in Table 3. The parallel interface timing diagram for the 6800 series is given in Chapter 18 (see Figs 35 and 36). The timing diagrams differ because the clock is connected (in Fig.35) to the enable (E) input. In Fig.36 the clock is connected to the chip select input (SCE) and the enable input (E) is tied HIGH. 2004 May 17 15 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 11 SERIAL INTERFACING (SPI AND SERIAL INTERFACE) 11.1.1 The display data/command indication may be controlled either via software or the D/C select pin. When the D/C pin is used, display data is transmitted when D/C is HIGH, and command data is transmitted when D/C is LOW (see Figs 12 and 13). When pin D/C is not used, the display data length instruction is used to indicate that a specific number of display data bytes (1 to 255) are to be transmitted (see Fig.14). The next byte after the display data string is handled as an instruction command. Communication with the microcontroller can also occur via a clock-synchronized Serial Peripheral Interface (SPI). It is possible to select two different 3-line (SPI and serial interface) or a 4-line serial interface. Selection is achieved via PS[2:0]; see Section 7.12. 11.1 WRITE MODE Serial peripheral interface The serial peripheral interface is a 3-line or 4-line interface for communication between the microcontroller and the LCD driver chip. The 3 lines are: SCE (chip enable), SCLK (serial clock) and SDATA (serial data). For the 4-line serial interface a separate D/C line is added. The PCF8811 is connected to the serial data I/O (SDA) of the microcontroller by two pins: SDATA (data input) and SDO (data output) connected together. When the 3-line SPI interface is used the display data/command is controlled by software. If SCE is pulled HIGH during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. The next byte received will be handled as an instruction command (see Fig.15). handbook, full pagewidth SCE D/C SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGW744 Fig.12 Serial bus protocol: transmission of one byte. handbook, full pagewidth SCE D/C SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 MGW745 Fig.13 Serial bus protocol: transmission of several bytes. 2004 May 17 16 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth SCE SCLK SDATA DB7 DB6 DB5 DB4 DB2 DB1 DB0 data display length instruction and length data (two bytes) data last data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 display data string instruction MGW746 Fig.14 Transmission of several bytes. handbook, full pagewidth SCE SCLK SDATA data data data data data data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 MGW747 display data string instruction Fig.15 Transmission interrupted by SCE. 11.1.2 READ MODE (ONLY EXTENDED COMMAND SET) The PCF8811 samples the SDIN data on rising SCLK edges, but shifts SDO data on falling SCLK edges. Thus the microcontroller is supposed to read SDO data on rising SCLK edges. The read mode of the interface means that the microcontroller reads data from the PCF8811. To do so the microcontroller first has to send a command (the read status command) and then the PCF8811 will respond by transmitting data on the SDO line. After that SCE is required to go HIGH (see Fig.16). After the read status command has been sent, the SDIN line must be set to 3-state not later then the falling SCLK edge of the last bit (see Fig.16). The serial interface timing diagram is given in Chapter 19. 2004 May 17 17 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth SCE RES SCLK SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDO DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 instruction read out data MGW748 Fig.16 Read mode SPI 3-line and 4-line. 11.2 Serial interface (3-line) Figures 18, 19 and 20 show the protocol of the write mode: The serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The 3 lines are: SCE (chip enable), SCLK (serial clock) and SDATA (serial data). The PCF8811 is connected to the SDA of the microcontroller by two pins: SDATA (data input) and SDO (data output) which are connected together. 11.2.1 • When SCE is HIGH, SCLK clocks are ignored; during the HIGH time of SCE the serial interface is initialized • SCLK must be LOW on the falling SCE edge (see Fig.37) • SDATA is sampled on the rising edge of SCLK • D/C indicates, whether the byte is a command (D/C = 0) or RAM data (D/C = 1); it is sampled on the first rising SCLK edge WRITE MODE The write mode of the interface means that the microcontroller writes commands and data to the PCF8811. Each data packet contains a control bit (D/C) and a transmission byte. If D/C is LOW, the following byte is interpreted as a command byte. The command set is given in Table 5. If D/C is HIGH, the following byte is stored in the display data RAM. After every data byte the address counter is incremented automatically. Figure 17 shows the general format of the write mode and the definition of the transmission byte. • If SCE stays LOW after the last bit of a command/data byte, the serial interface receives the D/C bit of the next byte on the next rising edge of SCLK (see Fig.19) • A reset pulse RES interrupts the transmission. The data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C bit of a command/data byte (see Fig.20). Any instruction can be sent in any order to the PCF8811; the MSB is transmitted first. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no effect and no power is consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of data transmission. 2004 May 17 18 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 Transmission Byte (TB) (command byte OR data byte) handbook, full pagewidth D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MSB LSB TB D/C TB D/C D/C TB MGU278 Fig.17 Serial data stream; write mode. handbook, full pagewidth SCE SCLK SDIN D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGU279 Fig.18 Write mode: a control bit followed by a transmission byte. handbook, full pagewidth SCE SCLK SDIN D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C MGU280 Fig.19 Write mode: transmission of several bytes. 2004 May 17 19 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth SCE RES SCLK SDIN D/C D/C DB7 DB6 DB5 DB4 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C DB7 DB6 MGU281 Fig.20 Write mode: interrupted by reset (RES). 11.2.2 READ MODE (ONLY EXTENDED COMMAND SET) After the read status command has been sent, the SDATA line must be set to 3-state not later then the falling SCLK edge of the last bit (see Fig.21). The read mode of the interface means that the microcontroller reads data from the PCF8811. To do so the microcontroller first has to send a command (the read status command) and then the following byte is transmitted in the opposite direction (using SDO) (see Fig.21). After that, SCE is required to go HIGH before a new command is sent. The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge (see Fig.40). The last rising SCLK edge sets SDO to 3-state after the delay time t4. The serial interface timing diagram is given in Chapter 19. The PCF8811 samples the SDATA data on the rising SCLK edges, but shifts SDO data on the falling SCLK edges. Thus the microcontroller is supposed to read SDO data on rising SCLK edges. handbook, full pagewidth SCE SCLK SDIN D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDOUT D/C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 MGU282 Fig.21 Read mode serial interface 3-line. 2004 May 17 20 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 12.1.2 12 I2C-BUS INTERFACE 12.1 One data bit is transferred during each clock pulse (see Fig.23). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. Characteristics of the I2C-bus (Hs-mode) The I2C-bus Hs-mode is for bidirectional, two-line communication between different ICs or modules with speeds of up to 3.4 MHz. The only difference between Hs-mode slave devices and F/S-mode slave devices is the speed at which they operate, therefore the buffers on the SCLH and SDAH have open-drain outputs. This is the same for I2C-bus master devices which have an open-drain SDAH output and a combination of an open-drain, pull-down and current source pull-up circuits on the SCLH output. Only the current source of one master is enabled at any one time, and only during Hs-mode. Both lines must be connected to a positive supply via a pull-up resistor. 12.1.3 12.1.4 ACKNOWLEDGE Each byte of eight bits is followed by an acknowledge bit; see Fig.25. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. SYSTEM CONFIGURATION The system configuration is illustrated in Fig.22. Definitions of the I2C-bus terminology: • Transmitter: the device which sends the data to the bus • Receiver: the device which receives the data from the bus • Master: the device which initiates a transfer, generates clock signals and terminates a transfer • Slave: the device addressed by a master • Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message • Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted • Synchronization: procedure to synchronize the clock signals of two or more devices. 2004 May 17 START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.24. Data transfer may be initiated only when the bus is not busy. 12.1.1 BIT TRANSFER 21 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER PCF8811 SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL MGA807 Fig.22 System configuration. handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed MBC621 Fig.23 Bit transfer. handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition Fig.24 Definition of START and STOP conditions. 2004 May 17 22 MBC622 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.25 Acknowledge on the I2C-bus. 12.2 After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its current source pull-up circuit. The active master re-enables its current source again when all devices have been released and the SCLH signal reaches a HIGH level. The rising of the SCLH signal is done by a pull-up resistor and therefore is slower, the last part of the SCLH rise time is speeded up because the current source is enabled. Data transfer only switches back to F/S mode after a STOP condition (P). I2C-bus Hs-mode protocol The PCF8811 is a slave receiver/transmitter. If data is to be read from the device, the SDAH pin must be connected, otherwise SDAH may be unused. Hs-mode can only commence after the following conditions: • START condition (S) • 8-bit master code (00001XXX) A write sequence after the Hs-mode is selected is illustrated in Fig.28. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, the remainder will ignore the I2C-bus transfer. • Not-acknowledge bit (A). The master code has two functions: it allows arbitration and synchronization between competing masters at F/S-mode speeds, resulting in one winner. The master code also indicates the beginning of an Hs-mode transfer. These conditions are illustrated in Figs 26 and 27. After the acknowledgement cycle of a write (W), one or more command words will follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and D/C, plus a data byte (see Fig.28 and Table 4). As no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge (A). After this A bit, and the SCLH line has been pulled up to a HIGH level, the active master switches to Hs-mode and enables at tH the current-source pull-up circuit for the SCLH signal (see Fig.27). The last control byte is tagged with a cleared MSB, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus. The active master will then send a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit, and receives an acknowledge bit (A) from the selected slave. 2004 May 17 23 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver Table 4 BIT PCF8811 Co and D/C definition LOGIC LEVEL R/W ACTION 0 N/A last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or RE-START condition Co 1 D/C another control byte will follow the data byte unless a STOP or RE-START condition is received 0 1 0 data byte will be decoded and used to set-up the device 1 data byte will return the status byte 0 data byte will be stored in the display RAM 1 RAM read back is not supported The data pointer is automatically updated and the data is directed to the intended PCF8811 device. If the D/C bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8811. At the end of the transmission the I2C-bus master issues a STOP condition (P) and switches back to the F/S-mode, however, to reduce the overhead of the master code, it is possible that a master can link a number of Hs-mode transfers, separated by repeated START conditions (Sr). A read sequence is given in Fig.29 and again this sequence follows after the Hs-mode is selected. The PCF8811 will immediately start to output the requested data until a not-acknowledge is transmitted by the master. Before the read access, the user has to set the D/C bit to the appropriate value by a preceding write access. The write access should be terminated by a RE-START condition so that the Hs-mode is not disabled. After the last control byte, depending on the D/C bit setting, either a series of display data bytes or command data bytes may follow. If the D/C bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. ,,,,, ,,,,, ,,,,,,,,,, handbook, full pagewidth Hs-mode (current-source for SCLH enabled) F/S-mode S MASTER CODE A Sr SLAVE ADD. R/W A DATA (n bytes + ack.) ,, ,, ,,,, ,,,, F/S-mode A/A P Hs-mode continues Sr SLAVE ADD. MSC616 Fig.26 Data transfer format in Hs-mode. 2004 May 17 24 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 8-bit Master code 00001xxx S A t1 tH SDAH SCLH 1 6 2 to 5 7 8 9 Fs mode R/W 7-bit SLA Sr n × (8-bit DATA A + A/A) Sr P SDAH SCLH 1 2 to 5 6 7 8 9 2 to 5 1 6 7 8 9 If P then Fs mode Hs-mode If Sr (dotted lines) then Hs mode tH tFS MSC618 = MCS current source pull-up = Rp resistor pull-up Fig.27 Data transfer timing format in Hs-mode. handbook, full pagewidth acknowledge from PCF8811 S S Sr 0 1 1 1 1 A A 0 A 1 D/C 1 0 slave address R/W Co acknowledge from PCF8811 control byte A acknowledge from PCF8811 data byte 2n ≥ 0 bytes A 0 D/C Co acknowledge from PCF8811 control byte 1 byte A acknowledge from PCF8811 A P data byte n ≥ 0 bytes MSB . . . . . . . . . . . LSB MGW749 Fig.28 Master transmits in Hs-mode to slave receiver; write mode. 2004 May 17 25 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 acknowledgement from PCF8811 handbook, full pagewidth S S Sr 0 1 1 1 1 A A 1 A 1 0 NOT acknowledgement from Master status information A P slave address R/W STOP condition MGW750 Fig.29 Master receives from slave transmitter (status register is read); read mode. 12.3 In the case of the parallel and 4-wire SPI interfaces, the distinction is the D/C pin. When the D/C pin is at logic 0, the chip will respond to instructions as defined in Table 5. When the D/C bit is at logic 1, the chip will send data to the RAM. Command decoder The command decoder identifies command words that are received on the I2C-bus: • Pairs of bytes: information in 2nd byte, first byte determines whether information is display or instruction data When the 3-wire SPI, the 3-wire serial interface or the I2C-bus interface is used, the distinction between instructions which define the operating mode of the device and those that fill the display RAM, is made respectively by the display data length instruction (3-line SPI) or by the D/C bit in the data stream (3-line serial interface and I2C-bus interface). • Stream of information bytes after Co = 0: display or instruction data depending on last D/C. The most significant bit of a control byte is the continuation bit Co. If this bit is at logic 1, it indicates that only one data byte, either command or RAM data, will follow. If this bit is at logic 0, it indicates that a series of data bytes, either command or RAM data, may follow. The DB6 bit of a control byte is the RAM data/command bit D/C. When this bit is at logic 1, it indicates that a RAM data byte will be transferred next. If the bit is at logic 0, it indicates that a command byte will be transferred next. There are 4 types of instructions. Those which: 1. Define the PCF8811 functions, such as display configuration etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. 13 INSTRUCTIONS In normal use, category 3 instructions are used most frequently. The PCF8811 interfaces via an 8-bit parallel interface, two different 3-line serial interfaces, a 4-wire serial interface or an I2C-bus interface. Processing of the instructions does not require the display clock. A basic and an extended instruction set is available: if the EXT pin is set LOW the basic command set is used. If the EXT pin is set HIGH the extended command set is used. Data accesses to the PCF8811 can be broken down into two areas; those that define the operating mode of the device, and those that fill the display RAM. 2004 May 17 Both command sets are detailed in Table 5. 26 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... INSTRUCTION EXT(2) COMMAND BYTE D/C R/W DESCRIPTION D7(3) D6 D5 D4 D3 D2 D1 D0 NOP X 0 0 0 1 0 0 1 1 X X no operation NOP X 0 0 1 1 1 0 0 1 0 0 no operation Reset X 0 0 1 1 1 0 0 0 1 0 soft reset Write data X 1 0 D7 D6 D5 D4 D3 D2 D1 D0 write data to display RAM Display data length X X 0 0 0 0 1 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 only used in 3-line SPI Status read X 0 1 BUSY DON RES MF2 MF1 MF0 DS1 DS0 read status byte X 0 X 1 1 0 1 1 0 1 X read status byte Display control 27 X 0 0 1 0 1 0 1 1 1 DON display on or off X 0 0 1 0 1 0 0 1 1 E normal or reverse mode X 0 0 1 0 1 0 0 1 0 DAL all pixels on or off X 0 0 1 0 1 0 0 0 0 MX mirror X X 0 0 1 1 0 0 MY X X X mirror Y 1 0 0 1 1 1 0 1 1 1 IC icon enable or disable; note 4 1 0 0 1 0 1 0 0 0 1 V vertical or horizontal addressing; note 4 1 0 0 1 1 1 0 1 0 1 DOR data order; note 4 1 0 0 1 1 1 0 1 1 0 BRS bottom row swap; note 4 0 1 0 1 1 Y3 Y2 Y1 Y0 set Y address; 0 ≤ Y ≤ 9 0 0 0 0 1 0 X6 X5 X4 set X address; 0 ≤ X ≤ 127 X 0 0 0 0 0 0 X3 X2 X1 X0 X 0 0 0 0 0 X 0 X 0 X 1 X 1 Y max3 0 Y max2 0 Y max1 1 Y max0 set Y max; 0 ≤ Y ≤ 9 X 0 0 0 X 0 X max6 0 X max5 1 X max4 1 X max3 0 X max2 0 X max1 0 X max0 set X max; 0 ≤ X ≤ 127 Set initial display line X X 0 0 0 0 0 X 1 L6 0 L5 0 L4 0 L3 0 L2 X L1 X L0 set initial display line; 0 ≤ L ≤ 79; note 5 Set initial row X X 0 0 0 0 0 X 1 C6 0 C5 0 C4 0 C3 1 C2 X C1 X C0 set start row; 0 ≤ C ≤ 79; note 6 Product specification 0 0 PCF8811 X X ADR commands Philips Semiconductors Instruction set; note 1 80 × 128 pixels matrix LCD driver 2004 May 17 Table 5 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... COMMAND BYTE D/C R/W DESCRIPTION D7(3) D6 D5 D4 D3 D2 D1 D0 Set partial display X X 0 0 0 0 0 X 1 P6 0 P5 0 P4 1 P3 0 P2 X P1 X P0 set partial display 1 : 16 to 1 : 80 VOP setting 0 0 0 0 0 0 1 X 0 X 0 VPR5 0 VPR4 0 VPR3 0 VPR2 0 VPR1 1 VPR0 set VOP; notes 7 and 8 0 0 0 0 0 1 0 0 VOFF2 VOFF1 VOFF0 offset for the programming range VOP; notes 7 and 8 1 1 0 0 0 0 1 VPR7 0 VPR6 0 VPR5 0 VPR4 0 VPR3 0 VPR2 0 VPR1 1 VPR0 set VOP; note 4 X 0 0 0 0 1 0 1 PC1 PC0 1 switch HVgen on/off Power control HVgen stages 28 0 0 0 0 1 1 0 0 1 S1 S0 set multiplication factor 1 0 0 0 1 1 0 0 S2 S1 S0 set multiplication factor; note 4 FR 1 0 0 0 0 0 1 1 1 FR1 FR0 set frame rate frequency; note 4 TC(9) 1 0 0 0 0 1 1 1 TC2 TC1 TC0 set temperature coefficient; note 4 Bias system 0 0 0 0 1 0 1 0 BS2 BS1 BS0 set bias system; note 10 Manual p value (p = 4) 1 0 0 0 0 0 1 1 0 1 MP set manual p value; notes 4 and 11 Power-save on X 0 0 1 0 1 0 1 0 0 1 power-save mode Power-save off X 0 0 1 1 1 0 0 0 0 1 exit power-save mode Internal oscillator X 0 0 1 0 1 0 1 0 1 OS switch internal oscillator on/off Internal oscillator 1 0 0 1 1 1 0 0 1 1 EC enable or disable the internal or external oscillator; note 4 Enter CALMM mode X 0 0 1 0 0 0 0 0 1 0 enter CALMM mode Reserved X 0 0 0 0 1 0 1 X X 0 reserved Reserved X 0 0 0 1 1 1 X X X X reserved Test X 0 0 1 1 1 1 X X X X do not use; reserved for testing Philips Semiconductors EXT(2) 80 × 128 pixels matrix LCD driver 2004 May 17 INSTRUCTION Product specification PCF8811 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 8. The programming of VOP in the basic command set must be done in the following order: Notes 1. X = don’t care. 2. Philips strongly recommends that the extended command set be used. a) VPR[5:0] 3. D7 = MSB. c) Must be followed by another command. b) VOFF[2:0] 9. One fixed TC is set automatically if the basic command set is used. 4. Commands only available with the extended command set, EXT = 1. If EXT = 0 these commands have no effect. 5. When icon mode is enabled the set initial display line is 0 ≤ L ≤ 78. 10. Bias system settings which can be received when the chip is used as replacement of Alth and Pleskho driving method (NOP). 6. When icon mode is enabled the set initial row is 0 ≤ C ≤ 78. 11. Only for mux rates 1 : 64 and 1 : 80 the number of simultaneous rows can be manually set to p = 4. 7. Commands only used for the basic command set, EXT = 0. If EXT = 1 these commands have no effect. Care should be taken when setting VOP in the basic command set, it must be followed by another command. 13.1 Explanation of the symbols 13.1.1 COMMON INSTRUCTIONS OF THE BASIC AND EXTENDED COMMAND SET Table 6 Explanation of the symbols BIT LOGIC 0 LOGIC 1 RESET STATE DON display off display on 0 E normal display inverse video mode 0 DAL normal display all pixels on 0 MX no X mirroring X mirroring 0 MY no Y mirroring Y mirroring 0 OC stop frame frequency calibration start frame frequency calibration 0 OS internal oscillator off start internal oscillator X[6:0] sets X address (column) for writing in the RAM 0000000 Y[3:0] sets Y address (bank) for writing in the RAM 0000 Xmax[6:0] set wrap around X address (column) 1111111 Ymax[3:0] set wrap around Y address (bank) 1001 L[6:0] sets line address of the display RAM to be displayed on the initial ROW 0 0000000 C[6:0] sets the initial ROW 0 of the display; this command cannot access the icon driver row ROW 80; if icon row is enabled 0000000 P[6:0] partial display mode 1 : 16 to 1 : 80; note 1 1010000 (1 : 80)/1000000 (1 : 64) PC[1:0] switch HV generator on/off 00 S[1:0] charge pump multiplication factor 00 2004 May 17 29 0 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 Note 1. Partial displays can be selected in steps of 8 when the icon mode is not selected. When the icon mode is selected partial displays can be selected in steps of 16. For example, without icons the available partial display sizes are 8, 16, 24, 32, 40, 48, 56, 64 or 72 lines. With icons there are 16, 32, 48 or 64 lines possible. Table 7 Table 8 Power control PC[1:0] DESCRIPTION 00 HVgen off 01 HVgen on 10 HVgen on 11 HVgen on Power-Save Mode (PSM), OS, DON, DAL and E combinations; note 1 PSM OS DON DAL E DESCRIPTION 0 0 X X X oscillator off; HVgen disabled 0 1 X 0 X oscillator on; HVgen enabled 0 1 0 1 X display off, ROW/COL at VSS; oscillator off; HVgen disabled; note 2 0 1 1 0 0 normal display mode 0 1 1 0 1 inverse display mode 0 1 1 1 X all pixels on; note 3 1 X X X X power-save mode: display off; ROW/COL at VSS; oscillator off; HVgen disabled Notes 1. X = don’t care. 2. The DON bit can only be addressed after DAL is activated. 3. The DAL bit has priority over the E bit. Table 9 Read status byte BIT DESCRIPTION BUSY if BUSY = 0 the chip is able to accept new commands DON same bit as in Table 4 RES if RES = 1 a reset is in progress MF[2:0] device manufacturer ID DS0 device recognition; see Table 10 Table 10 Device recognition; note 1 DS0 DESCRIPTION 0 64 row driver 1 80 row driver Note 1. This is the only default setting after reset, another setting can be selected with the ‘set partial display mode’ command. 2004 May 17 30 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 Table 11 Multiplication settings DECIMAL BINARY S[1:0] DESCRIPTION +12 01100 00 4 × voltage multiplier +13 01101 01 5 × voltage multiplier +14 01110 10 6 × voltage multiplier +15 01111 11 7 × voltage multiplier −1 11111 −2 11110 −3 11101 BINARY −4 11100 Table 12 VOS values in twos complement notation DECIMAL 13.1.2 0 00000 −5 11011 +1 00001 −6 11010 +2 00010 −7 11001 +3 00011 −8 11000 +4 00100 −9 10111 +5 00101 −10 10110 +6 00110 −11 10101 +7 00111 −12 10100 +8 01000 −13 10011 +9 01001 −14 10010 +10 01010 −15 10001 +11 01011 −16 10000 SPECIFIC COMMANDS OF THE BASIC COMMAND SET Table 13 Explanation of symbols BIT LOGIC 0 LOGIC1 RESET STATE VPR[5:0] programming value of VLCD 000000 VOFF[2:0] offset for the programming value of VLCD 000 2004 May 17 31 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 13.1.3 PCF8811 SPECIFIC COMMANDS OF THE EXTENDED COMMAND SET Table 14 Explanation of symbols BIT LOGIC 0 LOGIC 1 RESET STATE VPR[7:6] + VPR[5:0] programming value of VLCD 00000000 FR[1:0] frame-rate frequency 11 TC[2:0] temperature coefficient (TC2) 010 V horizontal addressing vertical addressing 0 DOR LSB at top MSB at top 0 IC no Icon row (1/16 to 1/80) Icon row (1/16 to 1/80) 0 BRS bottom rows are not mirrored bottom rows are mirrored 0 MP(1) mux rate driven p value (automatic) p = 4 selected for mux rate 1 : 64 and 1 : 80 0 EC use internal oscillator use external oscillator 0 S[2:0] charge pump multiplication factor 100 Note 1. It is strongly recommended to use the p = 4 setting. Table 15 Frame-rate frequency Table 17 Multiplication settings FR[1:0] FRAME-RATE FREQUENCY S[2:0] DESCRIPTION 000 2 × voltage multiplier 00 30 Hz 001 3 × voltage multiplier 01 40 Hz 010 4 × voltage multiplier 10 50 Hz 011 5 × voltage multiplier 11 60 Hz 100 4 × voltage multiplier 101 5 × voltage multiplier 110 6 × voltage multiplier 111 7 × voltage multiplier Table 16 Temperature coefficient TC[2:0] TEMPERATURE COEFFICIENT 000 0 13.2 001 1 010 2 011 3 100 4 101 5 110 6 Reset is accomplished by applying an external reset pulse (active LOW) at pad RES. When reset occurs within the specified time, all internal registers are reset, however the RAM is still undefined. The state after reset is described in Section 13.3. Pad RES must be ≤0.3VDD1 when VDD1 reaches VDD(min) (or higher) within a maximum time tVHRL after VDD1 goes high (see Fig.43). 111 7 2004 May 17 Initialization A reset can also be achieved by sending a reset command. This command can be used during normal operation but not to initialize the chip after power-on. 32 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 13.3 13.3.1 PCF8811 • Power-save mode is on Reset function • Horizontal addressing enabled (V = 0) BASIC COMMAND SET • No data order swap (DOR = 0) After reset the LCD driver has the following state: • No bottom row swap (BRS = 0) • Display setting E = 0 and DAL = 0 • Internal oscillator enabled (EC = 0) • Address commands X[6:0] = 0 and Y[3:0] = 0 • No frame calibration running (OC = 0). • VLCD is equal to 0, the HV generator is switched off (PC[1:0] = 00) 13.4 • No offset of the programming range (VOFF[2:0] = 0) In the power-save mode the LCD driver has the following state: • HV generator programming (VPR[5:0] = 0) • 4 × voltage multiplier (S[1:0] = 00) • All LCD outputs at VSS (display off) • After power-on, RAM data is undefined, the reset signal does not change the content of the RAM • Bias generator and VLCD generator switched off; external VLCD can be disconnected • All LCD outputs at VSS (display off) • Oscillator off (external clock possible) • Initial display line set to line 0 (L[6:0] = 0) • RAM contents not cleared; RAM data can be written • Initial row set to ROW 0 (C[6:0] = 0) • VLCD discharged to VSS in Power-down mode. • Full display selected (P[6:0] = mux 1 : 80 or 1 : 64) There are two ways to put the chip into power-save mode: • Display is not mirrored (MX = 0 and MY = 0) • The display must be off (DON = 0) and all the pixels on (DAL = 1) • Internal oscillator is off • Power-save mode is on • The power-save mode command is activated. • No frame calibration is running. 13.5 13.3.2 Power-save mode EXTENDED COMMAND SET Display control The bits DON, E and DAL select the display mode; see Table 8. After reset the LCD driver has the following state: • Display settings E = 0 and DAL = 0 • Icons disabled (IC = 0) 13.5.1 • Address counter X[6:0] = 0 and Y[3:0] = 0 When MX = 0 the display RAM is written from left to right (X = 0 is on the left side and X = X max is on the right side of the display). • Temperature control mode TC2 (TC[2:0] = 010) • VLCD is equal to 0; the HV generator is switched off (PC[1:0] = 0) MX When MX = 1 the display RAM is written from right to left (X = 0 is on the right side and X = X max is on the left side of the display). • HV generator programming (VPR[7:0] = 0) • 4 × voltage multiplier (S[2:0] = 100) The MX bit has an impact on the way the RAM is written to. So if a horizontal mirroring of the display is desired, the RAM must first be rewritten, after changing the MX bit. • Frame-rate frequency (FR[1:0] = 11) • After power-on, RAM data is undefined, the reset signal does not change the content of the RAM • All LCD outputs at VSS (display off) 13.5.2 • Full display selected (P[6:0] = mux 1 : 80 or 1 : 64) When MY = 1, the display is mirrored vertically. • Initial display line set to line 0 (L[6:0] = 0) A change of this bit has an immediate effect on the display. • Initial row set to ROW 0 (C[6:0] = 0) • Display is not mirrored (MX = 0; MY = 0) • Internal oscillator is off 2004 May 17 33 MY Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 13.6 PCF8811 Set Y address of RAM 13.8 Y[3:0] defines the Y address of the display RAM. L[6:0] is used to select the display line address of the display RAM to be displayed on the initial row, ROW 0. The selection of L is limited to steps of 8. When the icon row is selected, the selection of L is limited to steps of 16. When a partial mode is selected, the selection of L is also limited in steps. In addition, the selection of L = 72 is not allowed when the icon row is enabled or disabled. Table 18 X/Y address range Y3 Y2 Y1 Y0 CONTENT ALLOWED X RANGE 0 0 0 0 bank 0 (display RAM) 0 to 127 0 0 0 1 bank 1 (display RAM) 0 to 127 0 0 1 0 bank 2 (display RAM) 0 to 127 0 0 1 1 bank 3 (display RAM) 0 to 127 0 1 0 0 bank 4 (display RAM) 0 to 127 0 1 0 1 bank 5 (display RAM) 0 to 127 0 1 1 0 bank 6 (display RAM) 0 to 127 0 1 1 1 bank 7 (display RAM) 0 to 127 1 0 0 0 bank 8 (display RAM) 0 to 127 1 0 0 1 bank 9 (display RAM) 0 to 127 The initial row can, in turn, be set by C[6:0]. ROW 0 cannot be set to the icon row ROW 79 when enabled. An example of the mapping from the RAM content to the display is illustrated in Fig.30. The content of the RAM is not modified. This feature allows, for instance, screen scrolling without rewriting the RAM. When the icon row is enabled this icon row (ROW 79) will always be in bank 9 independent of the mux rate which is programmed. 13.7 Set X address of RAM The X address points to the columns. The range of X is 0 to 127 (7FH). 2004 May 17 Set display start line 34 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver set initial display line and start row when MY = 0 handbook, full pagewidth X address PCF8811 RAM Display 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 8 9 L=8 C = 16 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 ROW 8 ROW 9 ROW 10 ROW 11 ROW 12 ROW 13 ROW 14 ROW 15 ROW 16 ROW 17 ROW 18 ROW 19 ROW 20 ROW 21 ROW 22 ROW 23 ROW 24 ROW 25 ROW 26 ROW 27 ROW 28 ROW 29 ROW 30 ROW 31 ROW 64 ROW 65 ROW 66 ROW 67 ROW 68 ROW 69 ROW 70 ROW 71 ROW 72 ROW 73 ROW 74 ROW 75 ROW 76 ROW 77 ROW 78 ROW 79 MGW751 Fig.30 Programming the L address and C address when MY = 0. 2004 May 17 35 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 13.9 PCF8811 Bias levels The bias levels for an MRA driving method with p = 8 are given in Fig.31 when Gmax and F have the same value. The value p defines the number of rows which are simultaneously selected. handbook, full pagewidth VLCD G max = F = VLCD V3_H 0.75G max V2_H 0.50G max V1_H 0.25G max VC VC V1_L −0.75G max V2_L −0.50G max V3_L −0.25G max −G max = F = VSS VSS MGW752 Fig.31 Bias levels for a MRA system with p = 8 and Gmax = F. The row voltage F depends on the mux rate selected (number of rows N), the threshold voltage of the liquid (VTH), the number of simultaneously selected rows (p) and the multiplexibility (m): N m± m – N 1 F = ------- × V TH × ---- × -------------------------------2 m–1 p (1) The column voltages are situated around the common level VC. The column voltage levels are equidistant from each other. In Table 19 the column voltage levels are given as a function of F. 2004 May 17 36 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 Table 19 Bias levels for MRA driving method SYMBOL BIAS VOLTAGES DC SHIFTED BIAS VOLTAGES F = Gmax VLCD V3_H F VLCD F ( p – 2 ) × ---------------------------------m– m–N V LCD (p – 2) ------------- × 1 + ---------------------------------- 2 m– m–N V2_H F ( p – 4 ) × ---------------------------------m– m–N V LCD (p – 4) ------------- × 1 + ---------------------------------- 2 m– m–N V1_H F ( p – 6 ) × ---------------------------------m– m–N V LCD (p – 6) ------------- × 1 + ---------------------------------- 2 m– m–N VC 0 1/ V1_L F – ( p – 6 ) × ---------------------------------m– m–N V LCD (p – 6) ------------- × 1 – ---------------------------------- 2 m– m–N V2_L F – ( p – 4 ) × ---------------------------------m– m–N V LCD (p – 4) ------------- × 1 – ---------------------------------- 2 m– m–N V3_L F – ( p – 2 ) × ---------------------------------m– m–N V LCD (p – 2) ------------- × 1 – ---------------------------------- 2 m– m–N VSS −F VSS The row voltages (F) are not necessarily larger then the column voltages. This depends on the number of rows which are selected, the multiplexibility and the value of p. However, the PCF8811 is designed in such a way that the maximum column voltages are always equal to the row voltages. In Table 20 the VLCD and the different bias levels are given for the PCF8811. The VLCD voltage is defined as: V LCD = 2 × F This is only possible for the mux rates 1 : 64 and 1 : 80. If other mux rates are chosen the PCF8811 determines the optimum value of p. By setting the value of p manually a compromise can be made between contrast and power consumption with certain liquids for the high mux rates 1 : 64 and 1 : 80. However, care must be taken that the liquid which is chosen ensures that the row voltages (F) and the maximum column voltages are equal. (2) Table 20 Relationship between mux rates and bias setting variables without icon row Where F is defined in (1) The bias system settings for different display modes are given in Table 20. All bias levels can be calculated by using the third column of Table 19 and the variables given in Table 20. Programming of the bias levels is not necessary in the PCF8811. The selection of the appropriate bias level voltages for each display mode is done automatically. Only the appropriate VLCD voltage must be programmed according to equations (1) and (2) for the display modes listed in Table 20. The variables for calculating VLCD, when the icon row is enabled, are given in Table 21. The icon row can only be addressed in the extended command set. The PCF8811 allows the value of p, for certain mux rates, to be chosen manually. 2004 May 17 2VLCD 37 MUX RATE N m p 1 : 16 1 : 24 1 : 32 1 : 40 1 : 48 1 : 56 1 : 64 1 : 72 1 : 80 16 24 32 40 48 56 64 72 80 25 49 81 49 64 81 64 81 81 2 2 2 4 4 4 8 8 8 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 Table 21 Relationship between mux rates and bias setting variables with the icon row (only extended command set) MUX RATE N m p 1 : 16 24 49 2 1 : 32 40 49 4 1 : 48 56 81 8 1 : 64 80 81 8 1 : 80 80 81 8 13.10 Set VOP value For mux rate 1 : 80 the optimum operation voltage of a liquid can be calculated with the variables given in Table 21 and equations (1) and (2). 80 81 – 81 – 80 2 V LCD = ------- × V TH × ------ × ---------------------------------------- = 4.472 × V TH 2 81 – 1 8 (3) Where VTH is the threshold voltage of the liquid crystal material used. The way of programming the VOP value is implemented differently in the basic command set in comparison to the extended command set. In the basic command set two commands are sent to the PCF8811: namely VPR[5:0] and VOFF[2:0]. In the extended command set only one command VPR[7:0] is sent to the PCF8811. This VOP programming is illustrated in Fig.32. The programming of VOP in the basic command set can be used when the PCF8811 is used as a replacement for an IAPT LCD driver. A conversion table (ROM) can be provided which transfers the programming of an IAPT VOP value to a MRA VOP value. EXT = 1 handbook, full pagewidth VPR [7:0] MMVOPCAL [4:0] EXT = 0 VPR [5:0] VOFF [2:0] VOS [4:0] b a EXT 7 6 5 4 3 2 1 0 2 1 0 1 VLCD 0 LOOK-UP TABLE rom_add[8:0] VOP [7:0] ROM MGW753 Fig.32 Setting of VOP in the basic and extended command set. 2004 May 17 38 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 13.10.1 BASIC COMMAND SET Instead of using the VLCD offset pads (VOP[4:0]) the VLCD can be adjusted with the module maker calibration setting MMVOPCAL[4:0]; see Chapter 22. (5) V LCD ( T = T ) = a + ( V OS [4:0] + V PR [7:0] ) × b The VLCD at T = TCUT in the basic command set is determined by the conversion in the ROM look-up table with the programmed values of VPR[5:0] and VOFF[2:0]. It can, additionally, be adjusted with the VLCD offset pads VOS[4:0] to obtain the optimum optical performance. Instead of using the VLCD offset pads (VOP[4:0]) the VLCD can be adjusted with the module maker calibration setting MMVOPCAL[4:0]; see Chapter 22. (4) V LCD ( T = T ) = a + ( V OS [4:0] + V OP [7:0] ) × b CUT Where: • TCUT is a reference temperature (see Section 13.11) • a is a fixed constant value (see Table 22) • b is a fixed constant value (see Table 22) • VPR[7:0] is the programmed VOP value CUT • VOS[4:0]/MMVOPCAL[4:0] is the value of the offset VLCD offset pads or the value stored in the OTP cells. Where: • TCUT is a reference temperature; see Section 13.11 • a is a fixed constant value; see Table 22 As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD (9 V) the user has to ensure while setting the VPR register and selecting the Temperature Compensation (TC), that under all conditions and including all tolerances the VLCD remains below 9.0 V. This is valid for the two different command sets. • b is a fixed constant value; see Table 22 • VOP[7:0] is the result of the conversion table • VOS[4:0]/MMVOPCAL[4:0] is the value of the offset VLCD offset pads or the value stored in the OTP cells. Table 22 Parameters of VLCD for the basic and extended command set SYMBOL VALUE UNIT TCUT 40 °C b 0.03 V a 3 V 13.10.2 EXTENDED COMMAND SET The VLCD at T = TCUT can be calculated with equation (5). In the extended command set VPR[7:0] is the same value as VOP[7:0]. It can additionally be adjusted with the VLCD offset pads VOS[4:0] to obtain the optimum optical performance. 2004 May 17 39 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth MGT847 V LCD b a 00 01 02 03 04 05 06 ... ... FD FE FF V OP VOP[7:0] programming, (00H to FFH). Fig.33 VLCD programming of PCF8811. 13.11 Temperature control Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage VLCD might have to be increased at lower temperature to maintain optimum contrast. handbook, halfpage MGW754 VLCD The VLCD at a specific temperature is calculated as follows for both command sets. VLCD (at T = TCUT) is given by equations (4) or (5), depending on the command set which is used. (6) V LCD = V LCD × [ 1 + ( T – T CUT ) × TC ] (T) ( T = T CUT ) In the extended command set and basic command set 8 different temperature coefficients are available (see Fig.34). The typical values of the different temperature coefficients are given in Chapter 16. The coefficients are proportional to the programmed VLCD. TCUT The basic and extended command set differ in the way that the temperature coefficients can be accessed. In the basic command set only one temperature coefficient is available. However, the possibility exists to program the default temperature coefficient by means of OTP programming; see Chapter 22. In the extended command set the different temperature coefficients are selected by the interface with three bits TC[2:0]. 2004 May 17 Fig.34 Temperature coefficients. 40 T Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 14 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); notes 1 and 2. SYMBOL PARAMETER MIN. MAX. UNIT VDD1 general supply voltage −0.5 +6.5 V VDD2, VDD3 supply voltage for the internal voltage generator −0.5 +4.5 V VLCD LCD supply voltage −0.5 +10.0 V Vi all input voltages −0.5 VDD1 + 0.5 V ISS ground supply current −50 +50 mA Ii, Io DC input or output current −10 +10 mA Ptot total power dissipation − 300 mW Pout power dissipation per output − 30 mW Tstg storage temperature −65 +150 °C Notes 1. Stresses above those listed under limiting values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are referenced to VSS unless otherwise specified. 15 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ). 2004 May 17 41 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 16 DC CHARACTERISTICS VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = 3.0 V to 9.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. SYMBOL VDD1 PARAMETER CONDITIONS general supply voltage basic command set; when using ROM look-up table (see Section 13.10) MIN. TYP. MAX. UNIT 1.7 − 3.3 V 2.0 − 3.3 V 1.8 − 3.3 V VDD2, VDD3 supply voltage for the internal voltage generator VLCDIN LCD supply voltage LCD voltage externally supplied (voltage generator disabled) − − 9.0 V VLCDOUT voltage multiplier output voltage LCD voltage internally − generated (voltage generator enabled); note 1 − 9.0 V VLCD(tol) tolerance of generated VLCD without calibration −300 − +300 mV with calibration; note 2 −70 − +70 mV notes 3 and 4 0.5 1.5 5 µA notes 4 and 5 15 25 50 µA notes 3 and 4 0 0.5 1 µA notes 5 and 4 130 150 200 µA notes 5 and 4 145 175 250 µA − 0.2VDD1 V IDD1 general supply current IDD2, IDD3 supply current for the internal voltage generator IDD(tot) total supply current (VDD1 + VDD2 + VDD3) Logic inputs; MF[2:0], VOS[4:0], DS0, EXT, PS[2:0], RES and OSC VIL LOW-level input voltage VSS VIH HIGH-level input voltage 0.8VDD1 − VDD1 V IL leakage current VI = VDD or VSS −1 − +1 µA Column and row outputs Rcol column output resistance COL 0 to COL 127 VLCD = 5 V − − 5 kΩ Rrow row output resistance ROW 0 to ROW 79 VLCD = 5 V − − 5 kΩ Vbias(col) bias tolerance voltage COL 0 to COL 127 −100 0 +100 mV Vbias(row) bias tolerance voltage ROW 0 to ROW 80 −100 0 +100 mV LCD supply voltage generator TC0 VLCD temperature coefficient 0 − 0 − /°C TC1 VLCD temperature coefficient 1 − −0.16 × 10−3 − /°C TC2 VLCD temperature coefficient 2 − −0.33 × 10−3 − /°C − −0.50 × 10−3 − /°C 10−3 TC3 VLCD temperature coefficient 3 TC4 VLCD temperature coefficient 4 − −0.66 × − /°C TC5 VLCD temperature coefficient 5 − −0.833 × 10−3 − /°C 2004 May 17 42 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver SYMBOL TC6 TC7 PARAMETER PCF8811 CONDITIONS MIN. VLCD temperature coefficient 7 note 6 MAX. UNIT −1.25 × 10−3 − /°C − −1.66 × 10−3 − /°C − − VLCD temperature coefficient 6 TYP. Parallel interface; VDD1 = 1.8 V to 3.3 V VIL LOW-level input voltage VSS VIH HIGH-level input voltage 0.8VDD1 − 0.2VDD1 V VDD1 V Serial interface; VDD1 = 1.7 V to 3.3 V − VIL LOW-level input voltage VSS 0.2VDD1 V VIH HIGH-level input voltage 0.8VDD1 − VDD1 V VOL = 0.4 V; VDD1 > 2 V − − 3 mA VOL = 0.2VDD1; VDD1 < 2 V − − 2 mA − 0.3VDD1 V I2C-bus interface; VDD1 = 1.8 V to 3.3 V IOL(SDA) LOW-level output current at pin SDA VIL LOW-level input voltage VSS VIH HIGH-level input voltage 0.7VDD1 − VDD1 V Output levels for all interfaces − VOL LOW-level output voltage IOL = 0.5 mA VSS VOH HIGH-level output voltage IOH = −0.5 mA 0.8VDD1 − 0.2VDD1 V VDD1 V Notes 1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. Valid for values of temperature, VPR and TC used at calibration. 3. During power-down all static currents are switched off. 4. Conditions are: VDD1 = 1.8 V, VDD2 = 2.7 V, VLCD = 8.05 V, voltage multiplier 4VDD2, inputs at VDD1 or VSS, interface inactive, internal VLCD generation, VLCD output is loaded by 10 µA and Tamb = 25 °C. 5. Normal mode. 6. TC7 can only be used when VDD2 = VDD3 = 2.4 V or higher. 17 AC CHARACTERISTICS VDD1 = 1.7 V to 3.3 V; VSS = 0 V; VLCD = maximum 9.0 V; Tamb = −40 °C to +85 °C; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT − 200 − kHz 54 60 66 Hz fext external clock frequency fframe frame frequency Tamb = 25 °C; VDD1 = 2.4 V 43 58 73 Hz tVHRL VDD to RES LOW see Fig.43 0(2) − 1 µs tRW RES LOW pulse width see Fig.43 500 − − ns Notes 1. All specified timings are based on 20 % and 80 % of VDD. 2. RES may be LOW before VDD goes HIGH. 2004 May 17 43 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 18 PARALLEL INTERFACE TIMING CHARACTERISTICS VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD = maximum 9.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. SYMBOL PARAMETER MIN. MAX. UNIT Parallel bus timing; see Figs 35 and 36 6800 SERIES tSU;DC data/command set-up time 40 − ns tHD;DC data/command hold time 20 − ns Tcyc(DS) data strobe cycle time 1000 − ns tDS(L) data strobe LOW time 320 − ns tDS(H) data strobe HIGH time 300 − ns tSU;RW read/write set-up time 280 − ns tHD;RW read/write hold time 20 − ns tSU;CE chip enable set-up time 280 − ns tHD;CE chip enable hold time 0 − ns tSU;DAT data set-up time 20 − ns tHD;DAT data hold time 40 − ns tDAT;ACC data output access time − 280 ns tDAT;OH data output disable time − 20 ns 2004 May 17 44 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth RW t SU;CE t SU;RW t HD;CE t HD;RW t SU;DC t HD;DC D/C SCE Tcyc(DS) t DS(H) t DS(L) E t SU;DAT t HD;DAT D0 to D7 (write) t DAT;ACC t DAT;OH D0 to D7 (read) MGW755 Fig.35 Parallel interface timing (6800-series) (read). 2004 May 17 45 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth D/C, RW t SU;RW t HD;RW t SU;DC t HD;DC D/C E Tcyc(DS) t DS(L) t DS(H) SCE t SU;DAT t HD;DAT D0 to D7 (Write) t DAT;ACC t DAT;OH D0 to D7 (Read) MGW756 Fig.36 Parallel interface timing (6800-series) (write). 2004 May 17 46 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 19 SERIAL INTERFACE TIMING CHARACTERISTICS VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD = maximum 9.0 V; Tamb = −40 °C to +85 °C; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT 3-line and 4-line (SPI and serial interface); see Fig.37 to Fig.40 fSCLK clock frequency 9.00 − MHz Tcyc clock cycle SCLK 111 − ns tPWH1 SCLK pulse width HIGH 45 − ns tPWL1 SCLK pulse width LOW 45 − ns tS2 SCE set-up time 50 − ns tH2 SCE hold time 45 − ns tPWH2 SCE minimum high time 50 − ns tH5 SCE start hold time 50 − ns tS4 SDIN set-up time 50 − ns tH4 SDIN hold time 50 − ns tS3 data/command set-up time 50 − ns tH3 data/command hold time 50 − ns tS1 SDIN set-up time 50 − ns tH1 SDIN hold time 50 − ns t1 SDOUT access time − 50 ns t2 SDOUT disable time − 50 ns t3 SCE hold time 50 − ns t4 SDOUT disable time note 4 25 100 ns Cb capacitive load for SDO note 5 − 30 pF Rb series resistance for SDO note 5 − 500 Ω note 2 note 3 Notes 1. All specified timings are based on 20 % and 80 % of VDD. 2. tH5 is the time from the previous SCLK rising edge (irrespective of the state of SCE) to the falling edge of SCE. 3. SDOUT disable time for SPI 3-line or 4-line interface. 4. SDOUT disable time for serial interface 3-line. 5. Maximum values are for fSCLK = 9 MHz. Series resistance includes ITO track + connector resistance + printed-circuit board. 2004 May 17 47 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 t S2 handbook, full pagewidth t H2 t PWH2 SCE t H5 (t H5 ) T cyc t PWL1 t S2 t PWH1 SCLK t H1 t S1 SDATA MGW757 Fig.37 3-line serial interface timing. t S2 handbook, full pagewidth t H2 t PWH2 SCE t S3 t H3 t H5 (t H5 ) D/C T cyc t PWL1 t S2 t PWH1 SCLK t S4 t H4 SDATA MGW758 Fig.38 4-line serial interface timing. 2004 May 17 48 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth SCE t3 SCLK t H1 t S1 SDATA t1 t2 SDOUT MGW759 Fig.39 Serial interface timing; read mode SPI 3- or 4-line. handbook, full pagewidth SCE t3 SCLK t H1 t S1 SDATA t1 t4 SDOUT MGW760 Fig.40 Serial interface timing; read mode serial interface 3-line. 2004 May 17 49 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 20 I2C-BUS INTERFACE TIMING CHARACTERISTICS VDD1 = 1.8 V to 3.3 V; VSS = 0 V; VLCD = maximum 9.0 V; Tamb = −40 °C to +85 °C; note 1; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Fs-mode; see Fig.41 fSCLH SCLH clock frequency 0 − 400 kHz tSU;STA set-up time (repeated) START condition 600 − − ns tHD;STA hold time (repeated) START condition 600 − − ns tLOW LOW period of the SCLH clock 1300 − − ns tHIGH HIGH period of the SCLH clock 600 − − ns tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 0 − 900 ns tr SCL and SDA rise time note 2 20 + 0.1Cb − 300 ns tf SCL and SDA fall time note 2 20 + 0.1Cb − 300 ns Cb capacitive load represented by each bus line − − 400 pF tSU;STO set-up time for STOP condition 600 − − ns tSP tolerable spike width on bus − − 50 ns tBUF bus free time between START and STOP condition 1300 − − ns VnL noise margin at the LOW level for each connected device (including hysteresis) 0.1VDD1 − − V VnH noise margin at the HIGH-level for each connected device (including hysteresis) 0.2VDD1 − − V Hs-mode; see Fig.42 fSCLH SCLH clock frequency 0 − 3.4 MHz tSU;STA set-up time (repeated) START condition 160 − − ns tHD;STA hold time (repeated) START condition 160 − − ns tLOW LOW period of the SCLH clock 160 − − ns tHIGH HIGH period of the SCLH clock 60 − − ns tSU;DAT data set-up time 10 − − ns tHD;DAT data hold time 20 − 70 ns trCL rise time of the SCLH signal 10 − 40 ns trCL1 rise time of the SCLH signal after the acknowledge bit 10 − 80 ns tfCL fall time of the SCLH signal 10 − 40 ns trDA rise time of the SDAH signal 10 − 80 ns tfCL1 fall time of the SCLH signal 10 − 80 ns 2004 May 17 50 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver SYMBOL PARAMETER PCF8811 CONDITIONS MIN. TYP. MAX. UNIT 160 − − ns note 2 − − 100 pF note 2 − − 400 pF tolerable spike width on bus − − 5 ns VnL noise margin at the LOW-level for each connected device (including hysteresis) 0.1VDD1 − − V VnH noise margin at the HIGH-level for each connected device (including hysteresis) 0.2VDD1 − − V tSU;STO set-up time for STOP condition Cb2 capacitive load for the SDAH and SCLH lines Cb capacitive load for the SDAH + SDA line and SCLH + SCL line tSP Notes 1. All specified output timings are based on 20 % and 80 % of VDD1. 2. Cb = 100 pF total capacitance of one bus line. handbook, full pagewidth SDA tLOW tf tr tSU;DAT tf tHD;STA tSP tr tBUF SCL S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S MSC610 S = Start. Sr = Start repeated. P = Stop. Fig.41 I2C-bus timing diagram (Fs-mode). 2004 May 17 51 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver handbook, full pagewidth Sr PCF8811 Sr trDA tfDA P SDAH tSU;STA tHD;DAT tSU;STO tHD;STA tSU;DAT SCLH tfCL trCL1 (1) trCL1 trCL tHIGH tLOW tLOW (1) tHIGH MGK871 = MCS current source pull-up = Rp resistor pull-up (1) Rising edge of the first SCLH clock pulse after an acknowledge bit. Fig.42 I2C-bus timing diagram (Hs-mode). handbook, full pagewidth VDD t RW t RW RES VDD t VHRL t RW t RW RES MGW761 Fig.43 Reset timing. 2004 May 17 52 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 21 APPLICATION INFORMATION Semiconductors are light sensitive. Exposure to light sources can cause malfunction of the IC. In the application it is therefore required to protect the IC from light. The protection has to be done on all sides of the IC, i.e. front, rear and all edges. The pinning of the PCF8811 has an optimum design for single plane wiring e.g. for chip-on-glass display modules. Display size: 80 × 128 pixels. For further application information refer to Philips Application note AN10170. handbook, full pagewidth VSS1 VSS2 VDD2 VDD1 PCF8811 VLCDSENSE VLCDOUT VLCDIN DISPLAY 80 × 128 pixels CVLCD I/O CVDD VDD VSS MGW762 Fig.44 Application diagram: internal charge pump is used and a single supply. handbook, full pagewidth VSS1 VSS2 VDD1 VDD2 PCF8811 C VDD1 VDD1 I/O VLCDSENSE VLCDOUT VLCDIN DISPLAY 80 × 128 pixels CVLCD CVDD2 VSS VDD2 MGW763 Fig.45 Application diagram: internal charge pump is used and two separate supplies (VDD1 and VDD2). 2004 May 17 53 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 handbook, full pagewidth I/O VSS1 VSS2 VDD2 VDD1 PCF8811 VLCDSENSE VLCDOUT VLCDIN DISPLAY 80 × 128 pixels CVDD VDD VSS VLCDIN MGW764 Fig.46 Application diagram: external high voltage is used. The required minimum value for the external capacitors in an application with the PCF8811 are: CVLCD = 1 µF to 4.7 µF depending on the application CVDD, CVDD1 and CVDD2 = 1 µF. For these capacitors higher values can be used. 2004 May 17 54 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 22 MODULE MAKER PROGRAMMING In theory, both may be used together but it is recommended that the VOS pins are tied to VSS when OTP calibration is being used. This will set them to a default offset of zero. If both are used then the addition of the two 5-bit numbers must not exceed a 5-bit result otherwise the resultant value will be undefined. The final adder in the circuit has underflow and overflow protection. In the event of an overflow, the output will be clamped to 255; during an underflow the output will be clamped to 0. The One Time Programmable (OTP) technology is implemented on the PCF8811. It enables the module maker to program some extended features of the PCF8811 after it has been assembled on an LCD module. Programming is made under the control of the interfaces and the use of one special pin. This pin must be made available on the module glass but need not to be accessed by the set maker. The final control to the high voltage generator, VOP, will be the sum of all the calibration registers and pins. The VLCD equation (4) or (5) given in Section 13.10 must be extended to include the OTP calibration, as follows; (7) V LCD ( T = T ) = a + ( V OS [4:0] The PCF8811 features 3 module maker programmable parameters: • VLCD calibration • Temperature coefficient selection CUT + MMVOPCAL[4:0] + V OP [7:0] ) × b • Seal bit. 22.1 The possible MMVOPCAL[4:0] values are the same as the VOS[4:0] values; see Table 12. VLCD calibration The first feature included is the ability to adjust the VLCD voltage with a 5-bit code (MMVOPCAL). This code is implemented in twos complement notation giving rise to a positive or negative offset to the VPR register. This is in the same manner as the on-glass calibration pins VOS. handbook, full pagewidth OTP VLCD calibration: 5-bit offset range −16 to +15 MMVOPCAL[4:0] laser trim pins: 5-bit offset range −16 to +15 + + VOS[4:0] range 0 to +255 usable range +32 to +255 VPR register: 8-bit value VPR [7:0] Fig.47 VLCD calibration. 2004 May 17 55 VOP [7:0] range: 0 to +255 to high voltage generator MGU287 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 22.2 PCF8811 This OTP architecture allows the following operations: Temperature coefficient selection 1. Reading data from the OTP cells. The content of the non-volatile OTP cells is transferred to the shift register where upon it may affect the PCF8811 operation. The second feature is an OTP factory default setting for the temperature coefficient selection (MMTC) in the basic command set. This 3-bit value will be loaded from OTP after leaving the power-save mode or by the refresh command. The idea of this feature is to provide, in the basic command set, the complete set of temperature coefficients without an additional command. In the extended command set the temperature coefficient can be programmed as given in Table 16. 22.3 2. Writing data to the OTP cells. First, all 9 bits of data are shifted into the shift register via the interface. The content of the shift register is then transferred to the OTP cells (there are some limitations related to storing data in these cells; see Section 22.7). 3. Checking calibration without writing to the OTP cells. Shifting data into the shift register allows the effects on the VLCD voltage to be observed. Seal bit The module maker programming is performed in a special mode: the calibration mode (CALMM). This mode is entered via a special interface command, CALMM. To prevent wrongful programming, a seal bit has been implemented which prevents the device from entering the calibration mode. This seal bit, once programmed, can not be reversed, thus further changes in programmed values are not possible. The reading of data from the OTP cells is initiated by either: • Exit from power-save mode • The ‘Refresh’ command (power control). It should be noted that in both cases the reading operation needs up to 5 ms to complete. Applying the programming voltages when not in CALMM mode will have no effect on the programmed values. The shifting of data into the shift register is performed in the special mode CALMM. In the PCF8811 the CALMM mode is entered by the CALMM command. Once in the CALMM mode the data is shifted into the shift register via the interface at the rate of 1-bit per command. After transmitting the last (9th) bit and exiting the CALMM mode, the serial interface will return to the normal mode and all other commands can be sent. Care should be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the CALMM mode, otherwise the bits will be in the wrong positions. Table 23 Seal bit definition SEAL BIT 22.4 ACTION 0 possible to enter calibration mode 1 calibration mode disabled OTP architecture The OTP circuitry in the PCF8811 contains 9 bits of data: 5 for VLCD calibration (MMVOPCAL), 3 for the temperature coefficient default setting in the basic command set MMTC and 1 seal bit. The circuitry for 1-bit is called an OTP slice. Each OTP slice consists of 2 main parts: the OTP cell (a non-volatile memory cell) and the shift register cell (a flip-flop). The OTP cells are only accessible through their shift register cells: on the one hand both reading from and writing to the OTP cells is performed with the shift register cells, on the other hand only the shift register cells are visible to the rest of the circuit. The basic OTP architecture is shown in Fig.48. 2004 May 17 In the shift register the value of the seal bit is, like the others, always zero at reset. To ensure that the security feature works correctly, the CALMM command is disabled until a refresh has been performed. Once the refresh is completed, the seal bit value in the shift register will be valid and permission to enter the CALMM mode can thus be determined. The 9 bits are shifted into the shift register in a predefined order: first 5 bits of MMVOPCAL[4:0], 3 bits for MMTC[2:0] and lastly the seal bit. The MSB is always first, thus the first bit shifted is MMVOPCAL[4] and the two last bits are MMTC[0] and the seal bit. 56 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 DATA TO THE CIRCUIT FOR CONFIGURATION AND CALIBRATION handbook, full pagewidth OTP slice SHIFT REGISTER FLIP-FLOP read data from the OTP cell SHIFT REGISTER DATA INPUT SHIFT REGISTER write data to the OTP cell OTP CELLs MGU289 OTP CELL Fig.48 Basic OTP architecture. 22.5 Interface commands These instructions are in addition to those indicated in Table 5. Table 24 Additional instructions; note 1 COMMAND BYTE NAME EXT D/C R/W ACTION D7 D6 D5 D4 D3 D2 D1 D0 CALMM X 0 0 1 0 0 0 0 0 1 0 enter CALMM mode Power control (‘Refresh’) X 0 0 0 0 1 0 1 PC1 PC0 1 switch HVgen on/off to force a refresh of the shift register Note 1. X = don’t care. 22.5.1 CALMM This instruction puts the device in calibration mode. This mode enables the shift register for loading and allows programming of the non-volatile OTP cells to take place. If the seal bit is set then this mode cannot be accessed and the instruction will be ignored. Once in calibration mode all commands are interpreted as shift register data. The mode can only be exited by sending data with bit D7 set to logic 0. Reset will also clear this mode. Each shift register data byte is preceded by D/C = 0 and has only 2 significant bits, thus the remaining 6 bits are ignored. Bit D7 is the continuation bit (D7 = 1 remain in CALMM mode, D7 = 0 exit CALMM mode). Bit D0 is the data bit and its value is shifted into the OTP shift register (on the falling edge of SCLK). 2004 May 17 57 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver 22.5.2 PCF8811 It is assumed that the PCF8811 has just been reset. After transmitting the last bit the PCF8811 can exit or remain in the CALMM mode (see step 1). It should be noted that while in CALMM mode the interface does not recognize commands in the normal sense. REFRESH The action of the ‘Refresh’ instruction is to force the OTP shift register to re-load from the non-volatile OTP cells. This instruction takes up to 5 ms to complete. During this time all other instructions may be sent. After this sequence has been applied it is possible to observe the impact of the data shifted in. The described sequence is, however, not useful for OTP programming because the number of bits with the value logic 1 is greater than that allowed for programming; see Section 22.7. Figure 49 shows the shift register after this action. In the PCF8811 the ‘Refresh’ instruction is associated with the ‘Power control’ instruction so that the shift register is automatically refreshed every time the high voltage generator is enabled or disabled. It should be noted however, that if this instruction is sent while in the power-save mode, the PC[1:0] bits will be updated but the refreshing will be ignored. 22.6 Example of filling the shift register An example of the sequence of commands and data is shown in Table 25. In this example the shift register is filled with the following data: MMVOPCAL = −4 (11100 BIN), MMTC = 2 (010 BIN) and the seal bit is 0. Table 25 Example sequence for filling the shift register; note 1 STEP 1 EXT D/C R/W D7 D6 D5 D4 D3 D2 D1 D0 X 0 0 1 1 1 0 0 0 0 1 2 ACTION exit Power-down wait 5 ms for refresh to take effect 3 X 0 0 1 0 0 0 0 0 1 0 enter CALMM mode 4 X 0 0 1 X X X X X X 1 shift in data. MMVOPCAL[4] is first bit; note 2 5 X 0 0 1 X X X X X X 1 MMVOPCAL[3] 6 X 0 0 1 X X X X X X 1 MMVOPCAL[2] 7 X 0 0 1 X X X X X X 0 MMVOPCAL[1] 8 X 0 0 1 X X X X X X 0 MMVOPCAL[0] 9 X 0 0 1 X X X X X X 0 MMTC[2] 10 X 0 0 1 X X X X X X 1 MMTC[1] 11 X 0 0 1 X X X X X X 0 MMTC[0] 12 X 0 0 0 X X X X X X 0 seal bit; exit CALMM mode X X X 0 seal bit; remain in CALMM mode An alternative ending could be to stay in CALMM mode 13 X 0 0 1 X X X Notes 1. X = don’t care. 2. The data for the bits is not in the correct shift register position until all bits have been sent. 2004 May 17 58 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 OTP SHIFT REGISTER handbook, full pagewidth shifting direction SEAL BIT = 0 LSB MMTC [2:0] MSB 0 1 0 LSB 0 MMVOPCAL [4:0] 0 1 1 MSB 1 MGW765 Fig.49 Shift register contents after example sequence of Table 25. 22.7 Programming flow It should be noted that the programming specification refers to the voltages at the chip pins, contact resistance must therefore be considered by the user. Programming is achieved whilst in CALMM mode and with the application of the programming voltages. As mentioned previously, the data for programming the OTP cell is contained in the corresponding shift register cell. The shift register cell must be loaded with a logic 1 in order to program the corresponding OTP cell. If the shift register cell contains a logic 0, then no action will take place when the programming voltages are applied. An example sequence of commands and data for OTP programming is given in Table 26. The order for programming cells is not significant. However, it is recommended that the seal bit is programmed last. Once this bit has been programmed it will not be possible to re-enter the CALMM mode. Once programmed, an OTP cell cannot be de-programmed. An already programmed cell, i.e. an OTP cell containing a logic 1, must not be re-programmed. It is assumed that the PCF8811 has just been reset. During programming a substantial current flows in the VLCDIN pin. For this reason it is recommended to program only one OTP cell at a time. This is achieved by filling all but one shift register cells with logic 0. 2004 May 17 59 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 Table 26 Sequence for OTP programming; note 1 STEP EXT 1 X D/C R/W D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 0 0 0 0 1 2 ACTION exit power-save wait 5 ms for refresh to take effect 3 X 0 0 1 0 1 0 1 0 0 1 re-enter Power-down (DON = 0) 4 X 0 0 1 0 0 0 0 0 1 0 enter CALMM mode 5 X 0 0 1 0 X X X X X 1 shift in data; MMVOPCAL[4] is first bit 6 X 0 0 1 0 X X X X X 1 MMVOPCAL[3] 7 X 0 0 1 0 X X X X X 1 MMVOPCAL[2] 9 X 0 0 1 0 X X X X X 0 MMVOPCAL[1] 10 X 0 0 1 0 X X X X X 0 MMVOPCAL[0] 11 X 0 0 1 0 X X X X X 0 MMTC[2] 12 X 0 0 1 0 X X X X X 1 MMTC[1] 13 X 0 0 1 0 X X X X X 0 MMTC[0] 14 X 0 0 1 1 X X X X X 0 seal bit; remain in CALMM mode 15 apply programming voltage at pins VOTPPROG and VLCDIN according to Section 22.8 Repeat steps 5 to 14 for each bit that should be programmed to 1 16 apply external reset Note 1. X = don’t care. 22.8 Programming specification Table 27 Programming specification; see Fig.50 SYMBOL VOTPPROG VLCDIN PARAMETER voltage applied to pin VOTPPROG relative to VSS1 voltage applied to pin VLCDIN relative to VSS1 CONDITIONS MIN. TYP. MAX. UNIT programming active; note 1 11.0 11.5 12.0 V programming inactive; note 1 VSS − 0.2 0 +0.2 V programming active; notes 1 and 2 9 9.5 10 V programming inactive; notes 1 and 2 VDD2 − 0.2 VDD2 4.5 V when programming a single bit to logic 1 − 850 1000 µA ILCDIN current drawn by VLCDIN during programming IVOTPPROG current drawn by VOTPPROG during programming − 100 200 µA Tamb(PROG) ambient temperature during programming 0 25 40 °C tSU;SCLK set-up time of internal data after last clock 1 − − µs 2004 May 17 60 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver SYMBOL PARAMETER PCF8811 CONDITIONS MIN. TYP. MAX. UNIT tHD;SCLK hold time of internal data before next clock 1 − − µs tSU;VOTPPROG set-up time of VOTPPROG prior to programming 1 − 10 µs tHD;VOTPPROG hold time of VOTPPROG after programming 1 − 10 ms tPW pulse width of programming voltage 100 120 200 ms Notes 1. The voltage drop across the ITO track and zebra connector must be taken into account to guarantee a sufficiently high voltage at the chip pins. 2. The Power-down mode (DON = 0 and DAL = 1) and CALMM mode must be active while the VLCDIN pin is being driven. tSU;SCLK handbook, full pagewidth tHD;SCLK SCLK VVOTPPROG VLCDIN tSU;VOTPROG tHD;VOTPPROG tPW Fig.50 Programming waveforms. 2004 May 17 61 MGW766 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 23 CHIP INFORMATION The PCF8811 is manufactured in n-well CMOS technology. The substrate is at VSS potential. 24 BONDING PAD LOCATIONS Table 28 Bonding pad information PAD ROWS/COLS SIDE INTERFACE SIDE UNIT Pad pitch min. 51.84 min. 54 µm Pad size (aluminium) 42.84 × 105 50 × 100 µm Bump dimensions 31.9 × 100 × 17.5 (±5) 34 × 95 × 17.5 (±5) µm Wafer thickness (excluding bumps) 381 (±25) µm 12.45 mm handbook, halfpage handbook, halfpage 2.31 mm PCF8811 90 µm y center pitch y x center x MGW768 MGW767 Fig.52 Shape of alignment mark (90 µm diameter). Fig.51 Chip size and pad pitch. 2004 May 17 62 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 Table 29 Bonding pad locations All x and y co-ordinates are referenced to the centre of the chip (dimensions in µm; see Fig.53). CO-ORDINATES SYMBOL CO-ORDINATES SYMBOL PAD x y dummy_slanted 1 6092 1030 alignment mark 2 5995 1017 dummy 3 5876 1030 dummy 4 5822 1030 dummy 5 5768 1030 dummy 6 5714 1030 dummy 7 5660 1030 dummy 8 5390 1030 MF2 9 5012 1030 MF1 10 4850 1030 MF0 11 4688 1030 DS0 12 4526 1030 OSC 13 4364 1030 EXT 14 4094 1030 PS0 15 3932 1030 PS1 16 3770 1030 PS2 17 3608 1030 VSS(tie off) 18 3446 1030 SDAHOUT 19 2960 1030 SDAH 20 2420 1030 SDAH 21 2366 1030 SCLH/SCE 22 1826 1030 SCLH/SCE 23 1772 1030 VOTPPROG 24 1664 1030 VOTPPROG 25 1610 1030 VOTPPROG 26 1556 1030 RES 27 1448 1030 D/C 28 1232 1030 R/W 29 962 1030 E 30 800 1030 VDD(tie off) 31 638 1030 DB0 32 476 1030 DB1 33 314 1030 DB2 34 152 1030 DB3 35 −10 +1030 2004 May 17 63 PAD x y DB4 36 −172 +1030 DB5 37 −334 +1030 DB6 38 −550 +1030 DB7 39 −712 +1030 VDD1 40 −874 +1030 VDD1 41 −928 +1030 VDD1 42 −982 +1030 VDD1 43 −1036 +1030 VDD1 44 −1090 +1030 VDD1 45 −1144 +1030 VDD2 46 −1198 +1030 VDD2 47 −1252 +1030 VDD2 48 −1306 +1030 VDD2 49 −1360 +1030 VDD2 50 −1414 +1030 VDD2 51 −1468 +1030 VDD2 52 −1522 +1030 VDD2 53 −1576 +1030 VDD2 54 −1630 +1030 VDD2 55 −1684 +1030 VDD3 56 −1738 +1030 VDD3 57 −1792 +1030 VDD3 58 −1846 +1030 VDD3 59 −1900 +1030 VDD3 60 −1954 +1030 VSS1 61 −2062 +1030 VSS1 62 −2116 +1030 VSS1 63 −2170 +1030 VSS1 64 −2224 +1030 VSS1 65 −2278 +1030 VSS1 66 −2332 +1030 VSS1 67 −2386 +1030 VSS1 68 −2440 +1030 VSS1 69 −2494 +1030 VSS1 70 −2548 +1030 VSS2 71 −2602 +1030 VSS2 72 −2656 +1030 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 CO-ORDINATES SYMBOL CO-ORDINATES PAD SYMBOL x y PAD x y VSS2 73 −2710 +1030 dummy 110 −6058 +1030 VSS2 74 −2764 +1030 dummy 111 −6112 +1030 VSS2 75 −2818 +1030 dummy 112 −6129.24 −1032.5 VSS2 76 −2872 +1030 dummy 113 −6077.40 −1032.5 VSS2 77 −2926 +1030 dummy 114 −6025.56 −1032.5 VSS2 78 −2980 +1030 R79 115 −5973.72 −1032.5 VSS2 79 −3034 +1030 R78 116 −5921.88 −1032.5 VSS2 80 −3088 +1030 R77 117 −5870.04 −1032.5 T5 81 −3250 +1030 R76 118 −5818.20 −1032.5 T2 82 −3304 +1030 R75 119 −5766.36 −1032.5 T1 83 −3466 +1030 R74 120 −5714.52 −1032.5 T4 84 −3628 +1030 R73 121 −5662.68 −1032.5 T3 85 −3790 +1030 R72 122 −5610.84 −1032.5 VOS4 86 −4060 +1030 R71 123 −5559.00 −1032.5 VOS3 87 −4222 +1030 R70 124 −5507.16 −1032.5 VOS2 88 −4384 +1030 R69 125 −5455.32 −1032.5 VOS1 89 −4654 +1030 R68 126 −5403.48 −1032.5 VOS0 90 −4816 +1030 R67 127 −5351.64 −1032.5 VLCDOUT 91 −4924 +1030 R66 128 −5299.80 −1032.5 VLCDOUT 92 −4978 +1030 R65 129 −5247.96 −1032.5 VLCDOUT 93 −5032 +1030 R64 130 −5196.12 −1032.5 VLCDOUT 94 −5086 +1030 R63 131 −5144.28 −1032.5 VLCDOUT 95 −5140 +1030 R62 132 −5092.44 −1032.5 VLCDOUT 96 −5194 +1030 R61 133 −5040.60 −1032.5 VLCDOUT 97 −5248 +1030 R60 134 −4988.76 −1032.5 VLCDOUT 98 −5302 +1030 R59 135 −4936.92 −1032.5 VLCDOUT 99 −5356 +1030 R58 136 −4885.08 −1032.5 VLCDSENSE 100 −5410 +1030 R57 137 −4833.24 −1032.5 VLCDIN 101 −5464 +1030 R56 138 −4781.40 −1032.5 VLCDIN 102 −5518 +1030 R55 139 −4729.56 −1032.5 VLCDIN 103 −5572 +1030 R54 140 −4677.72 −1032.5 VLCDIN 104 −5626 +1030 R53 141 −4625.88 −1032.5 VLCDIN 105 −5680 +1030 R52 142 −4574.04 −1032.5 VLCDIN 106 −5734 +1030 R51 143 −4522.20 −1032.5 VLCDIN 107 −5788 +1030 R50 144 −4470.36 −1032.5 alignment mark 108 −5904 +1017 R49 145 −4418.52 −1032.5 dummy 109 −6004 +1030 R48 146 −4366.68 −1032.5 2004 May 17 64 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 CO-ORDINATES SYMBOL CO-ORDINATES PAD SYMBOL x PAD y x y R47 147 −4314.84 −1032.5 C28 184 −2189.40 −1032.5 R46 148 −4263 −1032.5 C29 185 −2137.56 −1032.5 R45 149 −4211.16 −1032.5 C30 186 −2085.72 −1032.5 R44 150 −4159.32 −1032.5 C31 187 −2033.88 −1032.5 R43 151 −4107.48 −1032.5 C32 188 −1878.36 −1032.5 R42 152 −4055.64 −1032.5 C33 189 −1826.52 −1032.5 R41 153 −4003.80 −1032.5 C34 190 −1774.68 −1032.5 R40 154 −3951.96 −1032.5 C35 191 −1722.84 −1032.5 R80 (duplicate R79) 155 −3900.12 −1032.5 C36 192 −1671.00 −1032.5 C0 156 −3640.92 −1032.5 C37 193 −1619.16 −1032.5 C1 157 −3589.08 −1032.5 C38 194 −1567.32 −1032.5 C2 158 −3537.24 −1032.5 C39 195 −1515.48 −1032.5 C3 159 −3485.40 −1032.5 C40 196 −1463.64 −1032.5 C4 160 −3433.56 −1032.5 C41 197 −1411.80 −1032.5 C5 161 −3381.72 −1032.5 C42 198 −1359.96 −1032.5 C6 162 −3329.88 −1032.5 C43 199 −1308.12 −1032.5 C7 163 −3278.04 −1032.5 C44 200 −1256.28 −1032.5 C8 164 −3226.20 −1032.5 C45 201 −1204.44 −1032.5 C9 165 −3174.36 −1032.5 C46 202 −1152.60 −1032.5 C10 166 −3122.52 −1032.5 C47 203 −1100.76 −1032.5 C11 167 −3070.68 −1032.5 C48 204 −1048.92 −1032.5 C12 168 −3018.84 −1032.5 C49 205 −997.08 −1032.5 C13 169 −2967 −1032.5 C50 206 −945.24 −1032.5 C14 170 −2915.16 −1032.5 C51 207 −893.40 −1032.5 C15 171 −2863.32 −1032.5 C52 208 −841.56 −1032.5 C16 172 −2811.48 −1032.5 C53 209 −789.72 −1032.5 C17 173 −2759.64 −1032.5 C54 210 −737.88 −1032.5 C18 174 −2707.80 −1032.5 C55 211 −686.04 −1032.5 C19 175 −2655.96 −1032.5 C56 212 −634.20 −1032.5 C20 176 −2604.12 −1032.5 C57 213 −582.36 −1032.5 C21 177 −2552.28 −1032.5 C58 214 −530.52 −1032.5 C22 178 −2500.44 −1032.5 C59 215 −478.68 −1032.5 C23 179 −2448.60 −1032.5 C60 216 −426.84 −1032.5 C24 180 −2396.76 −1032.5 C61 217 −375 −1032.5 C25 181 −2344.92 −1032.5 C62 218 −323.16 −1032.5 C26 182 −2293.08 −1032.5 C63 219 −271.32 −1032.5 C27 183 −2241.24 −1032.5 C64 220 −115.80 −1032.5 2004 May 17 65 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 CO-ORDINATES SYMBOL CO-ORDINATES PAD SYMBOL x y PAD x y C65 221 −63.96 −1032.5 C102 258 +1957.80 −1032.5 C66 222 −12.12 −1032.5 C103 259 +2009.64 −1032.5 C67 223 +39.72 −1032.5 C104 260 +2061.48 −1032.5 C68 224 +91.56 −1032.5 C105 261 +2113.32 −1032.5 C69 225 +143.40 −1032.5 C106 262 +2165.16 −1032.5 C70 226 +195.24 −1032.5 C107 263 +2217.00 −1032.5 C71 227 +247.08 −1032.5 C108 264 +2268.84 −1032.5 C72 228 +298.92 −1032.5 C109 265 +2320.68 −1032.5 C73 229 +350.76 −1032.5 C110 266 +2372.52 −1032.5 C74 230 +402.60 −1032.5 C111 267 +2424.36 −1032.5 C75 231 +454.44 −1032.5 C112 268 +2476.20 −1032.5 C76 232 +506.28 −1032.5 C113 269 +2528.04 −1032.5 C77 233 +558.12 −1032.5 C114 270 +2579.88 −1032.5 C78 234 +609.96 −1032.5 C115 271 +2631.72 −1032.5 C79 235 +661.80 −1032.5 C116 272 +2683.56 −1032.5 C80 236 +713.64 −1032.5 C117 273 +2735.40 −1032.5 C81 237 +765.48 −1032.5 C118 274 +2787.24 −1032.5 C82 238 +817.32 −1032.5 C119 275 +2839.08 −1032.5 C83 239 +869.16 −1032.5 C120 276 +2890.92 −1032.5 C84 240 +921.00 −1032.5 C121 277 +2942.76 −1032.5 C85 241 +972.84 −1032.5 C122 278 +2994.60 −1032.5 C86 242 +1024.68 −1032.5 C123 279 +3046.44 −1032.5 C87 243 +1076.52 −1032.5 C124 280 +3098.28 −1032.5 C88 244 +1128.36 −1032.5 C125 281 +3150.12 −1032.5 C89 245 +1180.20 −1032.5 C126 282 +3201.96 −1032.5 C90 246 +1232.04 −1032.5 C127 283 +3253.80 −1032.5 C91 247 +1283.88 −1032.5 R0 284 +3461.16 −1032.5 C92 248 +1335.72 −1032.5 R1 285 +3513.00 −1032.5 C93 249 +1387.56 −1032.5 R2 286 +3564.84 −1032.5 C94 250 +1439.40 −1032.5 R3 287 +3616.68 −1032.5 C95 251 +1491.24 −1032.5 R4 288 +3668.52 −1032.5 C96 252 +1646.76 −1032.5 R5 289 +3720.36 −1032.5 C97 253 +1698.60 −1032.5 R6 290 +3772.20 −1032.5 C98 254 +1750.44 −1032.5 R7 291 +3824.04 −1032.5 C99 255 +1802.28 −1032.5 R8 292 +3875.88 −1032.5 C100 256 +1854.12 −1032.5 R9 293 +3927.72 −1032.5 C101 257 +1905.96 −1032.5 R10 294 +3979.56 −1032.5 2004 May 17 66 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 CO-ORDINATES SYMBOL CO-ORDINATES SYMBOL PAD x y PAD x y R11 295 +4031.40 −1032.5 R31 315 +5068.20 −1032.5 R12 296 +4083.24 −1032.5 R32 316 +5120.04 −1032.5 R13 297 +4135.08 −1032.5 R33 317 +5171.88 −1032.5 R14 298 +4186.92 −1032.5 R34 318 +5223.72 −1032.5 R15 299 +4238.76 −1032.5 R35 319 +5275.56 −1032.5 R16 300 +4290.60 −1032.5 R36 320 +5327.40 −1032.5 R17 301 +4342.44 −1032.5 R37 321 +5379.24 −1032.5 R18 302 +4394.28 −1032.5 R38 322 +5431.08 −1032.5 R19 303 +4446.12 −1032.5 R39 323 +5482.92 −1032.5 R20 304 +4497.96 −1032.5 dummy 324 +5638.44 −1032.5 R21 305 +4549.80 −1032.5 dummy 325 +5690.28 −1032.5 R22 306 +4601.64 −1032.5 dummy 326 +5742.12 −1032.5 R23 307 +4653.48 −1032.5 dummy 327 +5793.96 −1032.5 R24 308 +4705.32 −1032.5 dummy 328 +5845.80 −1032.5 R25 309 +4757.16 −1032.5 dummy 329 +5897.64 −1032.5 R26 310 +4809 −1032.5 dummy 330 +5949.48 −1032.5 R27 311 +4860.84 −1032.5 dummy 331 +6001.32 −1032.5 R28 312 +4912.68 −1032.5 dummy 332 +6053.16 −1032.5 R29 313 +4964.52 −1032.5 dummy 333 +6105.00 −1032.5 R30 314 +5016.36 −1032.5 2004 May 17 67 Philips Semiconductors Product specification VDD1 VDD2 VDD3 VSS1 PCF8811 VSS2 VOS0 VOS1 VOS2 VOS3 VOS4 T3 T4 T1 T2 T5 VLCDOUT VLCDSENSE VLCDIN 80 × 128 pixels matrix LCD driver VSS1* PS2 PS1 PS0 EXT OSC DS0 MF0 MF1 MF2 SDAHOUT SDAH SCLH/SCE VOTPPROG DB7/SDATA DB6/SCLK DB5/SDO DB4 DB3/SA1 DB2/SA0 DB1 DB0 VDD1* E/RD R/W / WR D/C RES PCF8811 y x 0,0 mgw769 * VSS1* and VDD1* for local tie offs. Fig.53 Bonding pad location (viewed from bump side). 2004 May 17 68 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 25 DEVICE PROTECTION DIAGRAM handbook, full pagewidth VDD1 VDD2 VDD3 VSS1 VSS1 VSS1 VSS2 VSS2 VLCDIN , VLCDSENSE VLCDOUT VSS1 VSS1 VLCDIN VDD1 VSS1 VOTPPROG VSS1 DB [7:0], SCLK, SDATA, SDO, SA1, SA0, R/W, WR LCD outputs VDD1 OSC, RES, RD, D/C, PS [2:0], T1, T2, T5, E VSS1 VSS1 VDD1 VDD1 I2C-bus pins T3, T4, VSS1*, VDD* VSS1 VSS1 VSS1 MGW770 For test purposes only: The maximum forward current is 5 mA. The maximum reverse voltage is 5 V. Fig.54 Device protection diagram. 2004 May 17 69 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 26 TRAY INFORMATION handbook, full pagewidth A x C y 1,1 2,1 1,2 2,2 x,1 3,1 D B 1,3 F x,y 1,y E MGU295 Fig.55 Tray details. Table 30 Tray dimensions DIM. handbook, halfpage PCF8811-1 Fig.56 Tray alignment. 2004 May 17 70 VALUE A pocket pitch; x direction B pocket pitch; y direction 4.45 mm C pocket width; x direction 12.55 mm D pocket width; y direction 2.41 mm E tray width; x direction 50.80 mm F tray width; y direction 50.80 mm x number of pockets in x direction 3 y number of pockets in y direction 10 MGW771 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientation and position of the type name on the die surface. DESCRIPTION 13.77 mm Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 27 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 28 DEFINITIONS 29 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 May 17 71 Philips Semiconductors Product specification 80 × 128 pixels matrix LCD driver PCF8811 Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 30 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2004 May 17 72 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R15/03/pp73 Date of release: 2004 May 17 Document order number: 9397 750 13144