SAMSUNG 16T202DA1J

SDI
16T202DA1J (Rev 1.0)
Page 2 / 18
1. SCOPE
This specification applies to VFD module (Model No: 16T202DA1J) manufactured by Samsung SDI.
2. FEATURES
2.1
LCD compatible interface and mounting holes.
(This VFD module is capable to communicate some different type of bus systems such as i80 (Intel) or
M68 (Motorola), 8-bit or 4-bit parallel data.)
2.2
High quality of display and luminance.
2.3
Compact and light-weight unit by using new VFD technology and flat packed one-chip controller.
2.4
+5V single power supply.
2.5
Luminance adjustment available by software (4 levels).
2.6
8 user definable fonts available (CG-RAM font).
2.7
ASCII and Jananese Katakana characters (CG-ROM font).
3. GENERAL DESCRIPTIONS
3.1 This specification becomes effective after being approved by the purchaser.
3.2 When any conflict is found in the specification, appropriate action shall be taken upon agreement of both
parties.
3.3 The expected necessary service parts should be arranged by the customer before the completion of
production.
4. PRODUCT SPECIFICATIONS
4.1 Type
Table_1
Type
16T202DA1J
Digit Format
5 x 7 Dot Matrix with Cursor
4.2 Outer Dimensions, Weight (See Fig_7 on Page 6/18 for details)
Table_2
Parameter
Outer
Dimensions
Specification
Unit
Width
85.0 +/-1.0
mm
Height
36.0 +/-1.0
mm
19.5 Max
mm
Typical 35
g
Thickness
Weight
SDI
16T202DA1J (Rev 1.0)
Page 3 / 18
4.3 Specifications of the Display Panel (See Fig_9 on Page 7/18 for details)
Parameter
Display Size
Symbol
Specification
Unit
WxH
51.76 x 11.09
mm
-
16 Digits x 2 Lines
-
WxH
2.26 x 4.343
mm
-
3.3(H) / 6.15(V)
mm
WxH
0.372 x 0.534
mm
-
Blue-Green (peak 505 nm)
-
Number of Digit
Character Size (excluding cursor)
Character Pitch
Dot Size
Table_3
Display Color
4.4 Environment Conditions
Table_4
Parameter
Operating Temperature
Symbol
Min.
Max.
Unit
Topr
-20
+70
o
C
o
C
Storage Temperature
Tstg
-40
+85
Humidity (Operating)
Hopr
0
85
%
Humidity (Non-operating)
Hstg
0
90
%
Vibration (10 ~ 55 Hz)
-
-
4
G
Shock
-
-
40
G
4.5 Absolute Maximum Ratings
Parameter
Table_5
Symbol
Min.
Max.
Unit
Supply Voltage
V CC
-0.5
6.0
V DC
Input Signal Voltage
V IS
-0.5
Vcc+0.5
V DC
4.6 Recommend Operating Conditions
Parameter
Table_6
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
V CC
4.5
5.0
5.5
V DC
Signal (Logic) Input Voltage
V IS
0
-
V CC
V DC
TOPR
-20
+25
+70
Operating Temperature
4.7 DC Characteristics (Ta=+25oC, Vcc=+5.0V)
Parameter
Supply Current
"H" level Input current
Luminance
Table_7
Symbol
Min.
Typ.
Max.
Unit
ICC
-
130
200
mA
"H" Level
V IH
0.7xVCC
-
-
V DC
"L" Level
V IL
-
-
0.3xVCC
V DC
IIH
20
-
500
uA
100
200
(340)
(680)
*)
Logic Input Voltage
C
O
V IN=V CC
£Ì
-
ft-L
(cd/m2)
*) Icc shows the current when all dots are turned on. The surge current can be approx. 3 times the
specified supply current at power on. However, the exact peak surge current amplitude and
duration are dependent on the characteristics of the host power supply.
SDI
16T202DA1J (Rev 1.0)
Page 4 / 18
4.8 Timing Chart and AC Characteristics
4.8.1 Power-on Reset and/or RESET signal Timing
tOFF(VCC )
Vcc
Min 100ms
0.2V
tr (VCC )
Max 1ms
4.5V
tWAIT *
Min 100us
/WR
tRESET
Min 500ns
/RST
* Note) tWAIT : Internal Reseting Time
Fig-1 Power-on Reset and /RESET signal Timing
4.8.2 i80 type CPU bus write-in Timing
RS
tSU(RS)
tCYC(/WR)
Min 10ns
Min 200ns
tH(RS)
Min 10ns
tWH (/WR)
Min 100ns
tWL (/WR)
/WR
Min 30ns
tSU(data)
tHW (data)
Min 30ns
Min 10ns
DB0~DB7
VALID
Fig-2 Data write-in Timing Diagram (i80 bus interface)
4.8.3 i80 type CPU bus read-out Timing
RS
tSU(RS)
tCYC(/RD)
Min 10ns
Min 200ns
tH(RS)
Min 10ns
tWH (/RD)
Min 100ns
tWL (/RD)
/RD
Min 70ns
tHR (data)
tACESS(data)
Min 5ns
Max 70ns
DB0~DB7
VALID
Fig-3 Data Read-out Timing Diagram (i80 bus interface)
SDI
16T202DA1J (Rev 1.0)
Page 5 / 18
4.8.4 M68 type CPU bus write-in Timing
R/W
tSU(RS,R/W)
tH(RS.R/W)
Min 20ns
Min 10ns
RS
tWL (E)
Min 230ns
tWH (E)
Min 230ns
E
tCYC(E)
Min 500ns
tSU(data)
tHWR (data)
Min 80ns
Min 10ns
DB0~DB7
VALID
Fig-4 Data write-in Timing Diagram (M68 bus interface)
4.8.5 M68 type CPU bus read-out Timing
R/W
tSU(RS,R/W)
tH(RS.R/W)
Min 20ns
Min 10ns
RS
tWL (E)
Min 230ns
tWH (E)
Min 230ns
E
tCYC(E)
Min 500ns
tDELAY (data)
tHRD (data)
Max 160ns
Min 5ns
DB0~DB7
VALID
Fig-5 Data read-out Timing Diagram (M68 bus interface)
4.9 Connector Pin Assignment
Fourteen of through holes are prepared for power supply
and signal interface. A connector may be able to soldered
to the holes. Location and dimensions are showen at Fig-8
on page 7/18.
*) The third hole (pin #3) can be used for reset input if the
soldering pad "JP1" is short-circuited.
(Refer to "Fig-6 System Block Diagram" on next page.)
No.
Signal
No.
Signal
1
GND
8
DB1
2
Vcc
9
DB2
3
* /RST
10
DB3
4
RS
11
DB4
5
R/W(/WR)
12
DB5
6
E(/RD)
13
DB6
7
DB0
14
DB7
SDI
16T202DA1J (Rev 1.0)
Page 6 / 18
4.10 System Block Diagram
Vcc
VDD
E
#6
R/W
#5
RS
#4
/RST
#3
72 Lines
ANODE
16 Lines
GRID
E
R/W
RS
Controller
JP1
Vcc
RESET
External reset
selection switch
(Soldering Pad)
VFD
16T202
JP0
MPU
VSS
MPU interface
selection switch
(Soldering Pad)
DB0~DB7
VDI SP
#7~#14
Vbb
(+5Vdc)
Vcc
#2
GND
#1
DC/DC
Converter
Ef 1
F1
Ef 2
F2
Fig-6 System Block Diagram of this VFD Module
4.11 Outer Dimensions
85.0 +/-1.0
80.0 +/-0.3
2.5 +/-0.5
4-O2.5 +/-0.3
(19.18)
36.0 +/-0.5 31.0 +/-0.3
3.0 Max
23.0 +0.7
-0.5
DISPLAY AREA (51.76*11.09)
(12.61 )
2.5 +/-0.5
7.5 +/-1.0
14.5 Max
(45.06)
6.5 +/-1.0
(39.94)
76.0
+0.8
-0.5
(1.5)
10.0 +/-1.0
19.5 Max
3.5 Max
8.5 Max
Mounting Component Area
30.0 Max
Fig-7 Outer Dimensions
(Unit:mm)
SDI
16T202DA1J (Rev 1.0)
Page 7 / 18
4.12 Connector Through Hole Location
14-O1.0
7.88
2.54
2.50
#14
#13
#2
#1
2.54
15.24
(p2.54x6)
7.88
(7.5)
(Unit:mm)
Fig-8 14-pin Through Hole Dimensions
4.13 Pattern Details
51.76
3.30
2.26
1.04
0.372
0.10
0.534
4.94
0.10
6.15
0.311
11.09
1.21
4.343
0.286
(Unit:mm)
Fig-9 Pattern Details
5. FUNCTION DESCRIPTIONS
5.1 Registers in VFD Controller
The VFD controller has two 8-bit registers, an instruction register (IR) and a data register (DR).
IR stores instruction codes, such as display clear and cursor shift, and address information for DD-RAM
and CG-RAM. The IR can only be written from the host MPU. DR temporarily stores data to be written
into DD-RAM or CG-RAM and temporarily stores data to be read from DD-RAM or CG-RAM. Data written
into the DR from the MPU is automatically written into DD-RAM or CG-RAM by an internal operation.
The DR is also used for data storage when reading data from DD-RAM or CG-RAM. When address
information is written into the IR, data is read and then stored into the DR from DD-RAM or CG-RAM by
internal operation. Data transfer between MPU is then completed when the MPU reads the DR. After the
read, data in DD-RAM or CG-RAM at the next address is sent to the DR for the next read from the MPU.
By the register selector (RS) signal, these two registers can be selected (See Table-8).
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16T202DA1J (Rev 1.0)
Page 8 / 18
Table-8 Register Selection
RS
M68
i80
Operation
R/W
/RD
/WR
0
0
1
0
IR write as an internal operation (display clear, etc.)
0
1
0
1
Read busy flag (DB7) and address counter (DB0 to DB6)
1
0
1
0
DR write as an internal operation (DR to DDRAM or CGRAM)
1
1
0
1
DR read as an internal operation (DDRAM or CGRAM to DR)
5.1.1 Busy Flag (BF)
When the busy flag is 1, the controller is in the internal operation mode, and the next instruction
will not be accepted. When RS = 0 and R/W = 1 (Table-8), the busy flag is output to DB7.
The next instruction must be written after ensuring that the busy flag is 0.
5.1.2 Address Counter (ACC)
The address counter (ACC) assigns addresses to both DD-RAM and CG-RAM. When an address
of an instruction is written into the IR, the address information is sent from the IR to the ACC.
Selection of either DD-RAM or CG-RAM is also determined concurrently by the instruction.
After writing into (reading from) DD-RAM or CG-RAM, the ACC is automatically incremented by 1
(decremented by 1). The ACC contents are then output to DB0 to DB6 when RS = 0 and
R/W = 1 (See Table-8).
5.1.3 Display Data RAM (DD-RAM)
Display data RAM (DD-RAM) stores display data represented in 8-bit character codes.
The area in DD-RAM that is not used for display can be used as general data RAM.
See Table_9 for the relationships between DD-RAM addresses and positions on the VFD.
Table_9 Relation between Digit Position and DD-RAM data
Left End
2nd Column 3rd Column
.............
15th Column Right End
1st Row
00 Hex
01 Hex
02 Hex
.............
0E Hex
0F Hex
2nd Row
40 Hex
41 Hex
42 Hex
..............
4E Hex
4F Hex
5.1.4 Character Generator ROM (CG-ROM)
The character generator ROM (CG-ROM) generates character patterns of 5x7 dots from 8-bit
character codes (Table-10). It can generate 240 kinds of 5x7 dot character patterns.
The character fonts are shown on the following page. The character codes 00H to 0FH are
allocated to the CG-RAM
5.1.5 Character Generator RAM (CG-RAM)
In the character generator RAM (CG-RAM), the user can
rewrite character patterns by program.
For 5x7 dots and cursor, eight character patterns can be
written. Write into DD-RAM the character codes at the
addresses shown as the left column of Table-10 to show
the character patterns stored in CG-RAM.
See Table-11 for the relationship between CG-RAM
addresses and data and display patterns and refer to
Fig-10 for dot assignment of VFD.
Areas that are not used for display can be used
as general data RAM.
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
16 17 18 19 20
21 22 23 24 25
26 27 28 29 30
31 32 33 34 35
36
Fig-10 Dot Assignment
SDI
16T202DA1J (Rev 1.0)
Page 9 / 18
Table-10 Characters Font Table (CG-ROM) and CG-RAM codes
U pper bit s DB7
DB6
DB5
Lower bit s
DB4
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
DB3 DB2 DB1 DB0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
CG-RAM
(1)
0
0
0
1
1
CG-RAM
(2)
0
0
1
0
2
CG-RAM
(3)
0
0
1
1
3
CG-RAM]
(4)
0
1
0
0
4
CG-RAM
(5)
0
1
0
1
5
CG-RAM
(6)
0
1
1
0
6
CG-RAM
(7)
0
1
1
1
7
CG-RAM
(8)
1
0
0
0
8
CG-RAM
(1)
1
0
0
1
9
CG-RAM
(2)
1
0
1
0
A
CG-RAM
(3)
1
0
1
1
B
CG-RAM]
(4)
1
1
0
0
C
CG-RAM
(5)
1
1
0
1
D
CG-RAM
(6)
1
1
1
0
E
CG-RAM
(7)
1
1
1
1
F
CG-RAM
(8)
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16T202DA1J (Rev 1.0)
Page 10 / 18
Table-11 Relationship between CG-RAM Addresses, Character Codes(DD-RAM) and 5x7 (with Cursor)
Dot Character Patterns (CG-RAM data)
Character Codes
Character Patterns
CG-RAM Address
(DD-RAM data)
(CG-RAM data)
D D D D D D D D
A A A A A A
D D D
D
D
D
D
D
7
5
0
0
0
0
6
0
0
0
0
5
0
0
0
0
4
0
0
0
3
2
x 0
x 0
x 0
0 ¡¿ 1
1
0
0
1
1
0
0
1
0
1
0
0
0
1
4
0
0
1
1
3
0
1
0
1
2
1
0
7
6
5
4
3
2
1
0
0
0
0
x
x
x
1
2
3
4
5
0
0
1
x
x
x
6
7
8
9
10
0
1
0
x
x
x 11 12 13 14 15
0
1
1
x
x
x 16 17 18 19 20
1
0
0
x
x
x 21 22 23 24 25
1
0
1
x
x
x 26 27 28 29 30
1
1
0
x
x
x 31 32 33 34 35
1
1
1
x
x
x 36
x
x
x
x
0
0
0
x
x
x
1
2
3
4
5
0
0
1
x
x
x
6
7
8
9
10
0
1
0
x
x
x 11 12 13 14 15
0
1
1
x
x
x 16 17 18 19 20
1
0
0
x
x
x 21 22 23 24 25
1
0
1
x
x
x 26 27 28 29 30
1
1
0
x
x
x 31 32 33 34 35
1
1
1
x
x
x 36
x
x
x
x
0
0
0
x
x
x
1
2
3
4
5
0
0
1
x
x
x
6
7
8
9
10
0
1
0
x
x
x 11 12 13 14 15
0
1
1
x
x
x 16 17 18 19
1
0
1
x
x
x 26 27 28 29 30
1
1
0
x
x
x 31 32 33 34 35
1
1
1
x
x
x 36
x
x
x
Character
Pattern(1)
Cursor
position
Character
Pattern(2)
Cursor
position
x
Notes: 1. Character code bits 0 to 2 correspond to CG-RAM address bits 3 to 5 (3 bits : 8 types).
2. CG-RAM address bits 0 to 2 designate the character pattern line position. The 8th line is the
cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line
data, corresponding to the cursor display position, at 0 as the cursor display.
If bit 4 of the 8th line data is 1, 1 bit will light up the cursor regardless of the cursor presence.
3. Character pattern row positions correspond to CG-RAM data bits 0 to 4 (bit 4 being at the left).
4. As shown Table-11, CG-RAM character patterns are selected when character code bits 4 to 7
are all 0. However, since character code bit 3 has no effect, the R display example above can
be selected by either character code 00H or 08H.
5. 1 for CG-RAM data corresponds to display selection and 0 to non-selection.
"x" Indicates no effect (Don't care)
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16T202DA1J (Rev 1.0)
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5.2 Interfacing to the MPU
This VFD module can interface in either two 4-bit operations or one 8-bit operation, thus allowing
interfacing with 4- or 8-bit MPUs.
* For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. When to use 4-bit
parallel data transfer, DB0 to DB3 keep "H" or "L". The data transfer between the VFD module and
the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer
the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits
(for 8-bit operation, DB0 to DB3).
The busy flag (BF) are performed before transferring the higher 4 bits. BF checks are not required
before transferring the lower 4 bits.
RS
R/W
E
DB7
IR7
IR3
D7
D3
BF
AC3
DR7 DR3
D7
D3
DB6
IR6
IR2
D6
D2
AC6
AC2
DR6 DR2
D6
D2
DB5
IR5
IR1
D5
D1
AC5
AC1
DR5 DR1
D5
D1
DB4
IR4
IR0
D4
D0
AC4
AC0
DR4 DR0
D4
D0
Busy Flag & Address
Counter Read
Data Register
Read
Instruction Register
Write
Character Code
Write
Character Code
Write
Fig-11 4-Bit Transfer Example (M68)
* For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
5.3 Reset Function
5.3.1 Power-on reset
An internal reset circuit automatically initializes the module when the power is turned on.
The following instructions are executed during the initialization.
1) Display clear
Fill the DD-RAM with 20H (Space Code)
2) Set the addres counter to 00H
Set the address counter (ACC) to point DD-RAM.
3) Display on/off control:
D = 0 ; Display off
C = 0 ; Cursor off
B = 0 ; Blinking off
4) Entry mode set:
I/D = 1 ; Increment by 1
S = 0 ; No shift
5) Function Set
IF = 1 ; 8-bit interface data
N = 1 ; 2-line display
BR0 = BR1 =0 ; Brightness = 100%
6) CPU interface type
when JP0 = Open ; M68 type (Factory Setting)
when JP0 = Short ; i80 type
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16T202DA1J (Rev 1.0)
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5.3.2 External reset
In order to use this function, a user must connect the soldering pad "JP1". When the soldering pad
"JP1" is open-circuited, this function is not valid and when it is short-circuited,. the third hole (pin #3) is
used for external reset input. If low level signal longer than 500ns is input into the hole, reset function
being same as power on reset is executed.
5.4 Soldering Land Function
Some soldering lands are prepared on the rear side of PCB, to set operating mode of the display
module. A soldering iron is required to short soldering lands.
Table-12 Soldering Land OPEN/SHORT Combination Table
JP0
JP1
F U N C T I O N
Open
x
M68 type
Short
x
i80 type
x
Open
Pin #3 : No connection
x
Short
Pin #3 : /RESET signal input (Low Active)
Open
Open
MPU type Selection
External Reset Section
Setting at Factory
x : Don't care
6. INSTRUCTIONS
6.1 Outline
Only the instruction register (IR) and the data register (DR) of the VFD controller can be controlled by
the user's MPU. Before starting the internal operation of the controller, control information is temporarily
stored into these registers to allow interfacing with various MPUs, which operate at different speeds, or
various peripheral control devices. The internal operation of the controller is determined by signals sent
from the MPU. These signals, which include register selection signal (RS), read/write signal (R/W), and
the data bus (DB0 to DB7), make up the controller instructions (See Table_13). There are four categories
of instructions that:
*
*
*
*
Designate controller functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Perform miscellaneous functions
Normally, instructions that perform data transfer with internal RAM are used the most.
However, auto-incrementation by 1 (or auto-decrementation by 1) of internal RAM addresses after each
data write can lighten the program load of the MPU. Since the display shift instruction can perform
concurrently with display data write, the user can minimize system development time with maximum
programming efficiency.
When an instruction is being executed for internal operation, no instruction other than the busy flag /
address read instruction can be executed. Because the busy flag is set to 1 while an instruction is
being executed, check it to make sure it is 0 before sending another instruction from the MPU.
Note : Be sure the controller is not in the busy state (BF = 0) before sending an instruction from the MPU
to the module. If an instruction is sent without checking the busy flag, the time between the first
instruction and next instruction will take much longer than the instruction time itself.
Refer to Table_13 for the list of each instruction execution time.
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16T202DA1J (Rev 1.0)
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Table-13 Instruction Set
Instruction
CODE
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Display Clear
0
Cursor Home
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Description
1
Clears all display and sets DDRAM address 0 in address counter.
x
Sets DDRAM address 0 in ACC.
Also returns the display being
shifted to the original position. DDRAM contents remain unchanged.
Entry Mode Set
0
0
0
0
0
0
0
1
I/D
S
Sets the cursor direction and
specifies display shift.
These operations are performed
during writing/reading data.
Display ON/OFF
Control
0
0
0
0
0
0
1
D
C
B
Sets all display ON/OFF(D), cursor
ON/OFF(C), cursor blink of
character position(B)
Cursor or
Display Shift
0
0
0
0
0
1
S/C
R/L
x
x
Shifts display or cursor, keeping
DD-RAM contents.
Function Set
0
0
0
0
1
IF
N
x
CGRAM Address
Setting
0
0
0
1
DDRAM Address
Setting
0
0
1
ADD
Sets the DD-RAM address.
Busy Flag &
Address Reading
0
1
BF
ACC
Read busy flag(BF) and address
counter (ACC).
Data Writing to
CG or DDRAM
1
0
Data writing
Writes data into CG-RAM or
DDRAM.
Data Reading from
CG or DDRAM
1
1
Data reading
Reads data from CG-RAM or
DDRAM.
ACG
I/D = 1 : Increment
I/D = 0 : Decrement
S
S
= 1 : Display shift enabled
= 0 : Cursor shift enabled
S/C = 1 : Display shift
S/C = 0 : Cursor move
R/L = 1 : Shift to the right
R/L = 0 : Shift to the left
* NOTE
IF
IF
N
N
BF
BF
[ Abbreviation ]
DD-RAM : Display Data RAM
CG-RAM : Character Generater
RAM
ACG : CG-RAM Address
ACC : Address Counter
= 1 : 2 Lines display
= 0 : 1 Line display
: 100%
: 75%
: 50%
: 25%
= 1 : Busy (Internally operating)
= 0 : Not busy (Instruction acceptable)
x : Don't Care
Sets the CG-RAM address.
ADD : DD-RAM Address
= 1 : 8bits
= 0 : 4bits
BR1, BR0 = 00
01
10
11
Sets data length(IF), number of
BR1 BR0 display lines(N), Set brightness level
(BR1,BR0)
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6.2 Instruction Descriptions
6.2.1 Display Clear
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
1
RS = 0,
01H
R/W = 0
This instruction
(1) Fills all locations in the display data RAM (DD-RAM) with 20H (Blank-character).
(2) Clears the contents of the address counter (ACC) to 00H.
(3) Sets the display for zero character shift (returns original position).
(4) Sets the address counter (ACC) to point to the DD-RAM.
(5) If the cursor is displayed, moves the cursor to the left most character in the top line (upper line).
(6) Sets the address counter (ACC) to increment on the each access of DD-RAM or CG-RAM.
6.2.2 Cursor Home
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
1
x
RS = 0,
R/W = 0
02H to 03H
x : Don't Care
This instruction
(1) Clears the contents of the address counter (ACC) to 00H.
(2) Sets the address counter (ACC) to point to the DD-RAM.
(3) Sets the display for zero character shift (returns original position).
(4) If the cursor is displayed, moves the left most character in the top line (upper line).
6.2.3 Entry Mode Set
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
1
I/D
S
RS = 0,
04H to 07H
R/W = 0
The I/D bit selects the way in which the contents of the address counter (ACC) are modified after
every access to DD-RAM or CG-RAM.
I/D = 1 : The address counter (ACC) is incremented.
I/D = 0 : The address counter (ACC) is decremented.
The S bit enables display shift, instead of cursor shift, after each write or read to the DD-RAM.
S = 1 : Display shift enabled.
S = 0 : Cursor shift enabled.
The direction
For example,
to DD-RAM.
cursor would
in which the display is shifted is opposite in sense to that of the cursor.
if S=0 and I/D=1, the cursor would shift one character to the right after a MPU writes
However if S=1 and I/D=1, the display would shift one character to the left and the
maintain its position on the panel.
The cursor will already be shifted in the direction selected by I/D during reads of the DD-RAM,
irrespective of the value of S. Similarly reading and writing the CG-RAM always shift the cursor.
Also both lines are shifted simultaneously.
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Table-14 Cursor move and Display shift by the "Entry Mode Set"
I/D
S
After writing DD-RAM data
After reading DD-RAM data
0
0
The cursor moves one character to the left.
The cursor moves one character to the left.
1
0
The cursor moves one character to the right.
The cursor moves one character to the right.
0
1
The display shifts one character to the right
without cursor's move.
The cursor moves one character to the left.
1
1
The display shifts one character to the left
without cursor's move.
The cursor moves one character to the right.
6.2.4 Display ON/OFF
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
D
C
B
RS = 0,
This instruction
D = 1 :
C = 1 :
B = 1 :
08H to 0FH
R/W = 0
controls various
Display on,
Cursor on,
Blinking on,
features
D = 0 :
C = 0 :
B = 0 :
of the display.
Display off.
Cursor off.
Blinking off
(Blinking is achieved by alternating between a normal and all on display of a character.
The cursor blinks with a frequency of about 1.0 Hz and DUTY 50%.)
6.2.5 Cursor/Display Shift
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
S/C
R/L
x
x
RS = 0,
10H to 1FH ( x : Don't care )
R/W = 0
This instruction shifts the display and/or moves the cursor, on character to the left or right,
without reading or writing DD-RAM.
The S/C bit selects movement of the cursor or movement of both the cursor and the display.
S/C = 1 : Shift both cursor and display
S/C = 0 : Shift cursor only
The R/L bit selects left ward or right ward movement of the display and/or cursor.
R/L = 1 : Shift one character right
R/L = 0 : Shift one character left
Table-15 Cursor/Display shift
S/C
R/L
Cursor shift
Display shift
0
0
Move one character to the left
No shift
0
1
Move one character to the right
No shift
1
0
Shift one character to the left with display
Shift one character to the left
1
1
Shift one character to the right with display
Shift one character to the right
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6.2.6 Function Set
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
IF
N
x
BR1
BR0
20H to 3FH
RS = 0, R/W = 0
x : Don't care
This instruction sets width of data bus line.(when to use parallel interface. IM=1), the number of display
line and brightness control.
This instruction initializes the system, and must be the first instruction executed after power-on.
The IF bit selects between an 8-bit or 4-bit bus width interface.
IF = 1 : 8-bit CPU interface using DB7 to DB0
IF = 0 : 4-bit CPU interface using DB7 to DB4
The N bit selects between 1-line or 2-line display.
N = 1 : Select 2 line display (Using anode output A1 to A80)
N = 0 : Select 1 line display (Using anode output A1 to A40. A41 to A80 fixed Low level.)
BR1, BR0 flag is control to brightness of VFD to modulate pulse width of Anode output as follows.
BR1
BR0
Brightness
~~~
~~~
~~~~~~~~
0
0
100 %
0
1
75 %
1
0
50 %
1
1
25 %
6.2.7 Set CG-RAM Address
DB7
DB6
0
1
DB5
DB4
DB3
DB2
DB1
DB0
ACG
40H to 7FH
RS = 0, R/W = 0
This instruction
(1) Load a new 6-bit address into the address counter (ACC).
(2) Sets the address counter (ACC) to address CG-RAM.
Once "Set CG-RAM Address" has been executed, the contents of the address counter (ACC) will be
automatically modified after every access of CG-RAM, as determined by the "Entry Mode Set" instruction.
The active width of the address counter (ACC), when it is addressing CG-RAM, is 6 bits, so the counter
will wrap around to 00H from 3FH if more than 64 bytes of data are written to CG-RAM.
6.2.8 Set DD-RAM Address
DB7
DB6
DB5
DB4
1
DB3
DB2
DB1
DB0
80H to A7H (1-Line)
C0H to E7H (2-Line)
ADD
RS = 0, R/W = 0
This instruction
(1) Loads a new 7-bit address into the address counter (ACC).
(2) Sets the address counter (ACC) to point to the DD-RAM.
Once the "Set DD-RAM Address" instruction has been executed, the contents of the address counter
(ACC) will be automatically modified after each access of DD-RAM, as selected by the "Entry Mode Set"
instruction.
Table-16 Valid DD-RAM address Ranges
Number of Character
Address Range
1st line
40
00H to 27H
2nd line
40
40H to 67H
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6.2.9 Read Busy Flag and Address
DB7
DB6
DB5
DB4
BF
DB3
DB2
DB1
DB0
ACC
RS = 0,
R/W = 1
Read busy flag and address reads the busy flag (BF) indicating that the system is now internally
operating on a previously received instruction. If BF is 1, the internal operation is in progress.
BF = 1 : busy state
BF = 0 : ready for next instruction, command receivable.
The next instruction will not be accepted until BF is reset to 0. Check the BF status before the next
write operation. At the same time, the value of the address counter (ACC) in binary AAAAAAA is
read out. This address counter (ACC) is used by both CG-RAM and DD-RAM addresses, and its value
is determined by the previous instruction. The address contents are the same as for instructions set
CG-RAM address and set DD-RAM address.
6.2.10 Write Data to CG or DD-RAM
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data Write
RS = 1,
00H to FFH
R/W = 0
This instruction writes 8-bit binary data (DB7 to DB0) into CG-RAM or DD-RAM.
To write into CG-RAM or DD-RAM is determined by the previous specification of the CG-RAM or
DD-RAM address setting. After a write, the address is automatically incremented or decremented by 1
according to the entry mode. The entry mode also determines the display shift.
When data is written to the CG-RAM, the DB7, DB6 and DB5 bits are not displayed as characters.
6.2.11 Read Data from CG or DD-RAM
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Data Read
RS = 1,
R/W = 1
This instruction reads 8-bit binary data (DB7 to DB0) from CG-RAM or DD-RAM.
The previous designation determines whether CG-RAM or DD-RAM is to be read.
Before entering this read instruction, either CG-RAM or DD-RAM address set instruction must be
executed. If not executed, the first read data will be invalid. When serially executing read instructions,
the next address data is normally read from the second read. The address set instructions need not
be executed just before this read instruction when shifting the cursor by the cursor shift instruction
(when reading out DD-RAM).
The operation of the cursor shift instruction is the same as the set DD-RAM address instruction.
After a read, the entry mode automatically increases or decreases the address by 1.
Note : The address counter (ACC) is automatically incremented or decremented by 1 after the write instructions
to CG-RAM or DD-RAM are executed. The RAM data selected by the ACC cannot be read out at this
time even if read instructions are executed. Therefore, to correctly read data, execute either the address
set instruction or cursor shift instruction (only with DD-RAM), then just before reading the desired data,
execute the read instruction from the second time the read instruction is sent.
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7.OPERATING RECOMMENDATIONS
7.1 Avoid applying excessive shock or vibration beyond the specification for the VFD module.
7.2 Since VFDs are made of glass material, careful handling is required.
i.e. Direct impact with hard material to the glass surface(especially exhaust tip) may crack
the glass.
7.3 When mounting the VFD module to your system, leave a slight gap between the VFD glass
and your front panel.
The module should be mounted without stress to avoid flexing of the PCB.
7.4 Avoid plugging or unplugging the interface connection with the power on, otherwise it may
cause the severe damage to input circuitry.
7.5 Slow starting power supply may cause non-operation because one chip micom won't be reset.
7.6 Exceeding any of maximum ratings may cause the permanent damage.
7.7 Since the VFD modules contain high voltage source, careful handling is required during
powered on.
7.8 When the power is turned off, the capacitor does not discharge immediately.
The high voltage applied to the VFD must not contact to the ICs. And the short-circuit of
mounted components on PCB within 30 seconds after power-off may cause damage to those.
7.9 The power supply must be capable of providing at least 3 times the rated current, because
the surge current can be more than 3 times the specified current consumption when the
power is turned on.
7.10 Avoid using the module where excessive noise interference is expected. Noise may affects
the interface signal and causes improper operation. And it is important to keep the length of
the interface cable less than 50cm.
7.11 Since all VFD modules contain C-MOS ICs, anti-static handling procedures are always required.