Committed to flexible digital TV and PC/TV solutions, Philips Semiconductors has developed a complete DTV receiver reference design based on proven ICs from other reference designs. It is laid out according to Device Bay physical specifications and allows a DTV transport stream to be carried over Device Bay or IEEE 1394 connections. IEEE 1394/Device Bay ATSC DTV receiver Reference design Highly integrated DTV front-end, with IEEE 1394/Device Bay transport stream output In the fast moving digital broadcast market, where TV and PC technologies are converging, the high performance IEEE 1394 bus is now the established high-speed, real-time true plug-and-play serial bus system. As its popularity grows, it is becoming the accepted standard for connecting a variety of digital consumer electronics equipment to each other, as well as to multimedia PCs and workstations. Drawing on Philips Semiconductors’ acknowledged expertise in digital TV systems and IEEE 1394 interface devices, this reference design combines these technologies in the emerging Device Bay format, creating a simple high performance DTV receiver for PC and other IEEE 1394-based applications. Based around a proven 8-VSB (Vestigial SideBand) demodulator with on-chip digital tuner AGC control, used in the established ‘Coney’ PCI-based ATSC/NTSC PC-TV board, this reference design also Applications • Digital ATSC-compliant terrestrial reception • Personal computers with digital television capabilities • Modular digital home entertainment systems incorporates Philips’ advanced IEEE 1394 devices: a high-performance Link layer controller with isochronous operation and embedded IEC61883 support; and a three-port Physical layer interface. These high-speed devices enable the digital TV signal (MPEG2 transport stream) to be transferred over the IEEE 1394 bus at 200 Mbits/s, output via either 1394 port or Device Bay connections. Highly featured board • • • developing the user interfaces and applications that will differentiate or Device Bay connections them in a market where competition is very fierce. A licence is available, Reference design laid out according to royalty-free, from Philips Semiconductors to use the PCB layout Device Bay physical specifications (Gerber) files as well as the original design schematics. Single-chip TDA8960 ATSC-compliant 8-VSB demodulator and decoder front-end • IF ADC 8-VSB DEMODULATOR DATA FORMATTING & CONTROL 1394 LINK LAYER CONTROLLER 1394 PHYSICAL LAYER 1394 PORT I2C I2C µC 80C51 PDI1394L11 IEEE 1394-1995 A/V Link layer controller with hardware support for IEC61883 • TUNER PDI1394P11 IEEE 1394-1995 Physical layer controller supports data transfer at up to 200 Mbits/s • This reference design enables platform providers to concentrate on Outputs a DTV transport stream over IEEE 1394 EEPROM 64k8 SRAM 64k8 1394 PHYSICAL LAYER 1394 POWER TDA9829 IF downconversion for VSB POWER ENABLE LOGIC DEVICE BAY CONNECTORS MSD052 COMPLETE REFERENCE DESIGN FOR A IEEE 1394/DEVICE BAY ATSC DTV RECEIVER MODULE This reference design demonstrates a complete solution for capture, demodulation and decoding of ATSCcompliant DTV signals, and outputting DTV transport streams over the high speed IEEE 1394 bus using either IEEE 1394 or Device Bay connections. It uses just three core ICs: the TDA8960 VSB demodulator/decoder and two IEEE 1394 ICs - a physical layer controller and A/V link layer controller. SINGLE-CHIP ATSC DEMODULATOR/DECODER One of the key chips in the Device Bay module, the TDA8960 • TDA8960 ATSC-compliant 8-VSB accepts 8-VSB modulated signals from the IF block of the tuner demodulator and concatenated Trellis front-end, or alternatively, the VSB IC AGC control output can (Viterbi)/Reed-Solomon decoder with be applied directly to the tuner. Adaptive equalization using de-interleaver and de-randomizer the ATSC field sync (trained equalization) and/or the 8-VSB data • 8-bit MPEG2 transport stream output itself (blind equalization) is performed via a decision feedback • On-chip digital tuner AGC control equalizer (DFE) following internal carrier recovery, half Nyquist • Integrated digital Square-Root filtering and symbol timing recovery. Raised-Cosine (half Nyquist) filter with • • 11.5 % roll-off Following trellis decoding, the stream is de-interleaved with a Feed forward adaptive equalizer convolutional de-interleaver with on-chip memory. The ATSC- including a Decision Feedback Equalizer compliant Reed-Solomon decoder has a length of 207 and can (DFE) correct up to 10 bytes. After decoding, the stream is de-randomized Reed-Solomon decoder with internal and passed to a FIFO, preventing irregular gaps in the data; this then convolutional de-interleaving outputs an 8-bit MPEG2 transport stream for de-multiplexing. • De-randomizer based on ATSC standard • Rate 2/3 (rate 1/2 Ungerboeck-codebased) Trellis (Viterbi) decoder PROVEN HIGH PERFORMANCE IEEE 1394 SILICON Philips Semiconductors’ controllers deliver a high-performance, low-cost, proven IEEE 1394 system solution. Our Physical layer controllers are fully interoperable with all 1394 link layer controllers including PCI/OCHI compatible devices, while our Link layer controllers offer support for MPEG2 and DV data streams, and IEC61883. Our latest full duplex A/V link layer controller (PDI1394L21) also supports processor based time stamp handling. All Philips IEEE 1394 silicon offers bus holder circuits on the Link/PHY interface, allowing effective node isolation - required in almost all 1394-enabled equipment. A single capacitor in series with each Link/PHY interface line provides economical yet highly effective isolation. PDI1394L11 1394 A/V Link layer controller • Full IEEE 1394-1995 compliant The board supports standard 6 MHz VHF/ • Hardware support for IEC 61883 standard UHF digital terrestrial TV channels in the • A/V interface port supports high-speed (isochronous) 38.9 MHz to 45.75 MHz frequency range. • digital data streams IF gain is controlled using three AC-coupled, Asynchronous interface port supports command and differential amplifier stages, with a feedback stage controlled by emitter-degeneration. control functions • Compatible with any IEEE 1394-1995 100, 200 and 400 Mbits/s physical layer devices 87C654 microcontroller Together with an FPGA, the microcontroller Philips’ PDI1394L11, is an IEEE 1394-1995 link layer controller performs basic data, address and control signal featuring an embedded A/V layer interface. The A/V layer is handling, as well power-up and reset functions. designed to pack and un-pack application data packets for A derivative of the 80C51 microcontroller transmission over an IEEE 1394 bus using isochronous data transfers. family, with the same instruction set, it has a non-volatile 16 k x 8 EPROM and a volatile Application data is packetized according to IEC61883 specification 256 x 8 read/write data memory, four 8-bit of digital interface for consumer electronic audio/video equipment. I/O ports, two 16-bit timer/event counters, The A/V layer interface is a byte wide port capable of nested multiple interrupts, an I2C-bus interface accommodating various MPEG2 and DV codecs. A byte wide host and on-board UART. interface is provided for internal register configuration as well as performing asynchronous data transfers. The IEC61883 standard Today, transmission of digital video and audio PDI1394P11 three-port Physical Layer Controller data is commonplace, demanding standards to • IEEE 1394-1995 compliant ensure compatibility of equipment and • Three cable ports capable of 100 Mbits/s and 200 Mbits/s interfaces. IEC61883 specifies a digital data rates interface for consumer electronic audio/video Energy saving power down feature offers lower power equipment. As a major contributor to the consumption than competing devices IEC61883 protocol Philips has in-depth Interfaces to any IEEE 1394 standard link layer controller expertise in the implementation of IEC61883 • • over IEEE 1394. Integrated on the main board for output over 1394 port connections, or on a Device Bay daughter card for output over a Device Bay signal The IEC61883 standard describes the general connector, the PDI1394P11 provides the analog physical layer packet format, data flow and connection functions to connect to a three-port node in a 1394 application. management for audio/visual data. General It manages bus initialization and arbitration cycles, as well as transmission rules for control commands are transmission and reception of data bits. Supporting the IEEE 1394a also specified, as are the transmission protocol short arbitrated bus reset, the PDI1394P11 reduces reset times and hence the risk of losing isochronous data. and control commands for digital audio and video equipment connecting via the IEEE 1394 interface. Data packetization and TDA9829 IF downconverter transmission timing for MPEG2 transport The TDA9829 DTV IF amplifier/converter chip provides the signal streams transmitted over the IEEE 1394 stages for IF processing to the DVB standard, down-converting the interface and specifications for the IEEE 1394 digital Quadrature Amplitude Modulation (QAM) signal to a packet itself are also covered by IEC61883. frequency matching the symbol rate. It features VCO for QAM carrier recovery, internal and external AGC for DVB, and is applicable for VSB (HDTV) IF and OFDM downconversion. IEEE 1394/Device Bay ATSC DTV receiver Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. 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Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1999 SCB62 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands Date of release: March 1999 Document order number: 9397 750 05382