PHILIPS TDA8960

INTEGRATED CIRCUITS
DATA SHEET
TDA8960
ATSC 8-VSB demodulator and
decoder
Preliminary specification
File under Integrated Circuits, IC02
1999 Jun 14
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
FEATURES
General features
• One-chip Advanced Television Systems Committee
(ATSC)-compliant demodulator and concatenated trellis
(Viterbi)/Reed Solomon decoder with de-interleaver and
de-randomizer
I2C-bus interface
• 0.4 µm process
• I2C-bus interface to initialize and monitor the
demodulator and Forward Error Correction (FEC)
decoder. Operation without I2C-bus control is possible
(default).
• 3.3 V device
• 64-lead QFP64 package
• Boundary scan test
• Output format: 8-bit wide bus.
DOCUMENT REFERENCES
8-VSB demodulator
See the ATSC URL on ‘http://www.atsc.com’ for the
following related documents:
• On-chip digital circuitry for tuner Automatic Gain Control
(AGC)
• “ATSC Digital Television Standard” (document no. A/53,
issued 1995 Sep 16)
• Square root raised cosine filter with 11.5% roll-off factor
• Fully internal carrier recovery loop
• “Guide to the use of the ATSC Digital Television
Standard” (document no. A/54, issued 1995 Oct 04).
• Mostly internal clock recovery and AGC loops with
programmable loop filters
• External indication of demodulator lock.
APPLICATIONS
Adaptive equalizer
• Digital ATSC compliant TV receivers
• Feed forward including a Decision Feedback Equalizer
(DFE) structure
• Set-top boxes.
• Personal computers with digital television capabilities
• Range of −2.3 to +10.5 µs
• Adaptation based on ATSC field sync (trained) and/or
8-VSB data (blind)
• Trellis (Viterbi) decoder
• Rate 2⁄3 (Rate 1⁄2 Ungerboeck code based).
Reed Solomon decoder
• (207, 187 and T = 10) Reed Solomon code
• Internal convolutional de-interleaving (I = 52; using
internal memory)
• External indication of uncorrectable error; transport error
indicator bit in Motion Picture Export Group (MPEG)
packet header is also set
• Followed by de-randomizer based on ATSC standard.
ORDERING INFORMATION
TYPE
NUMBER
TDA8960
1999 Jun 14
PACKAGE
NAME
QFP64
DESCRIPTION
VERSION
plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm SOT319-2
2
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
The carrier recovery is performed completely internally.
This function consists of a digital frequency and Frequency
Phase-Locked Loop (FPLL).
GENERAL DESCRIPTION
The TDA8960 is an ATSC-compliant demodulator and
forward error correction decoder for reception of 8-VSB
modulated signals for terrestrial and cable applications:
Data shaping is performed with a square root raised cosine
(half Nyquist) filter with roll-off factor of 11.5%.
• Terrestrial: reception of 8-VSB modulated signals via
standard 6 MHz VHF/UHF terrestrial TV channels
(TV channels 2 to 69 in the United States)
Symbol timing recovery is performed mostly within the
TDA8960, except that a low cost D/A converter and VCXO
are required externally to generate the nominal 21.52 MHz
clock signal for the A/D converter and TDA8960.
• Cable: reception of 8-VSB modulated signals via
standard 6 MHz VHF/UHF cable TV channels.
After carrier recovery, half Nyquist filtering and symbol
timing recovery, adaptive equalization is performed based
on the use of the ATSC field sync (trained equalization)
and/or the 8-VSB data itself (blind equalization).
The adaptive equalizer uses a DFE structure.
Most of the loop components needed to recover the data
from the received symbols are internal. The only required
external loop components are a low-speed serial D/A
converter and a Voltage Controlled crystal Oscillator
(VCXO) for the symbol timing recovery and an opamp
integrator for the AGC. Loop parameters of the clock and
carrier recovery can be controlled by the I2C-bus.
After trellis decoding, the stream is de-interleaved with a
convolutional de-interleaver (interleaving depth 52).
The memory for de-interleaving is on-chip. The Reed
Solomon decoder is ATSC-compliant with a length of 207
and can correct up to 10 bytes. The decoded stream is
de-randomized using a Pseudo Random Bit Sequence
(PRBS). Finally the data is passed to a First-In, First-Out
(FIFO) register that prevents the appearance of irregular
gaps in the output data.
A tuner converts the incoming RF frequency to a fixed IF
frequency centred at 44 MHz. The output of the tuner is
filtered, followed by a down conversion in an IF block to a
low IF frequency centred at 1⁄2 the VSB symbol rate (or a
frequency of approximately 5.38 MHz). The low IF signal is
applied to the A/D converter.
To use its full input span, the A/D converter is located
within what is typically a fine AGC loop which includes a
variable gain stage at the output of the IF block. However,
it is also possible to apply the TDA8960 AGC control
output directly to the tuner. The detector for the TDA8960
AGC output is located after the A/D converter and
determines the peak level of the incoming signals. After
gain control, the low IF signal is sampled at a nominal rate
of twice the VSB symbol frequency, or approximately
21.5 MHz.
1999 Jun 14
TDA8960
The output of the TDA8960 is an ATSC-compliant MPEG-2
packet stream together with a clock. Furthermore some
signal flags are provided to indicate the sync bytes and the
valid data bytes. Uncorrected blocks are also indicated.
The 8-bit wide MPEG-2 stream can be applied to an
MPEG-2 transport demultiplexer.
3
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDDD
digital supply voltage
IDDD(tot)
total digital supply current
fclk
CONDITIONS
MIN.
TYP.
MAX.
UNIT
3.0
3.3
3.6
V
−
300
−
mA
clock frequency
−
21.52
−
MHz
fsym
symbol frequency
−
10.76
−
Msymbols/s
IL
implementation loss
−
−
−
dB
αro
half Nyquist filter roll-off factor
−
11.5
−
%
tacq
acquisition time
−
−
290
ms
Tamb
ambient temperature
−20
−
+70
°C
Ptot
total power dissipation
−
1.0
−
W
VDDD = 3.3 V
note 1
Note
1. This corresponds to 12 training sequences.
1999 Jun 14
4
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
BLOCK DIAGRAM
handbook, full pagewidth
EQLOCKINDIC
AGCOUT
LOCKINDIC
53
54
ADIN0 to ADIN9
56
1 to 8, 11, 12
27
RESET
RSTAN
LOCK
DETECTORS
61
DIGITAL FRONT-END(1)
SERIAL
DAC
INTERFACE
TRELLIS DECODER
62
63
64
17
21
SYNCHRONIZATION
BOUNDARY
SCAN TEST
REED SOLOMON DECODER
20
18
19
13
DE-RANDOMIZER
16
I2C-BUS
INTERFACE
CLK
DATACLK
31 to 33
35 to 37
39, 40
22
24
TRCS
TRLD
25
23, 34,
45, 57,
9, 26,
41, 60
TDI
TDO
TRST
TMS
TCK
A0
A1
SCL
SDA
30, 38,
49,55,
10, 28,
42, 58
VSSD1 to VSSD8
VDDD1 to VDDD8
ERROR SOP DATAVALID
DATA7 to DATA0
(1) The digital front-end consists of the following circuits:
- Fine AGC
- Carrier recovery
- Half Nyquist filter
- Symbol timing recovery
- Sync recovery and pilot removal
- Adaptive equalization.
Fig.1 Block diagram.
1999 Jun 14
14
15
FIFO
29
TRSTB
TDA8960
DE-INTERLEAVER
59
TRSDO
5
MGR598
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
ADIN0
1
I
data input bit 0 from ADC
ADIN1
2
I
data input bit 1 from ADC
ADIN2
3
I
data input bit 2 from ADC
ADIN3
4
I
data input bit 3 from ADC
ADIN4
5
I
data input bit 4 from ADC
ADIN5
6
I
data input bit 5 from ADC
ADIN6
7
I
data input bit 6 from ADC
ADIN7
8
I
data input bit 7 from ADC
VDDD5
9
−
digital supply voltage 5 (3.3 V)
VSSD5
10
−
digital core ground 5
ADIN8
11
I
data input bit 8 from ADC
ADIN9
12
I
data input bit 9 from ADC
A0
13
I
I2C-bus slave address bit 0
SCL
14
I
I2C-bus clock
SDA
15
I/O
A1
16
I
I2C-bus slave address bit 1
TDI
17
I
TAP controller data input; note 1
TMS
18
I
TAP controller test mode select; note 1
TCK
19
I
TAP controller test clock; note 1
TRST
20
I
TAP controller asynchronous reset; note 1
TDO
21
O
TAP controller test data output (3-state); note 1
ERROR
22
O
transport packet block error signal
VDDD1
23
−
digital supply voltage 1 (3.3 V)
SOP
24
O
start of transport packet signal
DATAVALID
25
O
transport packet data valid signal
VDDD6
26
−
digital supply voltage 6 (3.3 V)
I2C-bus serial data
RSTAN
27
I
asynchronous reset
VSSD6
28
−
digital ground 6
DATACLK
29
O
transport interface data clock
VSSD1
30
−
digital ground 1
DATA7
31
O
transport packet data output bit 7
DATA6
32
O
transport packet data output bit 6
DATA5
33
O
transport packet data output bit 5
VDDD2
34
−
digital supply voltage 2 (3.3 V)
DATA4
35
O
transport packet data output bit 4
DATA3
36
O
transport packet data output bit 3
DATA2
37
O
transport packet data output bit 2
VSSD2
38
−
digital ground 2
DATA1
39
O
transport packet data output bit 1
DATA0
40
O
transport packet data output bit 0
1999 Jun 14
6
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
SYMBOL
TDA8960
PIN
I/O
VDDD7
41
−
digital supply voltage 7 (3.3 V)
VSSD7
42
−
digital ground 7
n.c.
43
not connected
n.c.
44
not connected
VDDD3
45
n.c.
46
not connected
n.c.
47
not connected
n.c.
48
not connected
VSSD3
49
n.c.
50
not connected
n.c.
51
not connected
n.c.
52
LOCKINDIC
53
O
lock indicator of front-end
EQLOCKINDIC
54
O
lock indicator of equalizer
VSSD4
55
−
digital ground 4
AGCOUT
56
O
AGC control signal (3-state)
VDDD4
57
−
digital supply voltage 4 (3.3 V)
VSSD8
58
−
digital ground 8
CLK
59
I
clock
VDDD8
60
−
digital supply voltage 8 (3.3 V)
TRSDO
61
O
serial data to DAC
TRSTB
62
O
strobe signal to DAC
TRCS
63
O
chip select signal to DAC
TRLD
64
O
load signal to DAC
−
−
DESCRIPTION
digital supply voltage 3 (3.3 V)
digital ground 3
not connected
Note
1. In accordance with the “IEEE 1149.1” standard; pads TCK, TDI, TMS and TRST are input pads with an internal
pull-up transistor and pad TDO is a 3-state output pad.
1999 Jun 14
7
Philips Semiconductors
Preliminary specification
52 n.c.
ADIN0
1
51 n.c.
ADIN1
2
50 n.c.
ADIN2
3
49 VSSD3
ADIN3
4
48 n.c.
ADIN4
5
47 n.c.
ADIN5
6
46 n.c.
ADIN6
7
45 VDDD3
ADIN7
8
44 n.c.
VDDD5
9
43 n.c.
TDA8960
VSSD5 10
42 VSSD7
35 DATA4
TMS 18
34 VDDD2
TCK 19
33 DATA5
8
DATA6 32
TDI 17
DATA7 31
36 DATA3
VSSD1 30
A1 16
DATACLK 29
37 DATA2
VSSD6 28
SDA 15
RSTAN 27
38 VSSD2
VDDD6 26
SCL 14
DATAVALID 25
39 DATA1
SOP 24
A0 13
VDDD1 23
40 DATA0
ERROR 22
ADIN9 12
TDO 21
41 VDDD7
TRST 20
ADIN8 11
Fig.2 Pin configuration.
1999 Jun 14
55 VSSD4
56 AGCOUT
57 VDDD4
58 VSSD8
59 CLK
60 VDDD8
61 TRSDO
62 TRSTB
63 TRCS
64 TRLD
handbook, full pagewidth
53 LOCKINDIC
TDA8960
54 EQLOCKINDIC
ATSC 8-VSB demodulator and decoder
MGR599
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
By default the carrier is present at 2.69 MHz. During carrier
recovery a shift is applied such that the pilot is present at
DC. It can happen that the pilot is present at the higher
edge of the VSB spectrum. In this event the CR_INV bit in
I2C-bus register 08H (see Table 13) can be set to make
sure that after the shift the pilot is at DC.
FUNCTIONAL DESCRIPTION
The internal architecture of the TDA8960 consists of
basically two parts:
• The front-end containing the AGC, carrier recovery, half
Nyquist filter, symbol timing recovery, sync recovery and
adaptive equalization
• The back-end containing the trellis decoder,
de-interleaver, the Reed Solomon decoder and
de-randomizer.
MGR600
handbook, halfpage
5.38 MHz
amplitude
(dB)
AGC
This block controls an analog gain over a range of up to
±20 dB.
The data from the A/D converter (Philips Semiconductors’
TDA8763 is recommended) arrives at the VSB
demodulator via inputs ADIN9 to ADIN0, which is10-bit
wide. The format of the incoming samples can be
programmed using the I2C-bus accessible register 08H.
By writing to bit 3 the format can be either twos
complement or binary.
2.69
The carrier recovery is capable of tracking a frequency
offset of up to 100 kHz from the nominal frequency offset
within 100 ms.
By means of I2C-bus read register 03H the current
frequency offset in the carrier recovery can be read.
This value can be used for fine tuning applications.
Sync recovery and pilot removal
AGC output
PIN AGCOUT
This block performs several functions including pilot
removal, segment and field sync removal and rescale
AGC based on the segment sync. If this block is able to
find a data segment sync signal, the external pin
LOCKINDIC is asserted. The value of this signal can also
be read through I2C-bus control.
COMMENT
1
output of the filter is smaller than the
threshold
0
output of the filter is larger than the
threshold
Z
output of the filter is equal to the
threshold
Adaptive equalization
The equalizer consists of a forward filter and a feedback
filter section. Demodulated symbols from the
synchronization and pilot removal block are received every
symbol period. The equalizer tries to invert the effects of
the channel on the transmitted symbol stream by filtering
these symbols. The coefficients of the filters are updated
every symbol period using the training sequence. There is
also a provision to perform blind equalization. The filtered
output is available for the next block, the trellis decoder.
The analog low-pass filter or integrator circuit should be
designed with an 8 ms time constant. The response of the
gain amplifier is linear with respect to the control voltage
over the desired range of operation.
Carrier recovery
This circuit recovers the frequency and phase of the pilot
carrier. The spectrum during the carrier recovery is
displayed in Fig.3.
1999 Jun 14
8.07
frequency (MHz)
Fig.3 Signal spectrum during carrier recovery.
The absolute value of the input signal is averaged over
several samples. The filtered signal is compared to a
threshold. The threshold consist of a 4-bit signed value
which can be programmed using the I2C-bus. The 3-state
output signal charges or discharges an off-chip ideal
integrator and is used to control the gain controller of the
tuner front-end module. The values of the signal are shown
in Table 1.
Table 1
5.38
9
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
The equalizer has been designed to correct a maximum
pre-echo of 2.32 µs and a maximum post-echo of
10.50 µs. The equalizer uses an overlapping DFE to
reduce the effects of co-channel interference.
The equalizer has been optimized to have a typical
acquisition time of 12 training sequences, which
corresponds to approximately 290 ms. The acquisition
time has been defined as the time when the output
signal-to-noise ratio reaches the Threshold Of Visibility
(TOV). The ATSC defines a TOV of 14.9 dB for 8-VSB.
STATE 0: CHANNEL ACQUISITION
In this state either no channel signal is present or a
channel signal is being acquired. The AGC, timing
recovery and carrier recovery loops must first lock onto it.
If the segment sync lock is lost, pin LOCKINDIC is LOW,
or a hardware reset is applied to the VSB demodulator, the
finite state machine returns to state 0.
STATE 1: EQUALIZER TRAINING
The finite state machine remains in state 1 until the MSE
of the equalized training sequence falls below a certain
threshold. It should be noted that in state 1 the back-end is
continuously reset to make sure that after the demodulator
has locked onto a signal, the trellis decoder and following
processing blocks begin at the start of the next complete
data field. By means of I2C-bus registers 01H and 02H the
MSE value of the equalizer can be read. This value can be
used for applications such as antenna pointing.
Based on the training signal and the output of the equalizer
the Mean Square Error (MSE) signal is generated. This
16-bit value is used to control the channel adaptation
process and is available though I2C-bus control.
Control
The TDA8960 contains a complicated finite state machine.
This state machine controls the sequence of operations
that must be performed when a valid VSB data signal is
detected in order for it to be properly decoded into a
stream of MPEG-2 transport packets. The following steps
have to take place:
STATE 2: NORMAL OPERATION
Normally the state machine would remain in state 2 as
long as no synchronization error occurs. If the MSE of the
equalized training sequence is exceeded for more than
100 ms, the equalizer is reset for one symbol period and
the adaptation process starts again. If the demodulator is
in this state, the EQLOCKINDIC pin signal goes up.
The value of this signal can also be read through the
I2C-bus.
1. The external tuner is directed to lock to a specified
channel frequency. A VSB signal is present.
2. The tuner AGC locks to an acceptable signal gain.
3. The coarse AGC of the TDA8960 locks to acceptable
A/D converter gain.
4. The timing and carrier recovery loops lock to the
symbol clock and the carrier frequency.
5. The segment sync pattern is detected. The segment
sync lock is acquired.
6. The fine AGC locks.
7. The field sync pattern is detected. The MSE of the
received field sync training sequence is determined.
8. The equalizer uses subsequent training sequences to
adapt itself to the channel conditions.
9. The equalizer adapts to the point that the MSE of the
training sequence is sufficiently small. The trellis
decoding, convolutional de-interleaving and Reed
Solomon decoding processes all begin.
10. Valid MPEG-2 transport packets are generated.
The finite state machine consists of three states. After a
reset has been applied, the state machine starts in state 0.
1999 Jun 14
TDA8960
10
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
DAC interface
The TDA8960 D/A interface connects to an external off-chip serial D/A converter. It supports four different serial modes.
EXTERNAL INTERFACE
The DAC interface consists of pins 61 to 64; see Table 2.
Table 2
DAC interface
PIN
FUNCTION
TRSDO
serial data output
TRSTB
strobe signal which can be used by the DAC to shift in serial data
TRCS
chip select signal for DAC is also used by some DACs to load serially shifted data in the internal
parallel register on the positive edge
TRLD
load signal used by some DACs to load serially shifted data in the internal parallel latches
OUTPUT MODES
Table 3 shows which DACs can be used in the different output modes.
Table 3
DAC serial interface modes and DAC types
OUTPUT MODE
POLARITY
SET-UP TIME (ns)
0
+dF/dV
67
EXAMPLE DEVICE
Maxim
MAX531, MAX538, MAX539, MAX504 and MAX515
Texas Instruments TLC5615
Sipex SP9500 and SP960
Linear Technology TLC1451
1
+dF/dV
45
Analog Devices AD7943
2
+dF/dV
45
Analog Devices DAC8512
3
−dF/dV
67
same types as mode 0
The operating mode is programmed by means of the I2C-bus interface. Bits 4 and 5 of registers 09H control the mode;
see Table 13.
The timing diagrams of the different serial modes are shown in Fig.4. Modes 0 and 3 do not use the load signal available
at pin TRLD. In mode 3 the output of the timing recovery low-pass filter is inverted to control VCXOs which have a
negative dF/dV. Modes 0 and 3 can provide up to 67 ns of the serial data set-up time from the moment the TRSDO output
has a new data bit until the start of the TRSTB pulse.
In mode 1 the TRCS pin is not used.
1999 Jun 14
11
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
handbook, full TRCS
pagewidth
TRSTB
TRSDO
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MGR601
a. Modes 0 and 3
handbook, full
pagewidth
TRSTB
TRSDO
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TRLD
MGR602
b. Mode 1
handbook, fullTRCS
pagewidth
TRSTB
TRSDO
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TRLD
MGR603
c. Mode 2
Fig.4 Timing diagrams of the different DAC serial interface modes.
1999 Jun 14
12
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
Basically the 208 bytes of a field segment (187 data bytes,
20 error correcting bytes and one segment sync byte) are
distributed over the remaining 312 data segments.
The FIFO has a depth of two data segments. As the output
data rate is 5.38 MHz we have to distribute 416 bytes, or
two field sync data segments over 312 data segments.
Every MPEG-2 transport packet corresponding to a data
segment gets a delay equal to one 5.38 MHz clock cycle.
Further, every third MPEG-2 transport packet gets an
extra delay of one 5.38 MHz transport packet.
Transport stream interface
The transport stream interface provides an output of 8-bit
parallel MPEG-2 transport packets at a data rate of
5.38 Mbytes/s.
IMPLEMENTATION
The transport interface consists of a FIFO, which has two
tasks:
1. Removal of the field sync segment from the generation
of output data
EXTERNAL INTERFACE
2. Increase of the data rate of the de-randomizer from
2.69 to 5.38 MHz.
Table 4
TDA8960
The transport stream consists of four signals and one data
bus as shown in Table 4.
Transport stream interface
NAME
FUNCTION
DATACLK
output clock
DATAVALID
valid demodulator output data or one valid MPEG transport packet
DATA[7 to 0]
output data stream (8-bit wide output bus)
SOP
indicates the start of a packet. It goes HIGH at the start of a packet and remains HIGH
during the first byte of the packet, the so called sync byte
ERROR
a transport packet error indicator, which is HIGH for each 188 byte transport packet in
which the Reed Solomon decoder found more errors than it could correct
FUNCTIONAL DESCRIPTION
The timing of the transport stream interface signals is shown in Fig.5.
185.9 ns
handbook, full pagewidth
DATACLK
77.5 µs
DATAVALID
188 bytes/34.9 µs
DATA7 to DATA0
00H
MPEG-2
sync byte
00H
sync
185.9 ns
SOP
188 bytes/34.9 µs
ERROR
MGR604
Fig.5 Timing diagram of the transport interface (normal mode).
1999 Jun 14
13
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
• If the Reed Solomon decoder is unable to correct all
errors in a transport packet
The DATACLK signal is the 5.38 MHz demodulator output
clock. It is derived from the system clock of 21.52 MHz.
A few remarks can be made about the DATACLK signal:
• After a reset has been applied, the ERROR signal is
asserted; it remains HIGH until a valid transport packet
is produced by the demodulator
• If a reset is applied, DATACLK becomes LOW; it
remains LOW until reset is released and the symbol
timing recovery block has detected the synchronization
signals
• If the demodulator is out of sync, thus can not detect the
field sync and segment sync in the incoming data
stream.
• After a channel change the DATACLK signal stops; it
starts again after the system has been locked on to a
valid signal
The ERROR signal can be asserted in the middle of a
transport packet.
• If the Reed Solomon decoder produces an invalid
transport packet and the ERROR signal is asserted the
DATACLK signal continues to change state
Sync byte and transport error indicator
• If the sync recovery block is not able to detect the field
sync or data segment sync, DATACLK will not change.
The structure of a transport packet header is shown in
Fig.6. For the VSB demodulator only the first two bytes of
the so called transport packet header are important.
The DATAVALID signal indicates valid demodulator output
data or one valid MPEG-2 transport packet. It is active
HIGH for 188 bytes, or 34.9 µs. The zero bytes to be sent
after the 188 valid bytes of the transport packet can be
considered to be zeroed parity bytes.
The first byte in each header of a transport packet is the so
called MPEG-2 packet synchronization byte (sync byte).
As specified in the MPEG-2 standard, this sync byte must
have the same value for all packets. The VSB demodulator
IC sets this byte for each outgoing transport packet to 47H.
SOP or start of packet signal is HIGH during the first byte
of the packet.
The MSB of the second byte in the transport packet is the
transport_error_indicator bit. It indicates that the Reed
Solomon decoder was not able to correct all errors and the
transport packet has invalid data.
The ERROR signal indicates that the transport packet
contains uncorrectable output. The ERROR signal
becomes HIGH in the following situations:
188 bytes
handbook, full pagewidth
adaptation field
(if present)
payload
(if present)
transport packet header
0
1
0
0
0
1
1
1
1st byte
sync byte
4th byte
MSB
LSB
transport_error_indicator
MGR605
Fig.6 The structure of a transport packet header.
1999 Jun 14
14
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
a bypass register and a boundary scan register, four
dedicated pins collectively called the Test Access Port
(TAP) and a TAP controller.
Boundary scan interface
The TDA8960 Test Access Port (TAP) conforms to the
“IEEE 1149.1 Joint Test Action Group (JTAG)” standard.
It is used for board level testing of integrated circuits and
for testing the internals of an integrated circuit. The JTAG
standard defines on-chip test logic, which consists of an
instruction register, a group of test data registers including
Table 5
TDA8960
INSTRUCTION REGISTER
The instruction register consists of four bits without parity.
There are five defined public instructions; see Table 5.
Public instruction codes
INSTRUCTION
CODE
SELECTED DATA REGISTER
BYPASS(1)
1111
bypass (initialized state)
SAMPLE(2)
0001
boundary scan
EXTEST(3)
0000
boundary scan
INTEST(4)
0011
boundary scan
IDCODE(5)
0010
identification or bypass
Notes
1. The bypass instruction provides a minimum length (1-bit) serial path between the TDI and TDO pins when no test
operation is required.
2. This instruction can be used to take a sample of the inputs and outputs during normal operation of the component.
It can also be used to preload data values into the latched outputs of the boundary scan register.
3. This instructions allows testing off-chip circuitry and board level interconnections.
4. This instruction allows low speed, static testing of the on-chip logic. It can also be used after the chip is mounted on
a printed circuit board.
5. This instruction will return the manufacturer ID, part number code and version code. For the TDA8960 the
manufacturer ID is ‘B00000010101’, the part number code is ‘SVSB’ and the version code is ‘D1’.
In addition three private instructions are implemented to control different test modes; see Table 6.
Table 6
Private instruction codes
INSTRUCTION
CODE
SCAN_TEST
1000
test on-chip scan chains
BIST_TEST
1001
BIST test of de-interleaver RAM
RAM_TEST
1010
scan test of the on-chip memories
CHAR_MODE
1011
characterization mode
In the characterization mode the IC is scan-testable in the
same way as in the scan test mode. However the outputs
are not switched to the scan chain outputs. The outputs
retain their functionality. It is now possible to scan test
pattern through the logic and to verify if the timing
constrains at the outputs are met.
1999 Jun 14
TEST MODE
EXTERNAL INTERFACE
The TAP consists of five pins as shown in Table 7.
15
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
Table 7
TDA8960
TAP external interface
SIGNAL
TYPE
DESCRIPTION
TMS
I
test mode select
TCK
I
test clock
TDI
I
test data input
TDO
O
test data output
TRST
I
test asynchronous reset
OPERATION
The TAP controller is a finite state machine. It selects a
JTAG instruction or a data register to store the input based
on the TMS signal, receives instructions and data on the
TDI pin, executes the instruction when triggered by TMS,
and shifts data out of TDO.
I2C-BUS
MASTER
TCK provides the clock signal for the test logic required by
the standard. TCK is asynchronous to the system clock.
Stored devices in the JTAG controller must retain their
state indefinitely when TCK is stopped at logic 0.
TDA8960
Rpu
Rpu
SCL
SDA
The signal received at TMS is decoded by the TAP
controller to control test functions. The logic is required to
sample TMS at the rising edge of TCK.
MGR606
Fig.7 Typical I2C-bus system implementation.
Serial test instructions and test data are received at TDI.
The TDI signal is required to be sampled at the rising edge
of TCK. When test data is shifted from TDI to TDO, the
data must appear without inversion at TDO after a number
of rising and falling edges of TCK, determined by the
length of the instruction or test data register selected.
EXTERNAL INTERFACE
The I2C-bus interface consists of four signals as shown in
Table 8.
Table 8
TDO is the serial output for test instructions and data from
the TAP controller. Changes in the state of TDO must
occur after the falling edge of TCK. This is because
devices connected to TDO are required to sample TDO at
the rising edge of TCK. The TDO driver must be in an
inactive state (i.e. TDO line must be flat) except when the
scanning of data is in progress.
I2C-bus external interface
SIGNAL
TYPE
DESCRIPTION
I/O
I2C-bus
serial data
I
I2C-bus
clock
A0
I
I2C-bus
slave address bit 0
A1
I
I2C-bus slave address bit 1
SDA
SCL
I2C-bus interface
The TDA8960 has 3.3 V I/O and I2C-bus pins. Therefore,
in a complete system some circuitry might be necessary to
allow ICs with different supply voltages to communicate
and be controlled. This has been described in an
application report available from Philips Semiconductors
(application report “AN97055”, issued 1997 Aug 04).
The I2C-bus interface is used to write control information to
and read low-speed diagnostic information from the
TDA8960. The key features of the I2C-bus interface are:
• I2C-bus data rate up to 400 kbits/s
• Support for only 7-bit addressing and the possibility of
modifying the slave address externally.
A typical system using the I2C-bus interface is illustrated in
Fig.7. The TDA8960 is connected as a slave to a master
through SCL and SDA. Note that the bus has one pull-up
resistor for each of the clock and data lines.
1999 Jun 14
VDD
handbook, halfpage
16
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
The slave address of the device is shown in Table 9. Bits
0 to 6 are predefined, but bits 0 and 1 can be set using the
external pins A0 and A1.
ADDRESSING THE DEVICE
Addressing the VSB demodulator over the system the
I2C-bus requires that the 7-bit slave address (A6 to A0) of
the device is sent over the bus in accordance with the
protocols, together with the R/W bit equal to logic 1 or 0 to
write or read data respectively.
Table 9
TDA8960
Slave address
A6
A5
A4
A3
A2
A1
A0
R/W
0
0
0
1
1
A1
A0
0 = write
1 = read
handbook, full pagewidth
(1)(2)
S
(1)
SLAVE ADDRESS
(1)(3)
R/W
(4)(5)
A
(1)
DATA
(4)(5)
A
(1) (4)(5)(6)
DATA
(8)
(1)
(2)
(3)
(4)
From master to slave
S = START condition
Logic 0 (write)
From slave to master
(5)
(6)
(7)
(8)
A/A
(1)(7)
P
MGR607
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
P = STOP condition
Data transferred (n bytes + acknowledge).
Fig.8 A master-transmitter addresses a slave receiver with a 7-bit address (write access).
A write operation is shown in Fig.8. After the START
condition, the slave address followed by the R/W bit is
transmitted. The receiver, the TDA8960, sends an
acknowledge and the transmitter starts sending the
register values. After each received byte, the TDA8960
sends an acknowledge. The transfer stops if the TDA8960
does not acknowledge the transfer and/or the master
sends a STOP condition.
In Table 11 the default values are given for a number of
reserved addresses and reserved bits of certain
addresses. These correct default values have to be written
in order to prevent unexpected behaviour of the IC.
Figure 9 shows a read operation. The master sends a
START condition followed by the slave address and the
R/W bit is set to logic 1. The slave returns an acknowledge
followed by the value of the first address. The master
sends another acknowledge and the next value of the
address is returned. If the master transmits a STOP
condition after the acknowledge, the transfer is stopped.
Up to three consecutive addressed (00H to 03H) can be
read.
If register 08H has to be written to, eight consecutive bytes
are written. The first corresponds to register 01H, the
second to 02H and so on. The TDA8960 will
auto-increment the accessed address automatically. Up to
ten consecutive addresses can be written.
1999 Jun 14
17
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
(1)(2)
handbook, full pagewidth
S
(1)
SLAVE ADDRESS
(1)(3)
R/W
TDA8960
(4)(5)
(4)
A
(1)(5)
DATA
A
(4)
DATA
(8)
(1)
(2)
(3)
(4)
From master to slave.
S = START condition.
Logic 1 (read).
From slave to master.
(5)
(6)
(7)
(8)
(1)(6)
(1)(7)
A
P
MGR608
A = acknowledge (SDA LOW).
A = not acknowledge (SDA HIGH).
P = STOP condition.
Data transferred (n bytes + acknowledge).
Fig.9 A master-transmitter addresses a slave receiver with a 7-bit address (read access).
Table 10 I2C-bus control register overview (write); note 1
FUNCTION
ADDRESS
Operation
00H
Reserved
01H
Reserved
02H
Operation
03H
Reserved
04H
Reserved
05H
Reserved
06H
Reserved
07H
Carrier recovery
08H
Timing recovery
09H
D7
D6
D5
D4
D3
D2
D1
D0
GNRL_RST
INITIAL_RST
AGC_THRES
AD_FMT
CR_INV
INTMOD
Note
1. Do not write past address 09H.
Table 11 I2C-bus control registers (default settings after reset)
FUNCTION
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Operation
00H
0
0
0
0
0
0
0
0
Reserved
01H
0
0
0
0
0
0
0
0
Reserved
02H
0
0
0
0
0
1
0
0
Operation
03H
0
0
0
0
0
0
0
0
Reserved
04H
0
0
0
0
0
0
1
0
Reserved
05H
1
0
0
0
0
0
0
0
Reserved
06H
0
0
0
0
0
0
0
0
Reserved
07H
1
1
0
0
1
0
1
0
Carrier recovery
08H
0
0
0
0
0
1
0
0
Timing recovery
09H
0
0
0
0
0
0
0
0
1999 Jun 14
18
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
Table 12 I2C-bus diagnostic registers overview (read); note 1
FUNCTION
ADDRESS
D7
D6
D5
D4
D3
D2
D1
EQ_LOCK_INDICATOR
Operation
00H
LOCK_INDICATOR
Equalizer
01H
MSE[15 to 8]
02H
MSE[7 to 0]
03H
CR_OFFSET[7 to 0]
Carrier
recovery
D0
Note
1. Do not read past address 03H.
Table 13 I2C-bus control registers (write); notes 1 and 2
ADDRESS
00H
03H
08H
09H
FUNCTION
operation
operation
carrier
recovery
timing
recovery
COMMENTS
BIT
FIELD NAME
reserved
7 to 2
general reset
(note 1)
1
initial reset
(note 2)
0
reserved
7 to 4
AGC threshold
value
3 to 0 AGC_THRES
reserved
7 to 4
A/D input
format
3
AD_FMT
inverted
spectrum
2
CR_INV
reserved
1 to 0
reserved
7 to 6
DAC interface
mode
5 to 4 INT_MOD
GNRL_RESET
VALUE
0 = disable
1 = enable
INITIAL_RESET 0 = disable
1 = enable
0 = twos complement
1 = binary
0 = pilot at 8.07 MHz
1 = pilot at 2.69 MHz
00 = mode 0 (TRLD not used)
01 = mode 1 (TRCS not used)
10 = mode 2 (TRCS and TRLD are used)
11 = mode 3 (TRLD not used; negative dF/dV
reserved
3 to 0
Notes
1. Operating modes and control parameters are reset to their initial values.
2. Operating modes and control parameters are not affected.
1999 Jun 14
19
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
Table 14 I2C-bus diagnostic registers (read)
ADDRESS
00H
01H
FUNCTION
operation
equalizer
COMMENTS
BIT
reserved
7 to 3
sync recovery lock indicator
2
LOCK_INDICATOR
equalizer lock indicator
1
EQ_LOCK_INDICATOR
reserved
0
equalizer mean square error value 15 to 8
02H
03H
carrier recovery
FIELD NAME
carrier recovery offset
MSE
7 to 0
MSE
7 to 0
CR_OFFSET
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDDD
digital supply voltage
3.0
3.3
3.6
VI
input voltage on any pin with respect
to digital ground (VSSD)
−0.5
−
VDDD + 0.5 V
V
II
DC current into any input
−
−
tbf
mA
IO
DC current out of any output
−
−
tbf
mA
Tj
junction temperature
0
−
105
°C
Tstg
storage temperature
−
−
−
°C
Tamb
ambient temperature
−20
+25
+70
°C
Ptot
total power dissipation
−
1.0
−
W
Ves
electrostatic handling
note 1
−3000
−
+3000
V
note 2
−300
−
+300
V
Notes
1. Human body model: C = 100 pF; R = 1.5 kΩ; 3 zaps positive and 3 zaps negative.
2. Machine model: C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and 3 zaps negative.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1999 Jun 14
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
in free air
20
VALUE
UNIT
55
K/W
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
DC CHARACTERISTICS
VDDD = 3.3 V; VSSD = 0 V; Tamb = 25 °C; unless otherwise specified; note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDD
digital supply voltage
3.0
3.3
3.6
V
IDDD
digital supply current
−
300
−
mA
VIL
LOW-level input voltage
−
−
0.8
V
VIH
HIGH-level input voltage
2.0
−
−
V
ILI
input leakage current
−
−
1
µA
Ci
input capacitance
8
−
25
pF
VOL
LOW-level output voltage
−
−
0.4
V
VOH
HIGH-level output voltage
2.4
−
−
V
IOL
LOW-level output current
−
−
4
mA
Inputs
Output
3-state output, pin AGCOUT
IO(Z)
high-impedance output current
−
−
1
µA
CO(Z)
high-impedance output
capacitance
−
−
100
pF
−
0.3VDDD
V
I2C-bus, pins SDA and SCL
VIL
LOW-level input voltage
−0.5
VIH
HIGH-level input voltage
0.7VDDD
−
VDDD + 0.5 V
VOL
LOW-level output voltage
0
−
0.4
V
VOH
HIGH-level output voltage
note 2
−
−
3.3
V
IOL
LOW-level output current
VOL = 0.4 V
3
−
−
mA
IL
leakage current
VI = VSSD or VDDD
−
−
±10
µA
Ci
input capacitance
VI = VSSD
−
−
8
pF
Notes
1. All supply connections must be made to the same external power supply unit.
2. Open-drain output, determined by VDDD via an external pull-up resistor.
1999 Jun 14
21
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
AC CHARACTERISTICS
VDDD = 3.3 V; VSSD = 0 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock (pin CLK)
fclk(sys)
system clock frequency
−
21.52
−
MHz
tCLKH
system clock HIGH time
−
21.23
−
ns
tCLKL
system clock LOW time
−
21.23
−
ns
note 1
A/D interface (pins ADIN[9 to 0])
tsu(A/D)
A/D interface set-up time
5
−
−
ns
th(A/D)
A/D interface hold time
5
−
−
ns
DAC interface (pins TRSDO, TRCS, TRLD and TRSTB); see Fig.13
tsu(D/A)
D/A interface set-up time
−
40
−
ns
th(D/A)
D/A interface hold time
−
0
−
ns
Transport stream interface (pins DATA[7 to 0], SOP, ERROR and DATAVALID); see Fig.14
tsu(D)
transport interface data set-up time
5
−
−
ns
th(D)
transport interface data hold time
5
−
−
ns
tDATACLKL
transport interface DATACLK LOW
time
180
−
−
ns
tDATACLKH
transport interface DATACLK HIGH
time
180
−
−
ns
tDATCLKW
transport interface DATACLK period
371.7
−
−
ns
tDAT-VAL
transport interface DATA to
DATAVALID, ERROR and SOP
0
−
−
ns
I2C-bus (pins SDA and SCL); see Fig.10
fSCL
SCL clock frequency
0
−
400
kHz
tBUF
bus free time between a STOP and
START condition
1.3
−
−
µs
tHD;STA
hold time (repeated) START
condition; after this period the first
clock pulse is generated
0.6
−
−
µs
tLOW
LOW period of the SCL clock
1.3
−
−
µs
tHIGH
HIGH period of the SCL clock
0.6
−
−
µs
tSU;STA
set-up time for a repeated START
condition
0.6
−
−
µs
tSU;STO
set-up time for STOP condition
0.6
−
−
µs
tHD;DAT
data hold time
0
−
0.9
µs
tSU;DAT
data set-up time
100
−
−
ns
tSP
pulse width of spikes which must be
suppressed by the input filter
tbf
−
tbf
ns
tr
rise time of both SDA and SCL
signals
300
ns
1999 Jun 14
20 + 0.1Cb −
note 2
22
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
SYMBOL
PARAMETER
tf
fall time of both SDA and SCL
signals
Cb
capacitive load for each bus line
TDA8960
CONDITIONS
note 1
MIN.
TYP.
MAX.
UNIT
20 + 0.1Cb −
300
ns
−
−
400
pF
JTAG interface (pins TDO, TDI, TCK, TMS and TRST); see Fig.11
td(TCK-TDO) pin TCK to TDO valid delay
2
−
10
ns
tsu(i)(TCK)
input set-up time to TCK
10
−
−
ns
th(i)(TCK)
input hold time from TCK
2
−
−
ns
23
−
−
ns
Reset (pin RSTAN)
tsu(PO)L
power-on set-up time LOW
Notes
1. The chip clock (CLK) comes from a VXCO controlled by the external DAC. The control loop keeps the clock signal
constant at a frequency twice the symbol rate.
2. Cb = total capacitance of one bus line in pF.
1999 Jun 14
23
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t LOW
t BUF
tr
tf
t HD;STA
t SP
Philips Semiconductors
ATSC 8-VSB demodulator and decoder
1999 Jun 14
SDA
24
SCL
S
t HD;DAT
t SU;DAT
t HIGH
t SU;STA
MBC611
P
Preliminary specification
Fig.10 I2C-bus timing diagram.
t SU;STO
Sr
TDA8960
handbook, full pagewidth
t HD;STA
P
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
handbook, full pagewidth
TDA8960
TCK
td(TCK-TDO)
tsu(i)(TCK)
TDO
th(i)(TCK)
valid
MGR609
Fig.11 JTAG I/O timing.
Tcy(CLK)
handbook, full pagewidth
CLK
tsu(ADIN)
th(ADIN)
ADIN9 to ADIN0
valid
MGR610
Tcy(clk) = 46.47 ns.
Fig.12 Input timing.
handbook, full pagewidth
TRSTB
tsu(D/A)
th(D/A)
TRSDO
valid
MGR611
Fig.13 Serial D/A converter interface I/O timing.
1999 Jun 14
25
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
tDATCLKW
tDATACLKH
tDATACLKL
handbook, full pagewidth
DATACLK
tsu(D)
th(D)
valid
DATA7 to DATA0
tDAT-VAL
ERROR
VALID
SOP
valid
MGR612
Fig.14 Transport interface timing.
1999 Jun 14
26
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
APPLICATION INFORMATION
AGC
handbook, full pagewidth
terrestial/cable
UHF/VHF
TUNER
LOW
IF
A/D
CONVERTER
TDA8960
MPEG
transport stream
21.52 MHz
VCXO
D/A
CONVERTER
I2C-BUS
CONTROLLER
I2C-bus
MGR597
Fig.15 Front-end unit for reception of 8-VSB signals.
1999 Jun 14
27
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
c
y
X
51
A
33
52
32
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
20
64
detail X
19
1
ZD
w M
bp
e
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.20
0.25
0.05
2.90
2.65
0.25
0.50
0.35
0.25
0.14
20.1
19.9
14.1
13.9
1
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.2
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-02-04
97-08-01
SOT319-2
1999 Jun 14
EUROPEAN
PROJECTION
28
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
• For packages with leads on two sides and a pitch (e):
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 Jun 14
TDA8960
29
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Jun 14
30
Philips Semiconductors
Preliminary specification
ATSC 8-VSB demodulator and decoder
TDA8960
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Jun 14
31
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA 66
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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
545004/01/pp32
Date of release: 1999 Jun 14
Document order number:
9397 750 04248