PHILIPS PCA9544PWDH

INTEGRATED CIRCUITS
PCA9544
4-channel I2C multiplexer and interrupt
controller
Product specification
Supersedes data of 1999 Apr 01
1999 Oct 07
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
PCA9544
FEATURES
• 1-of-4 bi-directional translating multiplexer
• Channel selection via I2C bus
• Operating supply voltage 2.5 to 3.6 V
• Operating temperature range 0°C to 70°C
• Power-up with all multiplexer channels deselected
• 3 address pins, allowing up to 8 devices on the I2C bus
• Low on resistance
PIN CONFIGURATION
A0 1
20 VDD
A1 2
19 SDA
A2 3
18 SCL
INT0 4
17 INT
SD0 5
16 SC3
SC0 6
15 SD3
INT1 7
14 INT3
DESCRIPTION
SD1 8
13 SC2
The PCA9544 is a 1-of-4 bi-directional translating multiplexer,
controlled via the I2C bus. The SCL/SDA upstream pair fans out to
four SCx/SDx downstream pairs, or channels. Only one SCx/SDx
channel is selected at a time, determined by the contents of the
programmable control register. Four interrupt inputs, one for each of
the SCx/SDx downstream pair, are provided. One interrupt output,
which acts as an AND of the four interrupt inputs, is provided. All I/O
pins are 5 V tolerant.
SC1 9
12 SD2
VSS 10
11 INT2
SW00373
PIN DESCRIPTION
The pass gates of the multiplexer are constructed such that the VDD
pin can be used to limit the maximum high voltage which will be
passed by the PCA9544. This allows the use of different bus
voltages on each SCx/SDx pair, so that 3.3 V parts can
communicate with 5 V parts without any additional protection.
External pull-up resistors can pull the bus up to the desired voltage
level for this channel.
PIN
NUMBER
SYMBOL
1
A0
Address input 0
2
A1
Address input 1
3
A2
Address input 2
4
INT0
Interrupt input 0
5
SD0
Serial data 0
6
SC0
Serial clock 0
7
INT1
Interrupt input 1
8
SD1
Serial data 1
9
SC1
Serial clock 1
10
VSS
Supply ground
FUNCTION
11
INT2
Interrupt input 2
12
SD2
Serial data 2
13
SC2
Serial clock 2
14
INT3
Interrupt input 3
15
SD3
Serial data 3
16
SC3
Serial clock 3
17
INT
Interrupt output
18
SCL
Serial clock line
19
SDA
Serial data line
20
VDD
Supply voltage
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
20-Pin Plastic TSSOP
0°C to +70°C
PCA9544 PW DH
SOT360-1
1999 Oct 07
2
853–2178 22487
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
PCA9544
BLOCK DIAGRAM
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
VSS
VDD
POWER-ON
RESET
A0
SCL
SDA
INPUT
FILTER
I2C-BUS
CONTROL
A1
A2
INT[0–3]
INT LOGIC
INT
SW00379
1999 Oct 07
3
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
PCA9544
CHANNEL SELECTION
INTERRUPT HANDLING
A SC0x/SD0x downstream pair, or channel, is selected by the
contents of the control register. This register is written after the
PCA9544 has been addressed. The 3 LSBs of the control byte are
used to determine which channel is to be selected. When a channel
is selected, the channel will become active after a stop condition has
been placed on the I2C bus. This ensures that all SCx/SDx lines will
be in a HIGH state when the channel is made active, so that no
false conditions are generated at the time of connection.
The PCA9544 provides 4 interrupt inputs, one for each channel and
one open drain interrupt output. When an interrupt is generated by any
device, it will be detected by the PCA9544 and the interrupt output
will be driven LOW. The channel need not be active for detection of
the interrupt. A bit is also set in the control byte. Bits 4 – 7 of the
control byte correspond to channels 0 – 3 of the PCA9544,
respectively. Therefore, if an interrupt is generated by any device
connected to channel 2, then bit 6 will be set in the control register.
Likewise, an interrupt on any device connected to channel 3 would
cause bit 7 of the control register to be set. The master can then
address the PCA 9544 and read the contents of the control byte to
determine which channel contains the device generating the interrupt.
The master can then reconfigure the PCA9544 to select this
channel, and locate the device generating the interrupt and clear it.
The interrupt clears when the device originating the interrupt clears.
CONTROL BYTE
7
6
5
4
3
2
1
0
SELECTED
CHANNEL
X
X
X
X
X
0
X
X
none
X
X
X
X
X
1
0
0
0 (SC0/SD0)
X
X
X
X
X
1
0
1
1 (SC1/SD1)
X
X
X
X
X
1
1
0
2 (SC2/SD2)
X
X
X
X
X
1
1
1
3 (SC3/SD3)
It should be noted that more than one device can be providing an
interrupt on a channel, so it is up to the master to ensure that all
devices on a channel are interrogated for an interrupt.
7
6
5
4
3
2
1
0
INTERRUPTING
CHANNEL
0
0
0
0
1
X
X
X
X
0 (SC0/SD0)
B0
0
0
1
0
X
X
X
X
1 (SC1/SD1)
0
1
0
0
X
X
X
X
2 (SC2/SD2)
1
0
0
0
X
X
X
X
3 (SC3/SD3)
CONTROL REGISTER
7
6
5
4
INT3 INT2 INT1 INT0
Interrupt bits
(read only)
3
X
2
B2
1
B1
Channel select bits
(read/write)
SW00386
POWER-ON RESET
During power-up, the control register defaults to all zeroes causing
all the channels to be deselected.
1999 Oct 07
4
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
CHARACTERISTICS OF THE I2C-BUS
PCA9544
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 2).
Bit transfer
System configuration
One data bit is transferred during each clock pulse. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (see FIgure 1).
A device generating a message is a ‘transmitter’, a device receiving
is the ‘receiver’. The device that controls the message is the
‘master’ and the devices which are controlled by the master are the
‘slaves’ (see Figure 3).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
SW00363
Figure 1. Bit transfer
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
SW00365
Figure 2. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
I2C
MULTIPLEXER
SLAVE
SW00366
Figure 3. System configuration
1999 Oct 07
5
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
PCA9544
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START condition
SW00368
Figure 4. Acknowledgement on the
slave address
1
1
1
fixed
0
A2
A1 A0
hardware selectable
SW00453
Figure 5. Slave address
1999 Oct 07
6
I2C-bus
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
X
SDA
1
SCL
X
2
X
3
X
4
X
X
5
6
X
7
X
8
X
9
X
1
SLAVE ADDRESS
SDA
S
1
1
1
0
A2
X
2
X
3
PCA9544
X
4
X
5
X
6
X
7
8
9
CONTROL REGISTER
A1
A0
start condition
0
A
R/W
INT3 INT2 INT1 INT0 X
B2
acknowledge
from slave
B1
B0
A
P
acknowledge
from slave
PREVIOUS CHANNEL
NEW CHANNEL
tpv
SW00377
Figure 6. WRITE control register
SLAVE ADDRESS
SDA
S
1
1
start condition
1
0
A2
A1
CONTROL REGISTER
A0
1
R/W
A INT3 INT2 INT1 INT0 X
acknowledge
from slave
B2
last byte
B1
B0
NA
no acknowledge
from master
P
stop condition
SW00378
Figure 7. READ control register
1999 Oct 07
7
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
PCA9544
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).Voltages are referenced to GND (ground = 0 V).
RATING
UNIT
DC supply voltage
–0.5 to +7.0
V
VI
DC input voltage
–0.5 to +7.0
V
II
DC input current
±20
mA
SYMBOL
VDD
PARAMETER
CONDITIONS
IO
DC output current
±25
mA
IDD
Supply current
±100
mA
ISS
Supply current
±100
mA
Ptot
total power dissipation
Tstg
Storage temperature range
Tamb
Operating ambient temperature
400
mW
–60 to +150
°C
0 to +70
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
DC CHARACTERISTICS
VDD = 2.5 to 3.6 V; VSS = 0 V; Tamb = 0°C to +70°C; unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN
TYP
MAX
UNIT
Supply
VDDQn ≤ VDD
Supply voltage
IDD
Supply current
Istb
Standby current
VPOR
Power-on reset voltage
2.5
3.6
V
20
100
µA
–
2.5
100
µA
–
1.3
2.1
V
Operating mode; VDD = 3.6 V;
no load; VI = VDD or VSS;
fSCL = 100 kHz
–
Standby mode; VDD = 3.6 V;
no load; VI = VDD or VSS
VDD = 3.6 V; no load;
VI = VDD or VSS
Input SCL; input/output SDA
VIL
LOW level input voltage
–0.5
–
0.3 VDD
V
VIH
HIGH level input voltage
0.7 VDD
–
6
V
IOL
LOW level out
output
ut current
VOL = 0.4 V
3
–
–
VOL = 0.6 V
6
–
–
VI = VDD or VSS
–1
–
+1
µA
VI = VSS
–
–
13
pF
V
IL
Leakage current
Ci
Input capacitance
mA
Select inputs A0 to A2 / INT0 to INT3
VIL
LOW level input voltage
–0.5
–
+0.3 VDD
VIH
HIGH level input voltage
0.7 VDD
–
VDD + 0.5
V
ILI
Input leakage current
pin at VDD or VSS
–1
–
+1
µA
VCC = 3.67 V, VO = 0.4 V, IO = 15 mA
5
20
30
VCC = 2.3 to 2.7 V, VO = 0.4V, IO = 10 mA
7
26
55
Ω
Pass Gate
RON
Switch resistance
Vswin = VDD = 3.3 V; Iswout = –100 µA
VPass
P
IL
Switch output
out ut voltage
Leakage current
Vswin = VDD = 3.0 to 3.6 V; Iswout = –100 µA
2.2
1.6
Vswin = VDD = 2.5 V; Iswout = –100 µA
2.8
1.5
Vswin = VDD = 2.3 to 2.7 V; Iswout = –100 µA
1.1
VI = VDD or VSS
–1
–
VOL = 0.4 V
3
VI = VDD or VSS
–1
V
2.0
+1
µA
–
–
mA
–
+1
µA
INT Output
IOL
IL
1999 Oct 07
LOW level output current
Leakage current
8
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
PCA9544
AC CHARACTERISTICS
SYMBOL
STANDARD-MODE
I2C-BUS
PARAMETER
MIN
tpd
MAX
SCL clock frequency
tBUF
MIN
UNIT
MAX
0.31
Propagation delay from SDA to SDn or SCL to SCn
fSCL
FAST-MODE I2C-BUS
0.31
ns
0
100
0
400
KHz
Bus free time between a STOP and START condition
4.7
–
1.3
–
µs
Hold time (repeated) START condition
After this period, the first clock pulse is generated
4.0
–
0.6
–
µs
tLOW
LOW period of the SCL clock
4.7
–
1.3
–
µs
tHIGH
HIGH period of the SCL clock
4.0
–
0.6
–
µs
tSU:STA
Set-up time for a repeated START condition
4.7
–
0.6
tHD:DAT
Data hold time:
for CBUS compatible masters
for I2C-bus devices
5.0
02
–
–
–
02
–
0.93
µs
µs
tSU:DAT
Data set-up time
250
–
1004
–
ns
tSU:STO
ns
tHD:STA
µs
Set-up time for STOP condition
–
1000
–
300
tr
Rise time of both SDA and SCL signals
–
300
–
300
ns
tf
Fall time of both SDA and SCL signals
4.0
–
0.6
–
µs
400
–
400
pF
Cb
Capacitive load for each bus line
INT
tiv
INTn to INT active valid time
4
4
µs
tir
INTn to INT inactive delay time
2
2
µs
Lpwr
LOW level pulse width rejection or INTn inputs
1
1
ns
Hpwr
HIGH level pulse width rejection or INTn inputs
500
500
ns
NOTES:
1. Pass gate propagation delay is calculated from the 20Ω typical RON and and the 15pF load capacitance.
2. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. A fast-mode I2C bus device can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line trmax + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode
I2C-bus specification) before the SCL line is released.
5. Cb = total capacitance of one bus line in pF.
SDA
tBUF
tLOW
tR
tF
tHD;STA
tSP
SCL
tHD;STA
P
S
tSU;STA
tHD;DAT
tHIGH
tSU;DAT
Sr
tSU;STO
P
SU00645
Figure 8. Definition of timing on the I2C-bus
1999 Oct 07
9
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
1999 Oct 07
10
PCA9544
SOT360-1
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
NOTES
1999 Oct 07
11
PCA9544
Philips Semiconductors
Product specification
4-channel I2C multiplexer and interrupt controller
PCA9544
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 10-99
Document order number:
1999 Oct 07
12
9397–750–06498