PHILIPS VES1993

VES 1993
SINGLE CHIP
SATELLITE
CHANNEL RECEIVER
FEATURES
APPLICATIONS
• DSS and DVB-S compatible single chip
demodulator & forward error correction.
• Dual 6-bit ADC on chip.
• PLL for crystal frequency multiplication.
• Variable rate BPSK/QPSK coherent
demodulator.
• Modulation rate from 1 to 45MBaud.
• Automatic Gain Control output.
• Digital symbol timing recovery :
Acquisition range up to ±240ppm
• Digital carrier recovery :
Acquisition range up to ±12% of symbol rate
• Half Nyquist baseband filters on chip
roll-off = 0.35 for DVB and 0.2 for DSS
• Channel quality estimation.
• Viterbi decoder :
Supported rates : from 1/2 to 8/9.
Constraint length K = 7
with G1 = 1718 G2 = 1338
VBER measurement provided.
• Convolutional deinterleaver and Reed
Solomon decoder according to DVB and
DSS specifications.
• Automatic Frame Synchronization.
• Selectable DVB-S descrambling.
• I2C bus interface.
• 100-pin MQFP package.
• CMOS technology (0.35 µm 3.3V).
• DSS receivers.
• DVB-S receivers (ETS 300-421).
• Direct Broadcast Satellite (DBS).
DESCRIPTION
The VES 1993 is a single-chip channel receiver for satellite television
reception which matches both DSS and DVB-S standards. The
device contains a dual 6-bit flash analog to digital converter, variable
rate BPSK/QPSK coherent demodulator and Forward Error
Correction functions.The ADCs directly interface with I and Q analog
baseband signals. After A to D conversion, the VES 1993 implements
a bank of cascadable filters as well as antialias and half-Nyquist
filters. Analog AGC signal is generated by an amplitude estimation
function. The VES 1993 performs clock recovery at twice the Baud
rate and achieves coherent demodulation without any feedback to
the local oscillator. Forward Error Correction is built around two error
correcting codes : a Reed-Solomon (outer code), and a Viterbi
decoder (inner code). The Reed-Solomon decoder corrects up to 8
erroneous bytes among the N bytes of one data packet.
Convolutional deinterleaver is located between the Viterbi output and
the R.S. decoder input. De-interleaver and R.S. decoder are
automatically synchronized thanks to the frame synchronisation
algorithm which uses the sync pattern present in each packet. The
VES 1993 is controlled via an I2C bus interface. The circuit operates
up to 91MHz and can process variable modulation rates, up to
45Mbaud.
The VES 1993 provides an interrupt line which can be programmed
on either events or timing information.
Designed in 0.35 CMOS technology and housed in a 100-MQFP
package, the VES 1993 operates over the commercial temperature
range.
comatlas S.A., 30 rue du Chêne Germain, BP 814, 35518 CESSON-SEVIGNE Cedex, FRANCE
Phone : +33 (0)2 99 27 55 55, Fax : +33 (0)2 99 27 55 27, Internet : www.comatlas.fr / VES 1993 rev 2.0 / Jan 99
CAUTION
This document is preliminary and is subject to change. Contact a comatlas,
representative to determine if this is the current information on this device.
The information contained in this document has been carefully checked and is believed to be reliable. However,
comatlas makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible
for any loss or damage of whatever nature resulting from the use of, or reliance upon, it comatlas does not
guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright,
mask work right or other rights of third parties, and no patent or other license is implied hereby.
This document does not in any way extend comatlas warranty on any product beyond that set forth in its standard
terms and conditions of sale. comatlas reserves the right to make changes in the products or specifications, or
both, presented in this publication at any time and without notice.
LIFE SUPPORT APPLICATIONS : comatlas products are not intended for use as critical components in life support
appliances, devices, or systems in which the failure of a comatlas product to perform could be expected to result in
personal injury.
comatlas reserves the right to do any kind of modifications in this datasheet regarding hardware or software
implementations without notice.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p2
FIGURE 1. BLOCK DIAGRAM
1.1 WITH COMPLEX MULTIPLIER AFTER ANTI-ALIASING FILTERS (POSMUL=0) :
.
VAGC
PWM
AGC
ENCODER
DETECTION
I2C
INTERFACE
CARRIER
SYNCHRONIZATION
VIN1
ADC
VIN2
6
HALF
COMPLEX
FILTER BANK
6
NYQUIST
MULTIPLIER
FILTERS
XIN
PLL
SACLK
CLOCK
NCO
SYNCHRONIZATION
VITERBI
DECODER
R-S
DE-INTERLEAVER
DECODER
comatlas reserves the right to make any change at anytime without notice.
DE-SCRAMBLER
DO
OCLK
DEN
VES 1993 rev 2.0 / Jan 99 / p3
1.2 WITH COMPLEX MULTIPLIER BEFORE ANTI-ALIASING FILTERS (POSMUL=1) :
.
VAGC
PWM
AGC
ENCODER
DETECTION
I2C
INTERFACE
CARRIER
SYNCHRONIZATION
VIN1
ADC
VIN2
6
COMPLEX
6
HALF
FILTER BANK
NYQUIST
MULTIPLIER
FILTERS
XIN
PLL
SACLK
CLOCK
NCO
SYNCHRONIZATION
VITERBI
DECODER
R-S
DE-INTERLEAVER
DECODER
comatlas reserves the right to make any change at anytime without notice.
DE-SCRAMBLER
DO
OCLK
DEN
VES 1993 rev 2.0 / Jan 99 / p4
TABLE 1 : ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Unit
Ambient operating temperature (Ta)
0
70
°C
DC supply voltage
- 0.5
+4.1
V
DC input voltage
- 0.5
VDD + 0.5
V
DC input current
mA
± 20
Lead Temperature
+ 300
°C
Junction Temperature
+ 125
°C
Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
TABLE 2: RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Digital supply voltage
Min
3.135
Typ
3.3
Max
3.465
V
3.3V ±5%
VCC
5V supply voltage
4.75
5
5.25
V
pins 22 and 91
Ta
AVD
AVS
VINDC
VINAC
ZIN
VREFP
VREFN
XIN
ZOE (1)
DNL(2)
INL(3)
GE (4)
SINAD (5)
Operating temperature
0
Analog supply voltage
3.135
Analog ground
DC Analog Input
VREFN
AC Analog Input
Analog input impedance 10
Top voltage reference
Bottom voltage reference
Crystal frequency
Zero Offset Error
Differential Non Linearity
Integral Non Linearity
Gain Error
ADC signal to noise ratio
°C
V
V
V
mVpp
Ohms
V
V
MHz
mV
LSB
LSB
mV
dB
Ambient temperature
pin 43
pin 44
pins 41 and 45
pins 41 and 45
pins 41 and 45
pin 46
pin 42
3.3
0
70
3.465
VREFP
750
100
2.0
1.25
0.5
0.8
93
10
0.9
1
10
34
Unit
Notes
@ 1MHz input signal
and 92MHz sampling clock
THD(6)
Total Harmonic Distorsion
35
dB
VIH(7)
High-level input voltage
2
VCC+0.3 V
TTL input
VIL
Low-level input voltage
-0.5
0.8
V
TTL input
VOH(8)
High-level output voltage 2.4
V
@IOH = -2mA to -4mA
VOL(8)
Low-level output voltage
0.4
V
@IOL = + 2 mA to +4mA
IDD
Supply current
8.5
mA/MBaud @XIN = 91MHz
CIN
Input capacitance
15
pF
1MHz input to VSS
COUT
Output capacitance
15
pF
1MHz input to VSS
(1) Zero Offset Error : deviation of voltage input from ideal voltage to get the 00 code.
(2) Differential Non linearity : maximum deviation of the analog span of each output code from its ideal 1lsb value.
(3) Integral Non linearity : deviation of the ADC transfer curve from the ideal transfer curve, defined according to the
best straight line fit method.
(4) Gain Error : Deviation of voltage input from ideal value to get the highest code.
(5) Signal-to-noise plus distortion ratio (SINAD) : ratio between the RMS magnitude of the fundamental input
frequency to the RMS magnitude of all other A/D output signals.
(6) Total harmonic distortion (THD) : ratio of the RMS sum of all harmonics of the input signal (below one half of the
sample rate) to the fundamental.
(7) All inputs are 5V tolerant.
(8) IOH, IOL = ±4mA only for pins : SACLK, OCLK, SDA, SCL_0, SDA_0.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p5
FUNCTIONAL DESCRIPTION
½ PLL
The VES 1993 implements a PLL used as clock multiplier by 1, 2, 3, 4 or 6, so that the crystal can be low
frequency.
½ DUAL 6-BIT ADC
The VES 1993 implements a dual 6-bit ADC. The architecture is a standard flash one based on 63 latched
comparators determining simultaneously the precise analog signal level. No external voltage references are
required to use the ADCs.
½ FILTER BANK
The filter bank contains 2 selectable Anti-Alias lowpath filters (AAF) which, combined with cascadable decimation
filters, allows to perform variable rate demodulation capability over a ratio of up to 45.
½ COMPLEX MUTIPLIER
Coherent data demodulation (BPSK or QPSK) is performed by complex multiplication of the incoming symbol
with the computed correction angle. This leads to a rotation and a stabilization of the PSK constellation when the
algorithms of carrier and clock recovery have both converged.
The position of this complex multiplier is programmable and can be either after antialiasing filters or before any
filtering.
½ HALF NYQUIST FILTERS
Half-Nyquist filtering is performed in each arm of the constellation. 2 programmable roll-off are available
depending on the selected standard. The digital filter has 19 (roll-off 0.35) or 25 (roll-off 0.2) taps to provide an
outband attenuation of 40dB.
½ CARRIER SYNCHRONIZER
The carrier synchronizer block implements successively a phase/frequency comparator, a programmable digital
second order loop filter, a phase accumulator (NCO) that accumulates the phase error and drives a sine/cosine
table to determine the angle for correction, applied to the complex multiplier.
½ CLOCK SYNCHRONIZER
The clock phase detector block implements the algorithm for variable rate digital timing recovery. The digital
second order loop filter is programmable, and provides an 8-bit command to the NCO block for clock recovery.
½ AGC
This block calculates the magnitude of the I and Q channels after Nyquist filtering. This value is then compared to
a programmable threshold value, filtered and PWM encoded before being output on the VAGC pin.
½ VITERBI DECODER
The Viterbi decoder performs a maximum likelihood estimation over the received data on the basis of four-bit
quantized samples of the demodulated signals. The average truncation length is 144. The rate R can be chosen
between R = 1/2 and R = 8/9 (punctured codes). Automatic viterbi rate recovery can be selected, so as
automatic spectral inversion ambiguity resolution. The rate search is performed among rates ½, 2/3, ¾, 5/6 and
7/8 In DVB-S standard and among rates 2/3 and 6/7 in DSS mode. Output Bit Error Rate (VBER) is provided by
the decoder. Differential decoding is selectable. The Viterbi decoder provides decoded data and the
corresponding clock.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p6
FUNCTIONAL DESCRIPTION (Con’t)
½ FRAME SYNCHRONIZATION AND DEINTERLEAVING
The Viterbi decoder provides errors which occur in bursts. The length of some error bursts may exceed that
which can be reliably corrected by the Reed-Solomon decoder. The implemented de-interleaving is a
convolutional one of depth 12 for DVB and 13 for DSS. The first operation consists in synchronizing the deinterleaver. This is accomplished by detecting α consecutive sync Words (or sync ) which are present as the first
byte of each packet.
Next, the RAM memory associated with the de-interleaver fills up and the first deinterleaved bytes are provided
to the input of the Reed-Solomon decoder. The state machine of the de-interleaver goes to the control phase
which counts β consecutive missed sync Words (or sync ) before declaring the system desynchronized and
going back to the sync. phase. α and β are programmable through the I2C interface.
When the inverted sync word is detected at the input of the de-interleaver (π ambiguity at the output of the Viterbi
decoder), the bytes provided to the Reed-Solomon decoder are inverted at the output of the de-interleaver.
½ REED-SOLOMON DECODER
The Reed-Solomon decoder decodes the symbol stream from the de-interleaver according to the (N=204 for
DVB and N=146 for DSS) shortened Reed-Solomon code. Synchronization to Reed-Solomon code is defined
over the finite Galois field GF (28). The field generator polynomial is given by :
G(x) =
15
(x +
i
)
i =0
This Reed-Solomon decoder corrects up to eight erroneous symbols in each block. When the correction
capability of the decoder is exceeded, the block is not changed and is provided as it has been entered. In this
case the flag UNCOR is set and the MSB of the second byte in the MPEG2 frame is forced to one (TEI :
Transport Error Indicator in DVB-S).The correction capability of the RS decoder can be inhibited.
•
DESCRAMBLER (DVB-S)
In order to comply with energy dispersal requirements of radio transmission regulations and to ensure adequate
binary transitions, the MPEG2 frames are scrambled at the encoder side. Dual operation is achieved at the
output of the Reed-Solomon decoder using the same scrambler/descrambler. The polynomial for the pseudo
random binary sequence (PRBS generator is 1 + x14 + x15). The PRBS registers are initialized at the start of
every eight transport packets. To provide an initialization signal for the descrambler, the MPEG2 sync byte of the
first transport packet is inverted from 4716 to B816. When detected, the descrambler is loaded with the initial
sequence "100101010000000". The descrambler can be inhibited. Before being provided, the inverted sync
pattern B816 is reinverted in order to get the original MPEG2 sync word 4716.
•
INTERFACE
The VES 1993 integrates an I2C interface in slave mode. This I2C interface fulfills the Philips component I2C bus
specification.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p7
INPUT – OUTPUT SIGNAL DESCRIPTION
Symbol
CLB#
XIN
XOUT
SACLK
PLLAVS
PLLAVD
I[5:0]
And
Q[5:0]
VAGC
CTRL1
CTRL2
CTRL3
CTRL4
DO[7:0]
Pin Number
78
Type Description
I
The CLB# input is asynchronous and active low, and clears the CAS
1993. When CLB# goes low, the circuit immediately enters its RESET
mode and normal operation will resume 3 XIN rising edges later after
CLB# returned high. The I2C register contents are all initialized to their
default values. The minimum width of CLB# at low level is 3 XIN clock
periods.
97
I
Crystal oscillator input pin. Typically a fundamental XTAL oscillator is
connected between the XIN and XOUT pins. (See typical application
ERROR! REFERENCE SOURCE NOT FOUND. page Error! Bookmark not
defined.).
96
O
Crystal oscillator output pin. Typically a fundamental XTAL oscillator is
connected between the XIN and XOUT pins.
(See typical application
ERROR! REFERENCE SOURCE NOT FOUND. page Error! Bookmark not
defined..)
3
O
SamplingCLocK output. SACLK is nominally a square wave clock with a
maximum of 93 MHz depending on the XTAL connected between XIN
and XOUT and the multiplying factor of the PLL.
SACLK is provided in case an external A/D is used only. When the
internal A/D is used, SACLK is set to 0.
99
I
Analog ground for the PLL.
100
I
Analog positive supply voltage for the PLL. PLLAVD is typically 3.3V.
6,7,8,9,10,11
I
I[5:0] and Q[5:0] are the 6-bit in-phase and quadrature base-band
symbol input signals respectively, coming from an external dual A/D
converter. These signals are sampled on the rising edge of SACLK. The
16,17,18,19,20,
I
input data may be in either offset binary (default) or two’s complement
21
format.(See TABLE 3 page 11).When not used, these 12 pins must be
grounded (use of the internal ADCs).
5
O
PWM encoded output signal for AGC. This signal is typically fed to the
5V
AGC amplifier through a single RC network (see typical application
Error! Reference source not found. page Error! Bookmark not
defined.). The maximum signal frequency on VAGC output is SACLK /
8. The refresh frequency of AGC information is the symbol rate divided
by 2048.
4
O
ConTRoL line output. This output is directly programmable through the
5V
I2C interface. Its default value is a logical "1".
CTRL1 is an open drain output and therefore requires an external pullup resistor to either VDD or VCC.
27
O
ConTRoL line output. This output is directly programmable through the
5V
I2C interface. Its default value is a logical "0". CTRL2 is an open drain
output and therefore requires an external pull-up resistor to either VDD
or VCC.
92
O
ConTRoL Line output. This output is directly programmable through the
5V
I2C interface. Its default value is a logical "0". CTRL3 is an open drain
output and therefore requires an external pull-up resistor to either VDD
or VCC.
87
I/O ConTRoL Line input/output. This pin is directly programmable through
5V
the I2C interface. Its default configuration is an input. A pull-up to VDD
or VCC, or a pull-down resistor to VSS must be connected to CTRL4.
O
Data Output bus . These 8-bit parallel data are the outputs of the VES
56,57,58,
3.3V 1993 after demodulation, Viterbi decoding, de-interleaving, RS decoding
60,64,65,
and de-scrambling. There are 3 possible output interfaces : two parallel
67,68
and one serial (See Error! Reference source not found.,Error!
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p8
Symbol
Pin Number
OCLK
72
DEN
73
UNCOR
74
PSYNC
76
FEL
80
TEST
84
TRST
85
TDO
86
TCK
88
TDI
89
TMS
90
SADDR[2:0]
31,32,33
SDA
36
SCL
37
IICDIV[1:0]
12,15
VIN1
VIN2
VREFN
41
45
42
VREFP
46
AVD
AVS
43
44
Type Description
Reference source not found.,Error! Reference source not found.)
O
Output CLock. OCLK is the output clock for the parallel DO[7:0] outputs.
3.3V OCLK is internally generated depending on which type of interface is
selected.
O
Data ENable : this output signal is high when there is valid data on bus
3.3V DO[7:0].
O
UNCORrectable packet. This output signal goes high on a rising edge of
3.3V OCLK when the provided packet is uncorrectable.
O
Pulse SYNChro. This output signal goes high on a rising edge of OCLK
3.3V each time the first byte of a packet is provided.
O
Front End Locked. This output signal goes high when the demodulator,
5V
the Viterbi decoder and the de-interleaver are all synchronized. FEL is
an open drain output and therefore requires an external pull up resistor
to either VDD or VCC.
I
TEST input. This input pin must be grounded for normal operation of the
VES 1993.
I
Test ReSeT. This active low input signal is used to reset the TAP
controller when in boundary scan mode. In normal mode of operation
TRST must be set low.
O
Test Data Out. This is the serial Test output pin used in boundary scan
5V
mode. Serial Data are provided on the falling edge of TCK.
I
Test ClocK : an independant clock used to drive the TAP controller when
in boundary scan mode. In normal mode of operation, TCK must be
grounded.
I
Test Data In. The serial input for Test data and instruction when in
boundary scan mode. In normal mode of operation, TDI must be set to
GND or VDD.
I
Test Mode Select. This input signal provides the logic levels needed to
change the TAP controller from state to state. In normal mode of
operation, TMS must be set to VDD.
I
SADDR[2:0] input signals are the 3 LSBs of the I2C address of the VES
1993.The MSBs are internally set to 0001. Therefore the complete I2C
address of the VES 1993 is (MSB to LSB) : 0, 0, 0, 1, SADDR[2],
SADDR[1], SADDR[0].
I/O SDA is a bidirectional signal. It is the serial input/output of the I2C
5V
internal block. A pull-up resistor (typically 2.2 k•) must be connected
between SDA and VCC for proper operation (Open Drain output).
I
I2C clock input. SCL should nominally be a square wave with a
maximum frequency of 400 KHz. SCL is generated by the system I2C
master.
I
These pins allow to select the frequency of the I2C system clock,
depending on the crystal frequency. Internal I2C clock is a division of
IICDIV
(IICDIV from 1 to 3) and must be between 6 and 20 MHz.
XIN by 2
I
Analog signal Input for channel I.
I
Analog signal Input for channel Q.
O
Analog negative voltage reference. A decoupling capacitor of typically
0.1mF must be placed as closed as possible between VREFP and
VREFN. The typical voltage value at VREFN is 1.25V.
O
Analog positive voltage reference. A decoupling capacitor of typically 0.1
µF must be placed as closed as possible between VREFP and VREFN.
The typical voltage value at VREFP is 2V.
I
Analog positive supply voltage. AVD is typically 3.3V.
I
Analog ground voltage. A 0.1µF decoupling capacitor must be placed
between AVD and AVS.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p9
Symbol
SCL_0
Pin Number
28
SDA_0
29
TO[7:0]
INT
53,55,59,62,
66,69,75,77
79
22K_0
82
XINDIV
26
PWMO
25
IDDQ
GND
30
1,13,24,34,
47,50,63,70,
83,93,95
2,14,23,35,
48,49,61,71,
81,94,98
22, 91
VDD
VCC
Type Description
O
This output is equivalent to the SCL input, but can be tristated by I2C
5V
programmation. A pull-up resistor (typically 22KΩ) must be connected
between this pin and VCC.
I/O This signal is equivalent to the SDA I/O of the VES 1993 but can be
5V
tristated by I2C programmation. SDA_0 is bidirectionnal. A pull-up
resistor (typically 22KΩ) must be connected between this pin and VCC.
O
TO[7:0] is a dedicated Test output bus used to test the VES 1993. In
3.3V normal mode of operation, these 8 outputs are set to 0.*
O
INTerrupt line output. This active low output interrupt line can be
5V
configured by the I2C interface. INT is an open drain output and
therefore requires an external pull-up resistor to either VDD or VCC.
O
This output pin provides the 22KHz used to control the antena LNB. This
5V
output is controlled via the I2C interface.
O
This clock output pin is a division of the crystal frequency by a factor
5V
programmable from 1 to 15 through the I2C interface (index 39).
O
This output pin is a programmable PWM signal. It can be used as an
5V
analog control signal, which value can be programmed through the I2C
interface (index 38). The maximum frequency on VAGC output is
SACLK / 8.
I
Test input pin. Must be grounded.
I
Digital ground voltage.
I
Digital 3.3V supply voltage.
I
Digital 5V supply voltage.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p10
TABLE 3. I,Q INPUT FORMAT
This table is to be used with an external 6-bit ADC.
Offset binary
2’s complement
(IFS = 0)
(IFS = 1)
111111
011111
110000
010000
101111
001111
101110
001110
100001
000001
100000
000000
011111
111111
011110
111110
010001
110001
010000
110000
001111
101111
000000
100000
+1
zero
-1
Note : (+1) and (-1) levels correspond to AGCR[4:0] set to B16.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p11
TABLE 5. PUNCTURING AND MAPPING
Rate
½
R
000
2/3
001
¾
010
4/5
011
5/6
100
6/7
101
7/8
110
8/9
111
Inhibition Flags
inh[0] = 1
inh[1] = 1
inh[0] = 10 10
inh[1] = 11 11
inh[0] = 101
inh[1] = 110
inh[0] = 1000 1000
inh[1] = 1111 1111
inh[0] = 10101
inh[1] = 11010
inh[0] = 100101 100101
inh[1] = 111010 111010
inh[0] = 1000101
inh[1] = 1111010
inh[0] = 10001011 10001011
inh[1] = 11110100 11110100
Mapping
I = X1
Q = Y1
I = X1Y2Y3
Q = Y1X3Y4
I = X1Y2
Q = Y1X3
I = X1Y2Y4Y5Y7
Q = Y1Y3X5Y6Y8
I = X1Y2Y4
Q = Y1X3X5
I = X1Y2X4X6Y7Y9Y11
Q = Y1Y3Y5X7Y8X10 X12
I = X1Y2X4Y6
Q = Y1Y3X5X7
I = X1Y2Y4Y6X8Y9Y11X13X15
Q = Y1Y3X5X7X9Y10Y12Y14X16
Notes :
1.Polynomial X is G1=171 inhibited with inh[0]
2.Polynomial Y is G2=133 inhibited with inh[1]
3.In DVB and RAUTO modes, the only Viterbi rates that the internal state machine will look for synchronization are :
1/2, 2/3, 3/4, 5/6 and 7/8.
4.In DSS and RAUTO modes, the only Viterbi rates that the internal state machine will look for synchronization are :
2/3 and 6/7.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p12
FIGURE 2. BLOCK DIAGRAM
VCC
XIN
VDD
11
XOUT
XTAL
GND VREFP VREFN
11
SCL_O
POWER SUPPLIES
SDA_O
SACLK
VAGC
PWMO
CTRL1
CTRL2
CTRL3
CTRL4
6
I[5:0]
Q[5:0]
VIN1
6
VES1993
INPUTS
VIN2
CLB#
TEST
IDDQ
IICDIV[1:0]
OUTPUTS
INTERFACE
8
8
JTAG
FEL
PSYNC
UNCOR
DEN
OCLK
INT
22K_O
DO[7:0]
TO[7:0]
XINDIV
3
SADDR[2:0] SCL SDA
TDO TDI TMS TCK TRST
FIGURE 3. PIN DIAGRAM (100 MQFP)
GND
VDD
SACLK
CTRL1
VAGC
I5
I4
I3
I2
I1
I0
1
5
10
15
VDD
GND
IICDIV1
GND
VDD
IICDIV0
20
100
95
VES1993
40
VIN1
VREFN
AVD
AVS
VIN2
VREFP
GND
VDD
Q5
Q4
Q3
Q2
Q1
Q0
25
NC
NC
VCC
VDD
GND
35
30
VDD
SDA
SCL
NC
IDDQ
31
PWMO
XINDIV
CTRL2
SCL_O
SDA_O
SADDR2
SADDR1
SADDR0
GND
90
PLLAVD
PLLAVS
VDD
XIN
XOUT
GND
VDD
GND
CTRL3
VCC
TMS
TDI
TCK
CTRL4
TDO
45
85
50
81
22K_O
VDD
80
75
70
65
60
55
51
FEL
INT
CLB#
TO[0]
PSYNC
TO[1]
UNCOR
DEN
OCLK
VDD
GND
TO[2]
DO0
DO1
TO[3]
DO2
DO3
GND
TO[4]
VDD
DO4
TO[5]
DO5
DO6
NC
DO7
TO[6]
TO[7]
NC
NC
comatlas reserves the right to make any change at anytime without notice.
TRST
TEST
GND
VES 1993 rev 2.0 / Jan 99 / p13
TABLE 6. PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Pin Name
GND
VDD
SACLK
CTRL1
VAGC
I5
I4
I3
I2
I1
I0
IICDIV1
GND
VDD
IICDIV0
Q5
Q4
Q3
Q2
Q1
Q0
VCC
VDD
GND
PWMO
XINDIV
CTRL2
SCL_0
SDA_0
IDDQ
SADDR2
SADDR1
SADDR0
Type
O
OD
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
OD
O
I/O
I
I
I
I
Pin
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Pin Name
GND
VDD
SDA
SCL
NC
NC
NC
VIN1
VREFN
AVD
AVS
VIN2
VREFP
GND
VDD
VDD
GND
NC
NC
TO[7]
NC
TO[6]
DO7
DO6
DO5
TO[5]
DO4
VDD
TO[4]
GND
DO3
DO2
TO[3]
Type
I/O
I
I
O
I
O
O
O
O
O
O
O
O
O
O
O
O
Pin
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name
DO1
DO0
TO[2]
GND
VDD
OCLK
DEN
UNCOR
TO[1]
PSYNC
TO[0]
CLB#
INT
FEL
VDD
22K_0
GND
TEST
TRST
TDO
CTRL4
TCK
TDI
TMS
VCC
CTRL3
GND
VDD
GND
XOUT
XIN
VDD
PLLAVS
PLLAVD
Type
O
O
O
O
O
O
O
O
O
I
OD
OD
O
I
I
O
I/O
I
I
I
OD
O
I
O
O
Notes :
1.All inputs (I) are TTL, 5V tolerant inputs
2.OD are Open Drain 5V outputs, so they must be connected to a pull-up resistor to either VDD or VCC
3. NC pins are non connected pins. They can be grounded.
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 2.0 / Jan 99 / p14
comatlas S.A, 30 rue du Chêne Germain, BP 814, 35518 CESSON SEVIGNE CEDEX – France
Tel : +33 2 99 27 55 55, Fax : +33 2 99 27 55 27, Internet : www.comatlas.fr, e-mail : [email protected]
comatlas reserves the right to make any change at anytime without notice.
VES 1993 rev 1.0 / Nov 98 / p15